TPIC1321L TI1 | Alldatasheet
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/C0084/C0080/C0073/C0067/C0049/C0051/C0050/C0049/C0076 /C0051/C0262/C0072/C0065/C0076/C0070/C0032/C0072/C0262/C0066/C0082/C0073/C0068/C0071/C0069/C0032/C0071/C0065/C0084/C0069/C0262/C0080/C0082/C0079/C0084/C0069/C0067/C0084/C0069/C0068/C0032/C0076/C0079/C0071/C0073/C0067/C0262/C0076/C0069/C0086/C0069/C0076 /C0080/C0079/C0087/C0069/C0082/C0032/C0068/C0077/C0079/C0083/C0032/C0065/C0082/C0082/C0065/C0089 SLIS042 − NOVEMBER 1994 /C0261 Copyright 1994, Texas Instruments Incorporated 2−1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
- Low rDS(on) . . . 0.35 Ω Typ
- Voltage Output...6 0 V
- Input Protection Circuitry... 1 8 V
- Pulsed Current...4 A Per Channel
- Extended ESD Capability. . . 4000 V
- Direct Logic-Level Interface
description
The TPIC1321L is a monolithic gate-protected logic-level power DMOS array that consists of six electrically isolated N-channel enhancement- mode DMOS transistors configured as 3-half H-bridges. Each transistor features integrated high-current zener diodes (Z CXa and ZCXb ) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor. The TPIC1321L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature of −40°C to 125°C. schematic DRAIN3 Z1 Z3 Z4 Z6 GND GATE3 GATE6 OUTPUT3 DRAIN1 GATE1 OUTPUT1 GATE4 Q4 Q6 SOURCE6SOURCE4 OUTPUT2 GATE5 GATE2 DRAIN2 14, 1521, 22 1, 24 3, 4 11, 12 8, 9 5, 6 19, 2016 17, 18 D4 D5 NOTE A: For correct operation, no terminal may be taken below GND. ZC1b ZC1a ZC4b ZC4a ZC2b ZC2a ZC5b ZC5a ZC3b ZC3a ZC6b ZC6a OUTPUT1 GATE4 SOURCE4 SOURCE4 GND GND GATE5 SOURCE6 SOURCE6 GATE6 OUTPUT3 OUTPUT3 OUTPUT1 GATE1 DRAIN1 DRAIN1 DRAIN2 DRAIN2 OUTPUT2 OUTPUT2 GATE2 DRAIN3 DRAIN3 GATE3 DW PACKAGE (TOP VIEW) /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0084/C0080/C0073/C0067/C0049/C0051/C0050/C0049/C0076 /C0051/C0262/C0072/C0065/C0076/C0070/C0032/C0072/C0262/C0066/C0082/C0073/C0068/C0071/C0069/C0032/C0071/C0065/C0084/C0069/C0262/C0080/C0082/C0079/C0084/C0069/C0067/C0084/C0069/C0068/C0032/C0076/C0079/C0071/C0073/C0067/C0262/C0076/C0069/C0086/C0069/C0076 /C0080/C0079/C0087/C0069/C0082/C0032/C0068/C0077/C0079/C0083/C0032/C0065/C0082/C0082/C0065/C0089 /C0261 SLIS042 − NOVEMBER 1994 2−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating case temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
/C0084/C0080/C0073/C0067/C0049/C0051/C0050/C0049/C0076 /C0051/C0262/C0072/C0065/C0076/C0070/C0032/C0072/C0262/C0066/C0082/C0073/C0068/C0071/C0069/C0032/C0071/C0065/C0084/C0069/C0262/C0080/C0082/C0079/C0084/C0069/C0067/C0084/C0069/C0068/C0032/C0076/C0079/C0071/C0073/C0067/C0262/C0076/C0069/C0086/C0069/C0076 /C0080/C0079/C0087/C0069/C0082/C0032/C0068/C0077/C0079/C0083/C0032/C0065/C0082/C0082/C0065/C0089 /C0261 SLIS042 − NOVEMBER 1994 2−3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(BR)DSX Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 60 V VGS(th) Gate-to-source threshold voltage ID = 1 mA, See Figure 5 VDS = VGS, 1.5 1.75 2.2 V V(BR)GS Gate-to-source breakdown voltage IGS = 250 µA 18 V V(BR)SG Source-to-gate breakdown voltage ISG = 250 µA 9 V V(BR) Reverse drain-to-GND breakdown voltage (across D1, D2, D3, D4, D5) Drain-to-GND current = 250 µA 100 V VDS(on) Drain-to-source on-state voltage ID = 1.25 A, See Notes 2 and 3 VGS = 5 V, 0.44 0.5 V VF(SD) Forward on-state voltage, source-to-drain IS = 1.25 A, VGS = 0 (Z1 − Z6), See Notes 2 and 3 and Figure 12 0.9 1.1 V VF Forward on-state voltage, GND-to-drain ID = 1.25 A (D1 − D5) See Notes 2 and 3 4 V IDSS Zero-gate-voltage drain current VDS = 48 V, TC = 25°C 0.05 1 AIDSS Zero-gate-voltage drain current VDS = 48 V, VGS = 0 TC = 125°C 0.5 10 µA IGSSF Forward-gate current, drain short circuited to sourceVGS = 15 V, VDS = 0 20 200 nA IGSSR Reverse-gate current, drain short circuited to sourceVSG = 5 V, VDS = 0 10 100 nA Ilkg Leakage current, drain-to-GND VDGND = 48 V TC = 25°C 0.05 1 AIlkg Leakage current, drain-to-GND V DGND = 48 V TC = 125°C 0.5 10 µA rDS(on) Static drain-to-source on-state resistance VGS = 5 V, ID = 1.25 A, TC = 25°C 0.35 0.4 ΩrDS(on) Static drain-to-source on-state resistance ID = 1.25 A, See Notes 2 and 3 and Figures 6 and 7TC = 125°C 0.57 0.6 Ω gfs Forward transconductance VDS = 15 V, I D = 625 mA, See Notes 2 and 3 and Figure 9 1.6 1.74 S C iss Short-circuit input capacitance, common source 200 250 C oss Short-circuit output capacitance, common sourceVDS = 25 V, f = 1 MHz, VGS = 0, See Figure 11 175 220 pF C rss Short-circuit reverse-transfer capacitance, common source VDS = 25 V, f = 1 MHz, VGS = 0, See Figure 11 40 75 pF NOTES: 2. Technique should limit TJ − TC to 10°C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain and GND-to-drain diode characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT trr Reverse-recovery time IS = 625 mA, VGS = 0, VDS = 48 V, di/dt = 100 A/µs, Z1, Z2, and Z3 45 ns Q RR Total diode charge S VGS = 0, See Figures 1 and 14 DS di/dt = 100 A/µs, Z1, Z2, and Z3 50 nC
/C0084/C0080/C0073/C0067/C0049/C0051/C0050/C0049/C0076 /C0051/C0262/C0072/C0065/C0076/C0070/C0032/C0072/C0262/C0066/C0082/C0073/C0068/C0071/C0069/C0032/C0071/C0065/C0084/C0069/C0262/C0080/C0082/C0079/C0084/C0069/C0067/C0084/C0069/C0068/C0032/C0076/C0079/C0071/C0073/C0067/C0262/C0076/C0069/C0086/C0069/C0076 /C0080/C0079/C0087/C0069/C0082/C0032/C0068/C0077/C0079/C0083/C0032/C0065/C0082/C0082/C0065/C0089 /C0261 SLIS042 − NOVEMBER 1994 2−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(on) Turn-on delay time 34 70 td(off) Turn-off delay time VDD = 25 V, R L = 40 Ω, ten = 10 ns, 80 150 nstr Rise time VDD = 25 V, tdis = 10 ns, R L = 40 Ω, See Figure 2 ten = 10 ns, 28 55 ns tf Fall time tdis = 10 ns, See Figure 2 15 30 Q g Total gate charge VDS = 48 V, ID = 625 mA, VGS = 5 V, 4.6 5.8 Q gs(th) Threshold gate-to-source charge VDS = 48 V, See Figure 3 ID = 625 mA, V GS = 5 V, 0.7 0.88 nC Q gd Gate-to-drain charge See Figure 3 2.5 3.13 nC LD Internal drain inductance 5 nH LS Internal source inductance 5 nH R g Internal gate resistance 0.25 Ω thermal resistance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R θJA Junction-to-ambient thermal resistance See Notes 4 and 7 90 R θJB Junction-to-board thermal resistance See Notes 5 and 7 44.5 °C/W R θJP Junction-to-pin thermal resistance See Notes 6 and 7 28 C/W NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink. 5. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board. 6. Package mounted in intimate contact with infinite heatsink. 7. All outputs with equal power
/C0084/C0080/C0073/C0067/C0049/C0051/C0050/C0049/C0076 /C0051/C0262/C0072/C0065/C0076/C0070/C0032/C0072/C0262/C0066/C0082/C0073/C0068/C0071/C0069/C0032/C0071/C0065/C0084/C0069/C0262/C0080/C0082/C0079/C0084/C0069/C0067/C0084/C0069/C0068/C0032/C0076/C0079/C0071/C0073/C0067/C0262/C0076/C0069/C0086/C0069/C0076 /C0080/C0079/C0087/C0069/C0082/C0032/C0068/C0077/C0079/C0083/C0032/C0065/C0082/C0082/C0065/C0089 /C0261 SLIS042 − NOVEMBER 1994 2−11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 THERMAL INFORMATION † Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink. NOTE A: Z θB(t) = r(t) RθJB tw = pulse duration tc = cycle time d = duty cycle = tw /tc DW PACKAGE † JUNCTION-TO-BOARD THERMAL RESISTANCE vs PULSE DURATION tw − Pulse Duration − s 100 0.0001 0.001 0.1 0.01 0.1 1 10 d = 0.01 tw tc ID 100 JBθ C/W°− Junction-to-Board Thermal Resistance − R d = 0.02 d = 0.05 d = 0.1 d = 0.2 d = 0.5 DC Conditions Single Pulse Figure 17
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPIC1321LDW OBSOLETE SOIC DW 24 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 8-Apr-2005 Addendum-Page 1
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