TPD7203F

TPD7203F TOSHIBA | Alldatasheet

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TENTATIVE TOSHIBA INTELLIGENT POWER DEVICE SILICON MONOLITHIC POWER MOS INTEGRATED CIRCUIT TPD7203F is a power MOSFET Gate Driver for 3-Phase full- bridge circuit using charge pump system. Because this IC contains a charge pump circuit for high-side drive, it allows you to configure 3-phase full-bridge circuit. _— oe FEATURES S Ne oes @ Power MOSFET Gate Driver for 3-Phase DC Motor NE @ Built-in power MOSFET protection and diagnosis function: low-voltage protection @ Built-in a charge pump circuit $SOP24-P-300-1.00B @ Package: SSOP-24 (300 mil) with embossed-tape packing Weight : 0.29 g (typ.) PIN ASSIGNMENT MARKING (TOP VIEW) Toshiba Trademark cv cose z oon ahonononoonon Rosc u , i Lot code INS uu ine [4] zi] v TPD7203F Product no. ae EY OOO OOoOOooooo 1n2 [6] [9] w IN3 [18] wu Lot code naming system na BB] us ooogoga rautt [3] [ie] ve ‘——Toshiba house no. i 5 Manufactured week (52 weeks or 53 SGND PGND weeks indicating system starting from crt 114] we the first Thursday of January) cp2 Vo Manufactured year (last two digits of the year) Because this product uses MOS structure, must take special care with electrostatic when handling. 9809 10EBA @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified ‘operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook 3 The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications ‘of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 2000-03-02 1/19

BLOCK DIAGRAM / APPLICATION CIRCUIT 1 ve I Reverse connection protection (ray a (a) (tay Ps S & x certo $ 3 Shes) Tee “hb om 3 s Stes) S703) ‘4 ¥ a ecapeee @ = i “6 a . u ye i> | Ty fe me a Logic Circuit > ‘© ‘on Cdl TT me LTT PIT * [ee TTT IR il Pe TT pes TI eee BSP BS Cet tw bad © Pt od A aitiE See S. we, cy a be | | i= Kpe aI (*1) : Optimum conditions depend on switching loss, EMI, etc. of external MOSFET. (#2) : SBD Vp = 0.5V max (Recommended : CRSO3) This is needed when the U, V and W pin is biased to the negative side by more than 0.5 V. (*3) : This is a laminated ceramic capacitor. (*4) : High-speed diode tyr = 100 ns max (Recommended : CRHO1) (Note) : When selecting external parts, please read "Method for selecting external parts" described later. 2000-03-02 2/19

BLOCK DIAGRAM / APPLICATION CIRCUIT 2 ve I Reverse connection protection (3) a 3) 3) . g x = crt M ; : | eoecapeaa = —__| owe | Ss ” protection circuit 23) ne i || Ue. Fe Lge dd Pye ee canal 7 On 49} re) me nnn alll ahh ath eo tT | DIE BR ES Een) Coe SIT S. > ws, 1) S G9) “? 7 | i= (pas (#1) : Optimum conditions depend on switching loss, EMI, etc. of external MOSFET. (*2) : This is a laminated ceramic capacitor. (*4) : High-speed diode tyr = 100 ns max (Recommended : CRHO1) (Note) : When selecting external parts, please read "Method for selecting external parts" described later. 2000-03-02 3/19

fowne [ swoor [ esas id | | cose [esnnea = stm pF vecommensed)cpector | Connect a 1500 pF (recommended) capacitor. Connect a 100 kQ (recommended) resistor.

3 INS Input pin: it controls the power MOSFET connected to VB and built-in pull-

down resistor (100 kQ. typ.) Input pin: it controls the power MOSFET connected to WB and built-in pull- | | me [iin neon ook yp) ens Neen a | Po [maT | down resistor (100 kQ. typ.) Pe | me lic reser ook yp) Oa RI a down resistor (100 kQ, typ.) | 7 | me [aswnfeusartookt yp ER down resistor (100 kO. typ.) a ec down resistor (100 kQ. typ.) | | rut [eri contgurton ic Meh open rams | Circuit configuration is N-ch open drain. [10 | SGND signal block GND pin. SSSSSSSCSCSCSCSCSSSSC~‘*d po [on Seles | Connect a 0.47 uF (recommended) laminated ceramic capacitor. Connect a 0.47 uF (recommended) laminated ceramic capacitor. DD shut down. | 14 [| We [Drives the power MOSFET connected to the low side of W phase. | | 15 | PGND [Power block GND pin | 16 | VB [Drives the power MOSFET connected to the low side of V phase. | | 19 | W [Wphase output pin vie fate

24 CPV Connect 1 “F (recommended) laminated ceramic capacitor and 10 uF

(recommended) aluminum electrolytic capacitor in parallel. 2000-03-02 4/19

TRUTH TABLE (All outputs go low for input in High side/Low side arm shorting mode) iaketlepteeleelen| | (UU) | (VU) |(WU)| (UB) | (VB) |(WB)| UU | VU | WU | UB | VB | WB por PetetetTetetetetetetegvegtepo poo {H{TtTefeteftetH{efefefefepo Pos [etTH etetetefetapeqe pee pT poate tetH{efefefefetrfefefe po Pos Te TetetHtetefeveteq ape pep Poo [ete ftetetHfefetetete tape pT Por [ete ftetetefafeteteqe peta pT Pos THIET ETHT ETE eTeT eT eye & high sidestow side arm shorting mode (*) | po fof ete fet afetet fee fa]: [eave ne screen mode pote fefefefedataf feeds] a piacere screen mode Pe fefefetafefefefef eo] | [avers errs mode Paz PeTHPeTeTHPefeT eT eT ete & high sidestow side arm shorting mode (*) | pe fefefefefelatefe fee] | a five sre cre rem mode pe fefefatafefetet eee ye] s fevers mode ps fefefafetalefel fof] a] s averse cree mode Dw tatH[t[e[i1{tjala[tj[r{tfrf —S—S—s™Y A A A par tetetetetaefPafetet et etapa pT P22 fete te tet efafetet eta pe tap P23 PHT HITE PHT EP ee eT eT eft TE high side/tow side arm shorting mode (*) | P24 THT HITE Te THT ee Te Te Te] tT high sidestow side arm shorting mode (*) | Das [H[H|t[t[t[H]a[n|[tj[r{t[w[ id a Dare ae ea Pt Pt [tt [1 | 6 Iiigh ser ow side arm shoring mode (| Dae eA Heft at [et Lt [1 [0 high side/tow side arm shorting mode () | Pao THT EPH THT EP eT eT eT eT ef tT Ut high side/tow side arm shorting mode (*) | EE ee ee (*) : High side/ Low side arm shorting mode is disabled by the internal logic. (FAULT is kept low.) When undervoltage (6 V typ.) is detected, all outputs are pulled low regardless of input signals. At this time, FAULT output goes high (open-drain, high- impedance). 2000-03-02 5/19

(UU) | (VU) |(WU)| (UB) | (VB) |(WB)| UU | VU | WU | UB | VB | WB Pst THPETAH TET ETH TET ETET ET ET b High side/tow side arm shorting mode (*) | Paz Het HPAL Le] tt | tA high side/tow side arm shorting mode (| [3a ;t ttt pa[H}a[t[i1[cjaxjw] | Dae att Hie] ttt | | 1 LA |Aigh sie/tow se im shoring mode | Pas [eA Pe [HA Pe ft [et ft [1 | 6 high side tow sidearm shorting mode | P36 [ETHIE TETH PATE TET ET eT LT © righ sidestow side arm shorting mode *) | ps7 [eTH{T eRe pafetH Peta pe pap P38 eT eT HIRT HP eet eta RH tape ao fit [HH Pt [att [tt | t [1 high side/tow side arm shorting mode | SE paz {ete tetHtaHPafetet eat apap P43 THT HT ETH TH PEPE TET eT eT tT EL [High sidestow side arm shorting mode *) | P44 THT HT ET ETH PAPE TET eT eT tT UL High sidertow side arm shorting mode) | P45 [HTH] ETH ETH eT eT eT eT tT EL High sidestow side arm shorting mode *) | p46 [ETH HTHTH PEP eT eT eT te | tT UL High sidestow side arm shorting mode *) | Dar [twat ate [tC | tO high side/tow side arm shorting mode (| Pas eae aft a Pt Lt [1 [0 high side tow side arm shorting mode | Pas AH HPA] LLY] t Ct LC [Aig side/tow side arm shorting mode (| Pso THT tETHTUTHTAPeTeT eT eT et TL righ sidestow side arm shorting mode *) | Psi [HT LETH THT EPHP eT eT eT eT tT UL righ sidestow side arm shorting mode *) | Ps3 [HT HTH IEPA TEP eT eT eT e | tT Ut righ sidestow side arm shorting mode *) | Psa HH | HR] tpt tH] t [et [tt | t [1 high side/tow side arm shorting mode | pss [HILT eH TH THI eT eT eT ett | & |High sidestow side arm shorting mode *) | Psst PH] tH PAH] tt] tC | 1 [A high side/tow side erm shorting mode | Der fete aaa Pte] Lt [1 | O Ihigh side tow side arm shorting mode | Psp [HT HTHTHTHIT Eee Tee | t Tt righ sidestow side arm shorting mode *) | Pso [HT HIT HT ULTHPAP eT eT eT e | tT Ut Jrigh sidestow side arm shorting mode *) | | eo [HIH{THIHIT ETHIC eT eT ett | Ut JHigh sidestow side arm shorting mode *) | Per [HTH] ETHTHTHI LT eT eT eT tT EL righ sidestow side arm shorting mode *) | Dez [ifn |X [H PH [H]t[ et] tt | t [1 high side/tow side erm shorting mode Pes | Ht |X |H TA [H] LL || | 1 [Chih side/tow side arm shorting mode (| Pea THTHT HTH TH TH Pee Pe Pe Pt Tt Trish side/tow side arm shorting mode (*) | (*) : High side/Low side arm shorting mode is disabled by the internal logic. (FAULT is kept low.) When undervoltage (6 V typ.) is detected, all outputs are pulled low regardless of input signals. At this time, FAULT output goes high (open-drain, high- impedance). 2000-03-02 6/19

MAXIMUM RATING (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT REMARKS Power Supply Voliage ros30 [Vv CSCS Output Current Louse | tJ a | Pulse width = 10 ys Tapat Voltage [vin [08-70 [vf FAULT Pin Voltage Veaurt | 30 | Vv [SSCS U, V and W Pin Negative U(-) Negative voltage that can be Voltage v(-) V_ [applied to U, V and W pins 9 w(-) (reference to SGND pin) Negative voltage that can be PGND Pin Negative Voltage PGND (-) V_ | applied to PGND pin (reference to SGND pin) Fault Pin Current aur [3 [mal SCS Operating Temperature =a~=15_[ [SSCS THERMAL RESISTANCE CHARACTERISTIC SYMBOL RATING UNIT Junction to Ambient Thermal 156.3 ° (Note) : When a device mounted on 60mm x 60mm x 1.6t glass epoxy PCB. 2000-03-02 7/19

ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = -40~125°C) TEST CHARACTERISTIC | SYMBOL CONDITION a |v. [ax UNIT REMARKS CUIT Operating Supply Vi 7| 13. Vv Voltage DD 35 IpD (1) | Vpp = 13.5V }-[|-| »| Oscillation circuit stops Supply Current Vpp = 13.5V, When oscillation circuit IDD (2) ViIN1~VING is operating f = 20 kHz, =0V mean current Vin | as] — | — | IN1-IN6 high-level input Vpp = 7~18V, voltage Input Voltage lo =0A V_TlINT-ING low-level input VIL 15 voltage Vpp = 7~18V, Vin = 5¥, Io =0A . IN1-IN Input Current Vpp = 7=18V, 6 input current UL VIN = OV, -10 uA lo =0A Vpp = 13.5V, UU pin voltage Vou Vin = 5V, Vepv Vepy (reference to U pin) lo =0A -2 VU pin voltage High side (reference to V pin) Vpp = 13.5V, WU pin voltage _ ' (reference to W pin) Output VoL oa v Vcpv denotes CPV pin Voltage voltage. Vpp = 13.5V, UB pin voltage VOH VIN = 5V, 13.5 (reference to PGND pin) i Io = 0A VB pin voltage L id Pp 9) ow side Vpp = 13.5V, (reference to PGND pin) VoL Vin = OV, WB pin voltage lo = 0A (reference to PGND pin) Charge Pump _ CPV pin voltage Voltage Vepv Vpp = 13.5V 30 35) V (reference to SGND pin) Active Clamp UB, VB and WB pins Vin = 5V, Voltage VcLAMP lo = 10mA V_|clamp voltage (Low Side) O= (reference to PGND pin) Vpp = 13.5V, RSOURCE VIN = 5V, 7 UU, VU, WU, UB, VB . lo = 0.5A and WB output Output Resistance Vpp = 13.5V, a resistance RsINK Vin = OV, pulse width S$ 10 ys Io = -0.5A 2000-03-02 8/19

CHARACTERISTIC | SYMBOL | CIR- CONDITION TYP. |MAX.| UNIT REMARKS CUIT Low-vol i Low- Detection] Vsp (L) 5.5 65 ow-voltage detection voltage and hysteresis Voltage 3 Vv Vv voltage ela time. *d (ON) wi wnereany [T= [ al, pwn Time 9} Cour = 0.047 ef, us |and WB switching mT [wen | * fete lm time Turn-off |-|-| 4 fosc calculation ge Vpp = 7~18V, Oscillating formula fi Ri = 100kQ, 20 kHz Frequency Osc cose = 4500 pF fosc = 3/{Cosc (Rosc Osc + 2k)} (Hz) FAULT Pin _ FAULT pin low-level Voltage VFAULT | 2 | 'FAULT = 1mA | — | - | 03] v voltage (open-drain) t RFAULT = 5-1kQ, 1 Time from low voltage FAULT Delay ‘ON VEAULT = 5V. detection or Time t (External power 1 YS lrestoration to FAULT ‘OFF supply) output inversion 2000-03-02 9/19

TESTING CIRCUIT 1 Ipp (1) : | i ] OOOO Ypp Cosc Rose Pr cP2. CPV w @ G)in1 ne) ou vu @9) @ na VO om TPD7203F w@ @ ns wO @ins us @) @ aut w® SGND ecu w8G) (9 ® TESTING CIRCUIT 2) Ipp (2). VIH» Vite HHs NL) VoH» VOL. Vcpv. VFAULT !pp. © = le es $8 sx Sk’ @vorv Vpp = 13.5V Ss z [8 Pa cl ett Vop Cosc Rosc CP1 CP2 CPV @® Youu uu ORO om ‘94 (6) in2 69 Vovu vu a d vom TPD7203F w@& YO @D iow bun "Ld ¢ (4) INé final lina} ina} tinal ins] ting] ve @) ve (6) Mant) Yin2 | Vans} Vind | Vins] Vine SGND PGND we @ ® OM OD O® Vows] ‘ows |Vovel!ove |Vous|'ous 'FAULT VFAUL) 2000-03-02 10/19

TESTING CIRCUIT 3 Vsp (L), 4Vsp (L), FAULT delay time ton, torr (DOO 2 Yoo Cosc Rose ct ce cw im es © nz wo Qn iO ou TPD7203F w@ @) ins w@ en w@® (3) rautt wd vesv~ Oveauer sGNo reno WeGd ] @ ® low-voltage low-voltage detection restoration VeauLt waveform (50%) fo 2000-03-02 11/19

TESTING CIRCUIT 4 tg (ON), ton, td (OFF), tOFF vo ; Yoo Cosc Rosc CPi CP2. CPV Rg = 470 uu iC Youu Cour = 0.047 pF Gin ®

2 Rg = 470

o. . PS nme 3 Vovu Cour = 0.047 uF ™ v@ (3) ina Rg = 47 TPD7203F wu TO Vowu Court = 0.047 uF @ ws wd (4) ine Vinal Vina] Ying] Vinal Vins} Ving] us) Q2@Q@OQOQOO® Onmur ve G6) pc.|Pc.]Pc.| pc} pc.| pc SGND row WOOD Rg = 470|Rg = 47 O}Rg = 470 {9 ie ® ® © \\Yows| |Vove Yous Cour Cour [Cour Input waveform (5096) oo. ceccccccccuufevsnneseseennensnnsnnneneeenssessanannnseseeseasessnsnneeeeeennsunineneees Vin : : TT sh sssepnsed . (100%) = Vpp-2V sariniinbnanyfincnasinanannasiann” ions gh Output waveform i Your i i i i Ce ‘ (on: td (OFF) E “ton torr 2000-03-02 12/19

Ipp(1) - Ta Ipp(1) - Ta 5 5 ff] aes | [ j[ jf [ f J 4 ° je ° ers Vpp = 135V Vint =5V | RFE Hs | =80 0 80 160 =80 0 80 160 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) 5 5 ee ee ee Ae ee ee a a f EL, tt tt ty EERE EEE se fj | | tt tt FJ i | ft] tt ¢ 7] | tt tt tf 2 [tt iy i tt i ERREEER, ) FEEEEEES 2 2 POWER SUPPLY VOLTAGE Vpp (V) POWER SUPPLY VOLTAGE Vpp (V) 5 5 » EEREE=]) ; FREE , ~ it] |] tf Se ee gs J | | J } gf Lt | | il gz [ | J | | ff $ ce ee be 7 ° AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) 2000-03-02 13/19

re] ee] ee ee re z 8 z 38 gE] | | fT ft S [ [ ft fy fy - =80 0 80 760 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) VpRop - POWER SUPPLY VOLTAGE VoL - POWER SUPPLY VOLTAGE s [Treen (aa ote) = B |_|iiver ach output gh? SE, } Py yt tf g |__| voltages from the Vop voltage. & rf | | | | [ jf fi] g [tT TTryT TTT 3 oo | | | | tt $s 3 Popper ESSER ° f tT iti tr i ft fit tt i tt | POWER SUPPLY VOLTAGE Vpp/Vcpy (V) POWER SUPPLY VOLTAGE Vpp/Vcpy (V)

5 VpRoP - Ta 01 VoL - Ta

a _ The output drop voltage refers to a drop S 008 } | | ft | lo OA when each output is hig 2 g 3 0.04) 8 — 2 PERSSSS PRES er ee ee ee a_i | i | ft =80 0 80 760 =80 0 80 760 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) 2000-03-02 14/19

10 Rsource - Ta 10 RsINK - Ta

ey | | | Te oo a ee ej oi | [| ft 3 } > f+ feat. | a { [ Jf fT fT Tt =80 0 80 160 =80 0 80 160 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) Vsp(L) - Ta Vsp (Ll) - Ta Fd oe @ {TT TTT] 2 6 Go 65 B65 —_ red 28 ee 5 “ S| =80 0 80 760 80 0 80 760 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) OUTPUT SWITCHING TIME OUTPUT SWITCHING TIME 5 UU. VU, WU, UB, VB, WB) ton - VoD. ; (UU, VU, WU, UB, VB, WB) toFF - VDD Se ee 2 ELE TT oe 8 8 Pecos: eeeee 5 Court = 0.047 yr 5 Cour = 0.047 uF 0 5 70 5 20 0 5 10 5 20 POWER SUPPLY VOLTAGE Vpp (V) POWER SUPPLY VOLTAGE Vpp (V) 9900-03-02 15/19

OUTPUT SWITCHING TIME OUTPUT SWITCHING TIME 5 (UU, VU, WU, UB, VB, WB) ton - Ta 5 (UU, VU, WU, UB, VB, WB) torr - Ta a a a rs ee es 2 4 fs 5 5 { | ft |] x J | ft | ft ff yx J | ft fT ft ft zo; z 3

5 J, | | | tT ft | J, eI fT

5 =H + e | | jar - | ett) + : ee ee a { | J ft ft fy a { | J ft ty ei | | | ff fi | i tT] -80 oO 80 160 = AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) fosc - Ta VFAULT ~ Tj eI) OTT = jt ET 1 L Pe he PTODeroe) $= COeeer oo g 3 Zo 2 ose | g 5 PeLit it tT) ger ey Ere Tope, Ts

3 Cosc = 1500 pF f= 20kHz

8s 0 50 100 150 oa -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE Ta (°C) Ti CO Pp - Ta eu {| | | et XT] 5 IN LIN | 2 04] ~ é PL | TIN | of ay 40 120 AMBIENT TEMPERATURE Ta (°C) OTT 2000-03-02 16/19

METHOD FOR SELECTING EXTERNAL PARTS RECOMMENDED VALUE/ [holm name] rvee |recommenoep mooucr| __—oescnerion [2 [Rose [Resistor [100k ___—_—_____|Sets charge pump’s oscillation frequency. | Capacitor for the charge pump. Greater cP1 Capacitor 0.47 uF this capacitance larger the charging cP2 (laminated ceramic) current to the capacitor, so there is a greater loss in the IC. 1 pF (laminated ceramic) Greater this capacitance, larger the charge . pump (CPV pin)'s current supply capacity, and 10 yF (aluminum A - cPV Capacitor electrolytic) connected in so there is a greater loss in the IC. Therefore, be careful not to exceed the parallel allowable loss. Diode for the charge pump. An electric 1 cP1 High-speed trr = 100 ns (max.) charge equal to the diode's Qrr 12 cP2 diode CRHO1 (try = 35 ns max.) component goes out of the capacitor's 24 cPV recommended charged electricity. Therefore, use a high- speed diode. 22 UU 20 VU Gate resistor for external power MOSFET.

18 WU Resistor Choose the optimum value by considering

17 UB the switching loss and EMI of the power

16 VB MOSFET. 14 WB This is needed when the U, V or W pin is biased to the negative side by more than 0.5V from the SGND voltage. Because this 10 SGND Vp = 0.5V (max.) Ic operates relative to SGND, a parasitic 19 Ww diode exists toward each pin. When the SBD CRSO3 (VF = 0.45 V max. a " 21 Vv @0.7 A) recommended U, V or W pin is biased to the negative 23 U ° side by more than 0.5V from SGND, the parasitic diode conducts, causing the IC to operate erratically or generate abnormal heat. This is needed when the U, V or W pin is v Resistor biased to the negative side by more than U 0.5V from the SGND voltage. This is used to limit current for external SBD. 2000-03-02 17/19

(Note 1) : About taking the charge pump voltage to external devices Current can be taken out of the charge pump's final stage (CPV pin) to external devices without causing any problem. In this case, because the charge pump voltage drops, increase the capacitance of the capacitor connected to the CPV pin. However, this may cause the charging current to the capacitor and, hence, loss in the IC to increase. So be careful not to exceed the allowable loss. (Note 2) : About heat sink design Because this IC contains a charge pump function, loss in it affects external capacitor capacitance and diode characteristics. It is recommended that the junction temperature, Tj, be judged from the on-voltage of the FAULT pin (open-drain). When Vpp is within the range of operating power supply voltages, the FAULT pin outputs a low. For details about on-voltage characteristics, see Tj-VFAULT characteristic curves. (Note 3) : About dead time setting For arm-shorting input logic, all outputs (UU, VU, WU, UB, VB and WB) are pulled low. When operating in forward or reverse mode, consider the IC output switching time and the switching time (including temperature characteristic) of the external power MOSFET as you set the dead time. The dead time required for only the IC, not including the external power MOSFET, is 4 us (within all operating power supply voltages and all operating temperatures). (Note 4) : Shorting between outputs, Shortcircuit of outputs and Vpp pin or shortcircuit of outputs GND pin may cause the IC to break down. Therefore, pay careful attention to the design of output lines and Vpp and GND lines. (Note 5) : Precautions on dry packing After unpacking dry or moistureproof packing, please make sure the device is mounted in place within 48 hours at temperature and humidity of 30°C and 60% RH or less. Because the device is emboss-taped and cannot be processed by baking, always be sure to use it within said allowable time after unpacking. Tape packing quantity: 500 devices/reel (EL) or 2000 devices/reel (EL1) 2000-03-02 18/19

SSOP24-P-300-1.00B Unit : mm 24 13 . uN = | : | Oo o no ©} 2 1 ij 12 1.0TYP 0.4+0.1 fB10.200) 13.5MAX 13.0+0.2 Nx a) 4 lo} ry = lo} S| ° z fr) 0.45+0.2 Weight : 0.29 g (typ.) 2000-03-02 19/19