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TPD6S300RUKRG4

Texas Instruments

TPD6S300 USB Type-C™ Port Protector: Short-to-VBUS Overvoltage and IEC ESD Protection REVISED JANUARY 2017

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Technical content

OVP & ESD CC Analog USB PD Phy & Controller Power Switch Control FET OVP, OCP VBUS FET OVP Battery SBU1SBU2DP SBU Mux Copyright © 2016, Texas Instruments Incorporated DM Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD6S300 SLVSDK3C –SEPTEMBER 2016–REVISED JANUARY 2017 TPD6S300USBType-C™ PortProtector:Short-to-VBUSOvervoltageandIECESD Protection

1 Features

1• 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2): 24-VDC Tolerant

6-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2, DP, DM)
CC1, CC2 Overvoltage Protection FETs 600 mA capable for passing VCONN power
CC Dead Battery Resistors integrated for handling dead battery use case in mobile devices
3-mm × 3-mm WQFN Package

2 Applications

Laptop PC
Tablets
Smartphones
Monitors and TVs
Docking Stations

3 Description

The TPD6S300 is a single chip USB Type-C port protection solution that provides 20-V Short-to-VBUS overvoltage and IEC ESD protection. Since the release of the USB Type-C connector, many products and accessories for USB Type-C have been released which do not meet the USB Type-C specification. One example of this is USB Type-C Power Delivery adaptors that only place 20 V on the VBUS line. Another concern for USB Type-C is that mechanical twisting and sliding of the connector could short pins due to the close proximity they have in this small connector. This can cause 20-V VBUS to be shorted to the CC and SBU pins. Also, due to the close proximity of the pins in the Type-C connector, there is a heightened concern that debris and moisture will cause the 20-V VBUS pin to be shorted to the CC and SBU pins. These non-ideal equipments and mechanical events make it necessary for the CC and SBU pins to be 20- V tolerant, even though they only operate at 5 V or lower. The TPD6S300 enables the CC and SBU pins to be 20-V tolerant without interfering with normal operation by providing overvoltage protection on the CC and SBU pins. The device places high voltage FETs in series on the SBU and CC lines. When a voltage above the OVP threshold is detected on these lines, the high voltage switches are opened up, isolating the rest of the system from the high voltage condition present on the connector. Finally, most systems require IEC 61000-4-2 system level ESD protection for their external pins. The TPD6S300 integrates IEC 61000-4-2 ESD protection for the CC1, CC2, SBU1, SBU2, DP, DM pins, removing the need to place high voltage TVS diodes externally on the connector. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPD6S300 WQFN (20) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Diagram

12.2 Receiving Notification of Documentation Updates 27

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision B (November 2016) to Revision C Page Changes from Revision A (September 2016) to Revision B Page

C_CC2 C_CC1 C_SBU2 C_SBU1 CC2 CC1 SBU2 SBU1 VBIAS GND N.C. N.C. GND RPD_G2 RPD_G1 VPWR FLT GND 15 11 Thermal Pad TPD6S300 www.ti.com SLVSDK3C –SEPTEMBER 2016–REVISED JANUARY 2017 Product Folder Links: TPD6S300 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

5 Device Comparison Table

Part Number Over Voltage Protected Channels IEC 61000-4-2 ESD Protected Channels TPD6S300 4-Ch (CC1, CC2, SBU1, SBU2) 6-Ch (CC1, CC2, SBU1, SBU2, DP, DM) TPD8S300 4-Ch (CC1, CC2, SBU1, SBU2) 8-Ch (CC1, CC2, SBU1, SBU2, DP_T, DM_T, DP_B, DM_B)

6 Pin Configuration and Functions

20 Pin WQFN

NO. NAME 1 C_SBU1 I/O Connector side of the SBU1 OVP FET. Connect to either SBU pin of the USB Type-C connector 2 C_SBU2 I/O Connector side of the SBU2 OVP FET. Connect to either SBU pin of the USB Type-C connector 3 VBIAS Power Pin for ESD support capacitor. Place a 0.1-µF capacitor on this pin to ground 4 C_CC1 I/O Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-C connector 5 C_CC2 I/O Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-C connector 6 RPD_G2 I/O Short to C_CC2 if dead battery resistors are needed. If dead battery resistors are not needed, short pin to GND 7 RPD_G1 I/O Short to C_CC1 if dead battery resistors are needed. If dead battery resistors are not needed, short pin to GND

8 GND GND Ground

9 FLT O Open drain for fault reporting

10 VPWR Power 2.7-V-3.6-V power supply

SLVSDK3C –SEPTEMBER 2016–REVISED JANUARY 2017 www.ti.com Product Folder Links: TPD6S300 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE DESCRIPTION NO. NAME 11 CC2 I/O System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD controller 12 CC1 I/O System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD controller

13 GND GND Ground

14 SBU2 I/O System side of the SBU2 OVP FET. Connect to either SBU pin of the SBU MUX 15 SBU1 I/O System side of the SBU1 OVP FET. Connect to either SBU pin of the SBU MUX 16 N.C. I/O Unused pin. Connect to Ground 17 N.C. I/O Unused pin. Connect to Ground

18 GND GND Ground

19 D2 I/O USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C connector 20 D1 I/O USB2.0 IEC ESD protection. Connect to any of the USB2.0 pins of the USB Type-C connector — Thermal Pad GND Internally connected to GND. Used as a heatsink. Connect to the PCB GND plane

www.ti.com SLVSDK3C –SEPTEMBER 2016–REVISED JANUARY 2017 Product Folder Links: TPD6S300 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VI Input voltage VPWR –0.3 5 V RPD_G1, RPD_G2 –0.3 24 V VO Output voltage FLT –0.3 6 V VBIAS –0.3 24 V VIO I/O voltage D1, D2 –0.3 6 V CC1, CC2, SBU1, SBU2 –0.3 6 V C_CC1, C_CC2, C_SBU1, C_SBU2 –0.3 24 V TA Operating free air temperature –40 85 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

7.2 ESD Ratings— JEDEC Specification

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±500 (1) Tested on the TPD6S300 EVM connected to the TPS65982 EVM.

7.3 ESD Ratings— IEC Specification

V(ESD) Electrostatic discharge(1) IEC 61000-4-2, C_CC1, C_CC2, D1, D2 Contact discharge ±8000 V Air-gap discharge ±15000 IEC 61000-4-2, C_SBU1, C_SBU2 Contact discharge ±6000 Air-gap discharge ±15000

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VI Input voltage VPWR 2.7 3.3 4.5 V RPD_G1, RPD_G2 0 5.5 V VO Output voltage FLT pull-up resistor power rail 2.7 5.5 V VIO I/O voltage D1, D2 –0.3 5.5 V CC1, CC2, C_CC1, C_CC2 0 5.5 V SBU1, SBU2, C_SBU1, C_SBU2 0 4.3 V IVCONN VCONN current Current flowing into CC1/2 and flowing out of C_CC1/2, VCCx – VC_CCx ≤ 250 mV 600 mA IVCONN VCONN current Current flowing into CC1/2 and flowing out of C_CC1/2, TJ ≤ 105°C 1.25 A

7.5 Thermal Information

THERMAL METRIC(1) TPD6S300 UNITRUK (WQFN)

20 PINS

RθJA Junction-to-ambient thermal resistance 45.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.8 °C/W RθJB Junction-to-board thermal resistance 17.1 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 17.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 °C/W

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CC OVP SWITCHES RON On resistance of CC OVP FETs, TJ ≤ 85°C CCx = 5.5 V 278 392 mΩ On resistance of CC OVP FETs, TJ ≤ 105°C CCx = 5.5 V 278 415 mΩ RON(FLAT) On resistance flatness Sweep CCx voltage between 0 V and

1.2 V 5 mΩ

CON_CC Equivalent on capacitance Capacitance from C_CCx or CCx to GND when device is powered. VC_CCx/VCCx = 0 V to 1.2 V, f = 400 kHz 60 74 120 pF RD Dead battery pull-down resistance (only present when device is unpowered). Effective resistance of RD and FET in series V_C_CCx = 2.6 V 4.1 5.1 6.1 kΩ VTH_DB Threshold voltage of the pulldown FET in series with RD during dead battery I_CC = 80 µA 0.5 0.9 1.2 V VOVPCC OVP threshold on CC pins Place 5.5 V on C_CCx. Step up C_CCx until the FLT pin is asserted 5.75 6 6.2 V VOVPCC_HYS Hysteresis on CC OVP Place 6.5 V on C_CCx. Step down the voltage on C_CCx until the FLT pin is deasserted. Measure difference between rising and falling OVP threshold for C_CCx 50 mV BWON On bandwidth single ended (–3 dB) Measure the –3-dB bandwidth from C_CCx to CCx. Single ended measurement, 50-Ω system. Vcm = 0.1 V to 1.2 V

100 MHz

www.ti.com SLVSDK3C –SEPTEMBER 2016–REVISED JANUARY 2017 Product Folder Links: TPD6S300 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSTBUS_CC Short-to-VBUS tolerance on the CC pins Hot-Plug C_CCx with a 1 meter USB Type C Cable, place a 30-Ω load on CCx 24 V VSTBUS_CC_CL AMP Short-to-VBUS system-side clamping voltage on the CC pins (CCx) Hot-Plug C_CCx with a 1 meter USB Type C Cable. Hot-Plug voltage C_CCx = 24 V. VPWR = 3.3 V. Place a 30-Ω load on CCx 8 V SBU OVP SWITCHES RON On resistance of SBU OVP FETs SBUx = 3.6 V. –40°C ≤ TJ ≤ +85°C 4 6.5 Ω RON(FLAT) On resistance flatness Sweep SBUx voltage between 0 V and CON_SBU Equivalent on capacitance Capacitance from SBUx or C_SBUx to GND when device is powered. Measure at VC_SBUx/VSBUx = 0.3 V to 3.6 V 6 pF VOVPSBU OVP threshold on SBU pins Place 3.6 V on C_SBUx. Step up C_SBUx until the FLT pin is asserted 4.35 4.5 4.7 V VOVPSBU_HYS Hysteresis on SBU OVP Place 5 V on C_CCx. Step down the voltage on C_CCx until the FLT pin is deasserted. Measure difference between rising and falling OVP threshold for C_SBUx 50 mV BWON On bandwidth single ended (–3 dB) Measure the –3-dB bandwidth from C_SBUx to SBUx. Single ended measurement, 50-Ω system. Vcm = 0.1 V to 3.6 V

1000 MHz

Measure crosstalk at f = 1 MHz from SBU1 to C_SBU2 or SBU2 to C_SBU1. Vcm1 = 3.6 V, Vcm2 = 0.3 V. Be sure to terminate open sides to 50 Ω –80 dB VSTBUS_SBU Short-to-VBUS tolerance on the SBU pins Hot-Plug C_SBUx with a 1 meter USB Type C Cable. Put a 100-nF capacitor in series with a 40-Ω resistor to GND on SBUx 24 V VSTBUS_SBU_C LAMP Short-to-VBUS system-side clamping voltage on the SBU pins (SBUx) Hot-Plug C_SBUx with a 1 meter USB Type C Cable. Hot-Plug voltage C_SBUx = 24 V. VPWR = 3.3 V. Put a 150-nF capacitor in series with a 40-Ω resistor to GND on SBUx 8 V POWER SUPPLY and LEAKAGE CURRENTS VPWR_UVLO VPWR under voltage lockout Place 1 V on VPWR and raise voltage until SBU or CC FETs turnon 2.1 2.3 2.5 V VPWR_UVLO_H YS VPWR UVLO hysteresis Place 3 V on VPWR and lower voltage until SBU or CC FETs turnoff; measure difference between rising and falling UVLO to calculate hysteresis 100 150 200 mV IVPWR VPWR supply current VPWR = 3.3 V (typical), VPWR = 4.5 V (maximum). –40°C ≤ TJ ≤ +85°C. 90 135 µA ICC_LEAK Leakage current for CC pins when device is powered VPWR = 3.3 V, VC_CCx = 3.6 V, CCx pins are floating, measure leakage into C_CCx pins. Result must be same if CCx side is biased and C_CCx is left floating 5 µA

SLVSDK3C –SEPTEMBER 2016–REVISED JANUARY 2017 www.ti.com Product Folder Links: TPD6S300 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISBU_LEAK Leakage current for SBU pins when device is powered VPWR = 3.3 V, VC_SBUx = 3.6 V, SBUx pins are floating, measure leakge into C_SBUx pins. Result must be same if SBUx side is biased and C_SBUx is left floating. –40°C ≤ TJ ≤ +85°C 3 µA IC_CC_LEAK_OV P Leakage current for CC pins when device is in OVP VPWR = 0 V or 3.3 V, VC_CCx = 24 V, CCx pins are set to 0 V, measure leakage into C_CCx pins 1200 µA IC_SBU_LEAK_O VP Leakage current for SBU pins when device is in OVP VPWR = 0 V or 3.3 V, VC_SBUx = 24 V, SBUx pins are set to 0 V, measure leakage into C_SBUx pins 400 µA ICC_LEAK_OVP Leakage current for CC pins when device is in OVP VPWR = 0 V or 3.3 V, VC_CCx = 24 V, CCx pins are set to 0 V, measure leakage out of CCx pins 30 µA ISBU_LEAK_OVP Leakage current for SBU pins when device is in OVP VPWR = 0 V or 3.3 V, VC_SBUx = 24 V, SBUx pins are set to 0 V, measure leakage out of SBUx pins –1 1 µA IDx_LEAK Leakage current for Dx pins V_Dx = 3.6 V, measure leakage into Dx pins 1 µA FLT PIN VOL Low-level output voltage IOL = 3 mA. Measure the voltage at the FLT pin 0.4 V OVER TEMPERATURE PROTECTION TSD_RISING The rising over-temperature protection shutdown threshold 150 175 °C TSD_FALLING The falling over-temperature protection shutdown threshold 130 140 °C TSD_HYST The over-temperature protection shutdown threshold hysteresis 35 °C Dx ESD PROTECTION VRWM_POS Reverse stand-off voltage from Dx to GND Dx to GND. IDX ≤ 1 µA 5.5 V VRWM_NEG Reverse stand-off voltage from GND to Dx GND to Dx 0 V VBR_POS Break-down voltage from Dx to GND Dx to GND. IBR = 1 mA 7 V VBR_NEG Break-down voltage from GND to Dx GND to Dx. IBR = 8 mA 0.6 V CIO Dx to GND or GND to Dx f = 1 MHz, VIO = 2.5 V 1.7 pF ΔCIO Differential capacitance between two Dx pins f = 1 MHz, VIO = 2.5 V 0.02 pF RDYN Dynamic on-resistance Dx IEC clamps Dx to GND or GND to Dx 0.4 Ω

7.7 Timing Requirements

Time from crossing rising VPWR UVLO until CC and SBU OVP FETs are on 3.5 ms dVPWR_OFF/dt Minimum Slew rate allowed to guarantee CC and SBU FETs turnoff during a power off –0.5 V/µs OVER VOLTAGE PROTECTION tOVP_RESPONSE_CC OVP response time on the CC pins. Time from OVP asserted until OVP FETs turnoff 70 ns

www.ti.com SLVSDK3C –SEPTEMBER 2016–REVISED JANUARY 2017 Product Folder Links: TPD6S300 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated Timing Requirements (continued) MIN NOM MAX UNIT tOVP_RESPONSE_SBU OVP response time on the SBU pins. Time from OVP asserted until OVP FETs turnoff 80 ns tOVP_RECOVERY_CC_1 OVP recovery time on the CC pins. Once an OVP has occurred, the minimum time duration until the CC FETs turn back on. OVP must be removed for CC FETs to turn back on 21 29 39 ms tOVP_RECOVERY_SBU_1 OVP recovery time on the SBU pins. Once an OVP has occurred, the minimum time duration until the SBU FETs turn back on. OVP must be removed for SBU FETs to turn back on 21 29 39 ms tOVP_RECOVERY_CC_2 OVP recovery time on the CC pins. Time from OVP Removal until CC FET turns back on, if device has been in OVP > 40 ms 0.5 ms tOVP_RECOVERY_SBU_2 OVP recovery time on the SBU pins. Time from OVP Removal until SBU FET turns back on, if device has been in OVP > 40 ms 0.5 ms tOVP_FLT_ASSERTION Time from OVP asserted to FLT assertion 20 µs tOVP_FLT_DEASSERTION Time from CC FET turnon after an OVP to FLT deassertion 5 ms

7.8 Typical Characteristics

Figure 1. SBU S21 BW Figure 2. SBU Crosstalk Figure 3. SBU Short-to-VBUS 20 V Figure 4. SBU Short-to-VBUS 5 V Figure 5. SBU RON Flatness Figure 6. SBU IEC 61000-4-2 4-kV Response Waveform

8 Detailed Description

8.1 Overview

The TPD6S300 is a single chip USB Type-C port protection solution that provides 20-V Short-to-VBUS overvoltage and IEC ESD protection. Due to the small pin pitch of the USB Type-C connector and non-compliant USB Type-C cables and accessories, the VBUS pins can get shorted to the CC and SBU pins inside the USB Type-C connector. Because of this short-to-VBUS event, the CC and SBU pins need to be 20-V tolerant, to support protection on the full USB PD voltage range. Even if a device does not support 20-V operation on VBUS, non complaint adaptors can start out with 20-V VBUS condition, making it necessary for any USB Type-C device to support 20 V protection. The TPD6S300 integrates four channels of 20-V Short-to-VBUS overvoltage protection for the CC1, CC2, SBU1, and SBU2 pins of the USB Type-C connector. Additionally, IEC 61000-4-2 system level ESD protection is required in order to protect a USB Type-C port from ESD strikes generated by end product users. The TPD6S300 integrates eight channels of IEC61000-4-2 ESD protection for the CC1, CC2, SBU1, SBU2, DP_T (Top side D+), DM_T (Top Side D–), DP_B (Bottom Side D+), and DM_B (Bottom Side D–) pins of the USB Type-C connector. This means IEC ESD protection is provided for all of the low-speed pins on the USB Type-C connector in a single chip in the TPD6S300. Additionally, high- voltage IEC ESD protection that is 22-V DC tolerant is required for the CC and SBU lines in order to simultaneously support IEC ESD and Short-to-VBUS protection; there are not many discrete market solutions that can provide this kind of protection. This high-voltage IEC ESD diode is what the TPD6S300 integrates, specifically designed to guarantee it works in conjunction with the overvoltage protection FETs inside the device. This sort of solution is very hard to generate with discrete components.

C_SBU1 C_SBU2 SBU1 SBU2 ESD Clamps FLT C_CC1 C_CC2 CC1 CC2 ESD Clamps D1 D2 RD /VPWR RD /VPWR RPD_G1 RPD_G2 System Clamps System Clamps VBIAS Copyright © 2016, Texas Instruments Incorporated TPD6S300 SLVSDK3C –SEPTEMBER 2016–REVISED JANUARY 2017 www.ti.com Product Folder Links: TPD6S300 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins): 24-VDC Tolerant The TPD6S300 provides 4-channels of Short-to-VBUS Overvoltage Protection for the CC1, CC2, SBU1, and SBU2 pins of the USB Type-C connector. The TPD6S300 is able to handle 24-VDC on its C_CC1, C_CC2, C_SBU1, and C_SBU2 pins. This is necessary because according to the USB PD specification, with VBUS set for 20-V operation, the VBUS voltage is allowed to legally swing up to 21 V, and 21.5 V on voltage transitions from a different USB PD VBUS voltage. The TPD6S300 builds in tolerance up to 24-VBUS to provide margin above this 21.5 V specification to be able to support USB PD adaptors that may break the USB PD specification. When a short-to-VBUS event occurs, ringing happens due to the RLC elements in the hot-plug event. With very low resistance in this RLC circuit, ringing up to twice the settling voltage can appear on the connector. More than 2x ringing can be generated if any capacitor on the line derates in capacitance value during the short-to-VBUS event. This means that more than 44 V could be seen on a USB Type-C pin during a Short-to-VBUS event. The TPD6S300 has built in circuit protection to handle this ringing. The diode clamps used for IEC ESD protection also clamp the ringing voltage during the short-to-VBUS event to limit the peak ringing to around 30 V. Additionally, the overvoltage protection FETs integrated inside the TPD6S300 are 30-V tolerant, therefore being capable of supporting the high-voltage ringing waveform that is experienced during the short-to-VBUS event. The well designed combination of voltage clamps and 30-V tolerant OVP FETs insures the TPD6S300 can handle Short-to-VBUS hot-plug events with hot-plug voltages as high as 24-VDC.

USB Type-C CC/PD controller will have built in HBM ESD protection. full-featured USB Type-C and PD controller. Figure 29. TPD6S300 Protecting the TPS65982 During a Short-to-VBUS Event SBU2, DP_T (Top side D+), DM_T (Top Side D–), DP_B (Bottom Side D+), and DM_B (Bottom Side D–) pins. both IEC ESD and Short-to-VBUS protection requirements in a single device.

8.3.3 CC1, CC2 Overvoltage Protection FETs 600 mA Capable for Passing VCONN Power

if operating in a USB PD alternate mode, greater power levels are allowed on the VCONN line.

SLVSDK3C –SEPTEMBER 2016–REVISED JANUARY 2017 www.ti.com Product Folder Links: TPD6S300 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Feature Description (continued) When a USB Type-C port is configured for VCONN and using the TPD6S300, this VCONN current flows through the OVP FETs of the TPD6S300. Therefore, the TPD6S300 has been designed to handle these currents and have an RON low enough to provide a specification compliant VCONN voltage to the active cable. The TPD6S300 is designed to handle up to 600 mA of DC current to allow for alternate mode support in addition to the standard 1 W required by the USB Type-C specification.

8.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices

An important feature of USB Type-C and USB PD is the ability for this connector to serve as the sole power source to mobile devices. With support up to 100 W, the USB Type-C connector supporting USB PD can be used to power a whole new range of mobile devices not previously possible with legacy USB connectors. When the USB Type-C connector is the sole power supply for a battery powered device, the device must be able to charge from the USB Type-C connector even when its battery is dead. In order for a USB Type-C power adapter to supply power on VBUS, RD pull-down resistors must be exposed on the CC pins. These RD resistors are typically included inside a USB Type-C CC/PD controller. However, when the TPD6S300 is used to protect the USB Type-C port, the OVP FETs inside the device isolate these RD resistors in the CC/PD controller when the mobile device has no power. This is because when the TPD6S300 has no power, the OVP FETs are turned off to guarantee overvoltage protection in a dead battery condition. Therefore, the TPD6S300 integrates high- voltage, dead battery RD pull-down resistors to allow dead battery charging simultaneously with high-voltage OVP protection. If dead battery support is required, short the RPD_G1 pin to the C_CC1 pin, and short the RPD_G2 pin to the C_CC2 pin. This connects the dead battery resistors to the connector CC pins. When the TPD6S300 is unpowered, and the RP pull-up resistor is connected from a power adaptor, this RP pull-up resistor activates the RD resistor inside the TPD6S300. This enables VBUS to be applied from the power adaptor even in a dead battery condition. Once power is restored back to the system and back to the TPD6S300 on its VPWR pin, the TPD6S300 removes its RD pull-down resistor and turnon its OVP FETs within 3.5 ms to guarantee the RD pull- down resistor inside the CC/PD Controller is exposed within 10 ms. This is by design, because if the RD pull- down resistor is not exposed within 10 ms, the power adaptor can legally interpret this behavior as a port disconnect and remove VBUS. If desiring to power the CC/PD controller during dead battery mode and if the CC/PD Controller is configured as a DRP, it is critical that the TPD6S300 be powered before or at the same time that the CC/PD controller is powered. It is also critical that when unpowered, the CC/PD controller also expose its dead battery resistors. When the TPD6S300 gets powered, it exposes the CC pins of the CC/PD controller within 3.5 ms. Once the TPD6S300 turns on, the RD pull-down resistors of the CC/PD controller must be present immediately, in order to guarantee the power adaptor connected to power the dead battery device keeps its VBUS turned on. If the power adaptor sees any change to its CC voltage for more than 10 ms, it can disconnect VBUS. This removes power from the device with its battery still not sufficiently charged, which consequently removes power from the CC/PD controller and the TPD6S300. Then the RD resistors of the TPD6S300 are exposed again, connect the power adaptor's VBUS to start the cycle over. This creates an infinite loop, never or very slowly charging the mobile device. If the CC/PD Controller is configured for DRP and has started its DRP toggle before the TPD6S300 turns on, this DRP toggle is unable to guarantee that the power adaptor does not disconnect from the port. Therefore, it is recommended if the CC/PD controller is configured for DRP, that its dead battery resistors be exposed as well, and that they remain exposed until the TPD6S300 turns on. This is typically accomplished by powering the TPD6S300 at the same time as the CC/PD controller when powering the CC/PD controller in dead battery operation. If dead battery charging is not required in your application, connect the RPD_G1 and RPD_G2 pins to ground. 8.3.5 3-mm × 3-mm WQFN Package The TPD6S300 comes in a small, 3-mm × 3-mm WQFN package, greatly reducing the size of implementing a similar protection solution discretely. The WQFN package allows support for a wider range of PCB designs. Additionally, the pin-out of the TPD6S300 was designed to optimize routing with the TPS6598x family of USB Type-C/PD controllers.

8.4 Device Functional Modes

the conditions on any of the other pins. Table 1. Device Mode Table

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

TPD6S300 provides adequate system protection as well as insuring that proper system operation is maintained. The following application example explains how to properly design the TPD6S300 into a USB Type-C system.

9.2 Typical Application

Figure 30. TPD6S300 Typical Application Diagram

Figure 31. TPD6S300 Reference Schematic

9.2.1 Design Requirements

protection for the low speed and USB2.0 pins in the USB Type-C connector. Table 2 lists the TPD6S300 design parameters. Table 2. Design Parameters

Table 2. Design Parameters (continued)

9.2.2 Detailed Design Procedure

9.2.2.1 VBIAS Capacitor Selection

have great derating performance, allowing for the best short-to-VBUS performance of the TPD6S300. shows real capacitors recommended to achieve the best performance with the TPD6S300. Table 3. Design Parameters

0402 CC0402KRX7R9BB104

0603 GRM188R71H104KA93D

9.2.2.2 Dead Battery Operation

the OVP FETs are OFF, this isolates the TPS65982s dead battery resistors from the USB Type-C ports CC pins. the C_CC1 pin, and short the RPD_G2 pin to the C_CC2 pin. provides power to the TPS65982, turning the PD controller on, and allowing the battery to begin to charge. However, this application requires 100 W charging in dead battery mode, so VBUS at 20 V and 5 A is required. TPD6S300 is turned on simultaneously.

10 ms, the power adaptor interprets this as a disconnect and remove VBUS. operation with the correct voltages on its CC pins. higher power levels, allowing 100-W operation in dead battery mode. to the USB Type-C connector.

9.2.2.3 CC Line Capacitance

Table 4. USB PD cReceiver Specification external CC capacitor for this system, and shows that an external CC capacitor is required. Table 5. CC Line Capacitor Calculation TPD6S300 capacitance 60 120 pF From the table.

9.2.2.4 Additional ESD Protection on CC and SBU Lines

market which break the USB Type-C specification.

the CC or SBU line, this allows the diode to conduct indefinitely, destroying the diode.

9.2.2.5 FLT Pin Operation

designer desires the system to respond to a Short-to-VBUS event. configuration in an active cable or in the other PD controller, so it is best to detach and reconfigure the port. as a DRP, using the FLT pin is recommended.

9.2.2.6 How to Connect Unused Pins

If either the RPD_Gx pins or any of the Dx pins are unused in a design, they must be connected to GND.

9.2.3 Application Curves

Figure 32. TPD6S300 and TPS65982 Turning on in Dead Figure 33. TPD6S300 Protecting the TPS65982 During a

10 Power Supply Recommendations

The VPWR pin provides power to all the circuitry in the TPD6S300. It is recommended a 1-µF decoupling capacitor is placed as close as possible to the VPWR pin. If USB PD is desired to be operated in dead battery conditions, it is critical that the TPD6S300 share the same power supply as the PD controller in dead battery boot-up (such as sharing the same dead battery LDO). See the CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices section for more details.

11 Layout

11.1 Layout Guidelines

Place the bypass capacitors as close as possible to the VPWR pin, and ESD protection capacitor as close as possible to the VBIAS pin. Capacitors must be attached to a solid ground. This minimizes voltage disturbances during transient events such as short-to-VBUS and ESD strikes.
The USB2.0 and SBU lines must be routed as straight as possible and any sharp bends must be minimized. Standard ESD recommendations apply to the C_CC1, C_CC2, C_SBU1, C_SBU2, D1, D2, D3, and D4 pins as well:
The optimum placement for the device is as close to the connector as possible: – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TPD6S300 and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling.
It is best practice to not via up to the D1, D2, D3, and D4 pins from a trace routed on another layer. Rather, it is better to via the trace to the layer with the Dx pin, and to continue that trace on that same layer. See the ESD Protection Layout Guide application report, section 1.3 for more details.

11.2 Layout Example

Figure 34. TPD6S300 Typical Layout

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following: TPD6S300 Evaluation Module User's Guide

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. USB Type-C is a trademark of USB Implementers Forum. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPD6S300RUKR Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 6S30 TPD6S300RUKR.A Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 6S30 TPD6S300RUKRG4 Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 6S30 TPD6S300RUKRG4.A Active Production WQFN (RUK) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 6S30 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD6S300RUKR WQFN RUK 20 3000 346.0 346.0 33.0 TPD6S300RUKRG4 WQFN RUK 20 3000 346.0 346.0 33.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRUK 20 PLASTIC QUAD FLATPACK - NO LEAD3 x 3, 0.4 mm pitch 4229651/A

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 20X 0.25 0.15 1.7 0.05 20X 0.5 0.3

0.8 MAX

(DIM A) TYP OPT 02 SHOWN 0.05 0.00 16X 0.4 1.6 A 3.1 2.9 B 3.1 2.9 0.25 0.15 0.5 0.3 WQFN - 0.8 mm max heightRUK0020B PLASTIC QUAD FLATPACK - NO LEAD 4222676/A 02/2016 DIMENSION A OPTION 01 (0.1) OPTION 02 (0.2) PIN 1 INDEX AREA 0.08 C SEATING PLANE 5 11 6 10 20 16 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 EXPOSED THERMAL PAD

21 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

0.05 MAX

20X (0.2) 20X (0.6) ( ) TYP VIA 0.2 16X (0.4) (2.8) (2.8) (0.6) TYP ( 1.7) (R ) TYP 0.05 WQFN - 0.8 mm max heightRUK0020B PLASTIC QUAD FLATPACK - NO LEAD 4222676/A 02/2016 SYMM 6 10 1620 SYMM LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 20X (0.6) 20X (0.2) 16X (0.4) (2.8) (2.8) 4X ( 0.75) (0.47) TYP (0.47) TYP (R ) TYP0.05 WQFN - 0.8 mm max heightRUK0020B PLASTIC QUAD FLATPACK - NO LEAD 4222676/A 02/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 21: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 6 10 1620

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Product Information

TPD6S300RUKRG4 specifications and overview.

Summary

TPD6S300 USB Type-C™ Port Protector: Short-to-VBUS Overvoltage and IEC ESD Protection REVISED JANUARY 2017

Description

TPD6S300 USB Type-C™ Port Protector: Short-to-VBUS Overvoltage and IEC ESD Protection REVISED JANUARY 2017

Source title TPD6S300RUKRG4 Datasheet(PDF) - Texas Instruments

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