TPD4E001DRLRG4

TPD4E001_V02 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 30

Technical content

0.1□µF VCC USB Controller RT VBUS GND VBUS GND Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD4E001 SLLS682O –JULY 2006–REVISED JULY 2019 TPD4E001Low-Capacitance4-ChannelESD-ProtectionforHigh-SpeedDataInterfaces

1 Features

1• IEC 61000-4-2 ESD Protection (Level 4) – ±8-kV Contact Discharge – ±15-kV Air-Gap Discharge

• 5.5-A Peak Pulse Current (8/20-µs Pulse)
• IO Capacitance: 1.5 pF (Typical)
• Low Leakage Current: 1 nA (Maximum)
• Low Supply Current: 1 nA
• 0.9-V to 5.5-V Supply-Voltage Range
• Space-Saving DRL, DBV, DCK, DPK, and DRS Package Options
• Alternate 2, 3, 6-Channel options Available: TPD2E001, TPD3E001, TPD6E001

2 Applications

• USB 2.0
• Ethernet
• FireWire™ Serial Bus
• LVDS
• SVGA Video Connections
• Glucose Meters

3 Description

The TPD4E001 is a four-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array. The TPD4E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device has a 1.5-pF IO capacitance per channel, making it ideal for use in high-speed data IO interfaces. The ultra low leakage current (< 1 nA maximum) is suitable for precision analog measurements in applications like glucose meters and heart rate monitors. The TPD4E001 is available in DRL(SOT), DBV (SOT- 23), DCK (SC-70), DRS (QFN), and DPK (PUSON) packages and is specified for –40°C to +85°C operation. See also the TPD4E1U06DCKR and TPD4E1U06DBVR which are p2p compatible with the TPD4E001DCKR and TPD4E001DBVR. These devices offer higher IEC protection, lower capacitance, lower clamping voltage, and eliminate the input capacitor requirement. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPD4E001 SOT (6) 1.60 mm × 1.20 mm 2.90 mm × 1.60 mm SC70 (6) 2.00 mm × 1.25 mm USON (6) 1.60 mm × 1.60 mm SON (6) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Schematic

SLLS682O –JULY 2006–REVISED JULY 2019 www.ti.com Product Folder Links: TPD4E001 Submit Documentation Feedback Copyright © 2006–2019, Texas Instruments Incorporated Table of Contents

11.3 Receiving Notification of Documentation Updates 12

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision N (March 2018) to Revision O Page Changes from Revision M (May 2017) to Revision N Page Changes from Revision L (May 2016) to Revision M Page Changes from Revision K (January 2015) to Revision L Page Changes from Revision J (December 2013) to Revision K Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision I (September 2012) to Revision J Page

www.ti.com SLLS682O –JULY 2006–REVISED JULY 2019 Product Folder Links: TPD4E001 Submit Documentation FeedbackCopyright © 2006–2019, Texas Instruments Incorporated Changes from Revision H (August 2012) to Revision I Page Changes from Revision G (December 2011) to Revision H Page Changes from Revision F (May 2011) to Revision G Page Changes from Revision E (April 2011) to Revision F Page Changes from Revision C (April 2007) to Revision D Page

SLLS682O –JULY 2006–REVISED JULY 2019 www.ti.com Product Folder Links: TPD4E001 Submit Documentation Feedback Copyright © 2006–2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

NAME DRS, DRL, DPK DBV, DCK TPD4E001R GND 3 2 5 — Ground IOx 1 1 1 I ESD-protected channel 2 3 3 4 4 4 5 6 6 VCC 6 5 2 I Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor Exposed thermal pad (DRS package only) — Exposed thermal pad. Connect to GND or leave floating

www.ti.com SLLS682O –JULY 2006–REVISED JULY 2019 Product Folder Links: TPD4E001 Submit Documentation FeedbackCopyright © 2006–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC –0.3 7 V VI/O IO voltage tolerance –0.3 VCC + 0.3 V I(Surge) IEC 61000-4-5 peak pulse current (TP = 8/20 µs), IOx pins 5.5 A P(Surge) IEC 61000-4-5 peak pulse power (TP = 8/20 µs), IOx pins 100 W TJ Junction temperature 150 °C Bump temperature (soldering) Infrared (15 s) 220 Vapor phase (60 s) 215 Lead temperature (soldering, 10 s) 300 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings— JEDEC Specification

TPD4E001 in DRS, DRL, and DPK Packages V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except 1, 2, 4, and ±2000 VPins 1, 2, 4, and 5 ±15000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) All pins ±1000 TPD4E001 in DBV and DCK Packages V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except 1, 3, 4, and ±2000 VPins 1, 3, 4, and 6 ±15000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) All pins ±1000

6.3 ESD Ratings— IEC Specification

TPD4E001 in DRS, DRL, and DPK Packages V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge All pins ±8000 V IEC 61000-4-2 air-gap discharge All pins ±15000 TPD4E001 in DBV and DCK Packages V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge All pins ±8000 V IEC 61000-4-2 air-gap discharge All pins ±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT TA Operating free-air temperature –40 85 °C Operating voltage VCC pin 0.9 5.5 V IO1, IO2 pins 0 VCC

SLLS682O –JULY 2006–REVISED JULY 2019 www.ti.com Product Folder Links: TPD4E001 Submit Documentation Feedback Copyright © 2006–2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Thermal Information

THERMAL METRIC(1) TPD4E001 UNITDRL (SOT) DBV (SOT) DCK (SC70) DPK (USON) DRS (SON)

6 PINS 6 PINS 6 PINS 6 PINS 6 PINS

ψJB Junction-to-board characterization parameter 61 107.1 54.1 209.3 64.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 29.9 °C/W (1) Typical values are at VCC = 5 V and TA = 25°C. (2) Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to ICE61000-4-5.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted), VCC = 5 V ± 10% PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VCC Supply voltage 0.9 5.5 V ICC Supply current 1 100 nA VF Diode forward voltage IF = 10 mA 0.65 0.95 V VBR Breakdown Voltage IBR = 10 mA 11 V VC Channel clamp voltage TA = 25°C, ±15-kV HBM, IF = 10 A Positive transients VCC + 25 V Negative transients –25 TA = 25°C, ±8-kV contact discharge (IEC 61000-4-2), IF = 24 A Positive transients VCC + 60 Negative transients –60 TA = 25°C, ±15-kV air-gap discharge (IEC 61000-4-2), IF = 45 A Positive transients VCC + 100 Negative transients –100 Surge strike on IO pin, GND pin grounded, IPP = 5 A, 8/20 µs(2) Positive transients 17 VRWM Reverse stand-off voltage IO pin to GND pin 5.5 V II/O Channel leakage current Vi/o = GND to VCC ±1 nA CI/O Channel input capacitance VCC = 5 V, bias of VCC/2; ƒ = 10 MHz 1.5 pF

6.7 Typical Characteristics

Figure 1. IO Capacitance vs IO Voltage (VCC = 5 V) Figure 2. IO Leakage Current vs Temperature (VCC = 5.5 V) Figure 3. Peak Pulse Waveform, VCC = 5.5 V

SLLS682O –JULY 2006–REVISED JULY 2019 www.ti.com Product Folder Links: TPD4E001 Submit Documentation Feedback Copyright © 2006–2019, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPD4E001 is a four-channel transient voltage suppressor (TVS) based ESD protection diode array. The TPD4E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device has a 1.5-pF IO capacitance per channel, making it ideal for use in high-speed data IO interfaces. The ultra-low leakage current (<1 nA maximum) is suitable for precision analog measurements in applications like glucose meters and heart rate monitors.

7.2 Functional Block Diagram

7.3 Feature Description

The TPD4E001 is a uni-directional ESD protection device with low capacitance. The device is constructed with a central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. This central ESD clamp is also connected to VCC to provide protection for the VCC line. Each IO line is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 level 4 international standard. The TPD4E001's low loading capacitance makes it ideal for protection high-speed signal terminals.

7.4 Device Functional Modes

The TPD4E001 is a passive-integrated circuit that activates whenever voltages above VBR or below the lower diodes Vforward (–0.6 V) are present upon the circuit being protected. During ESD events, voltages as high as ±15 kV can be directed to ground and VCC via the internal diode network. Once the voltages on the protected lines fall below the trigger voltage of the TPD4E001 (usually within 10s of nano-seconds) the device reverts back to a high-impedance state.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. to a tolerable level to the protected IC.

8.2 Typical Application

Figure 4. Typical Application Schematic

8.2.1 Design Requirements

For this design example, a single TPD4E001 is used to protect all the pins of two USB2.0 connectors. Given the USB application, the following parameters in Table 1 are known. Table 1. Design Parameters

8.2.2 Detailed Design Procedure

1. Place the TPD4E001 solution close to the connectors. This allows the TPD4E001 to take away the energy

associated with ESD strike before it reaches the internal circuitry of the system board.

1. Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin

during the ESD strike event.

1. Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD4E001

associated with the ESD strike.

1. Leave the unused IO pins floating. In this example of protecting two USB ports, none of the IO pins are left
2. The VCC pin can be connected in two different ways:

8.2.3 Application Curve

Figure 5. TPD4E001DRL IEC61000-4-2 Voltage Clamp Waveform 8-kV Contact

9 Power Supply Recommendations

maximum voltage specifications for each pin are not violated.

10 Layout

10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Example

IO2 is D+ and D–, respectively, of USB port 1. IO3 and IO4 is D– and D+, respectively, of USB port 2. Figure 6. Routing With DRL Package

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

• Reading and Understanding an ESD Protection Datasheet
• ESD Layout Guide

11.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

11.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments. FireWire is a trademark of Apple Inc. All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 27-Jul-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples HPA00782DRLR ACTIVE SOT-5X3 DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (2C7, 2CR) (2CG, 2CH) TPD4E001DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 (NFY5, NFYF) (NFYP, NFYS) TPD4E001DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (2CF, 2CR) (2CP, 2CP) 2CH TPD4E001DPKR ACTIVE USON DPK 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 TPD4E001DPKT ACTIVE USON DPK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 TPD4E001DRLR ACTIVE SOT-5X3 DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2C7, 2CR) (2CG, 2CH) TPD4E001DRLRG4 ACTIVE SOT-5X3 DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (2C7, 2CR) (2CG, 2CH) TPD4E001DRSR ACTIVE SON DRS 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWM TPD4E001RDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 NRYF (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

www.ti.com 27-Jul-2019 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPD4E001 :

• Automotive: TPD4E001-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD4E001DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TPD4E001DCKR SC70 DCK 6 3000 183.0 183.0 20.0 TPD4E001DCKR SC70 DCK 6 3000 180.0 180.0 18.0 TPD4E001DPKR USON DPK 6 5000 184.0 184.0 19.0 TPD4E001DPKT USON DPK 6 250 184.0 184.0 19.0 TPD4E001DRLR SOT-5X3 DRL 6 4000 183.0 183.0 20.0 TPD4E001DRSR SON DRS 6 1000 367.0 367.0 35.0 TPD4E001RDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2019 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95

1.45 MAX

0.15

0.00 TYP

6X 0.50 0.25 0.6

0.3 TYP

0 TYP

1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

6X (1.1) 6X (0.6) (2.6) 2X (0.95) (R0.05) TYP 4214840/B 03/2018 SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 1.7 1.5 4X 0.5 2X 1 6X 0.3 0.1

0.6 MAX

6X 0.18 0.08 6X 0.4 0.2 TYP0.05 0.00 6X 0.27 0.15 B 1.3 1.1 A NOTE 3 1.7 1.5 SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE 4223266/A 09/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 6 PIN 1 ID AREA SEATING PLANE 0.05 C SCALE 8.000

0.1 C A B

0.05 SYMM SYMM

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

6X (0.67) 6X (0.3) (1.48) 4X (0.5) (R0.05) TYP 4223266/A 09/2016 SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:30X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDERMASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN (1.48) 4X (0.5) 6X (0.67) 6X (0.3) (R0.05) TYP SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE 4223266/A 09/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X SYMM SYMM 3 4

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated