TPD4E001 TI | Alldatasheet

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Technical content

TPD4E001 Low-Capacitance 4-Channel ESD-Protection for High-Speed Data Interfaces

1 Features

  • IEC 61000-4-2 ESD Protection (Level 4) – ±8kV Contact Discharge – ±15kV Air-Gap Discharge
  • 5.5A Peak Pulse Current (8/20µs Pulse)
  • IO Capacitance: 1.5pF (Typical)
  • Low Leakage Current: 1nA (Maximum)
  • Low Supply Current: 1nA
  • 0.9V to 5.5V Supply-Voltage Range
  • Space-Saving DRL, DBV, DCK, DPK, and DRS Package Options
  • Alternate 2, 3, 6-Channel options Available: TPD2E001, TPD3E001, TPD6E001

2 Applications

  • USB 2.0
  • Ethernet
  • FireWire™ Serial Bus
  • LVDS
  • SVGA Video Connections
  • Glucose Meters

3 Description

The TPD4E001 is a four-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array. The TPD4E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device has a 1.5pF IO capacitance per channel, making it ideal for use in high-speed data IO interfaces. The ultra low leakage current (< 1nA maximum) is suitable for precision analog measurements in applications like glucose meters and heart rate monitors. The TPD4E001 is available in DRL(SOT), DBV (SOT-23), DCK (SC-70), DRS (QFN), and DPK (PUSON) packages and is specified for –40°C to +85°C operation. See also the TPD4E1U06DCKR and TPD4E1U06DBVR which are p2p compatible with the TPD4E001DCKR and TPD4E001DBVR. These devices offer higher IEC protection, lower capacitance, lower clamping voltage, and eliminate the input capacitor requirement.

Package Information

PART NUMBER PACKAGE (1) BODY SIZE (NOM) TPD4E001 SOT (6) 1.60mm × 1.20mm 2.90mm × 1.60mm SC70 (6) 2.00mm × 1.25mm USON (6) 1.60mm × 1.60mm SON (6) 3.00mm × 3.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. IO3 IO4 GND IO2 IO1 0.1□µF VCC USB Controller RT VBUS GND VBUS GND Application Schematic TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

SLLS682P – JULY 2006 – REVISED JANUARY 2025 www.ti.com

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4 Pin Configuration and Functions

Figure 4-1. DRL Package 6-Pin SOT Top View IO3 GND VCC IO41 IO1 IO2 Figure 4-2. DBV or DCK Package 6-Pin SOT or SC70 Top View IO1 IO2 GND VCC IO4 IO3 GND 3 4 Figure 4-3. DRS Package 6-Pin SON Top View IO1 IO2 GND VCC IO4 IO3 3 4 6 Figure 4-4. DPK Package 6-Pin USON Top View IO1 VCC IO2 IO3 GND IO4 Figure 4-5. TPD4E001R DBV Package 6-Pin SOT Top View Pin Functions PIN I/O DESCRIPTION NAME DRS, DRL, DPK DBV, DCK TPD4E001R GND 3 2 5 — Ground IOx 1 1 1 I ESD-protected channel 2 3 3 4 4 4 5 6 6 VCC 6 5 2 I Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor Exposed thermal pad (DRS package only) — Exposed thermal pad. Connect to GND or leave floating www.ti.com TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC –0.3 7 V VI/O IO voltage tolerance –0.3 VCC + 0.3 V I(Surge) IEC 61000-4-5 peak pulse current (TP = 8/20µs), IOx pins 5.5 A P(Surge) IEC 61000-4-5 peak pulse power (TP = 8/20µs), IOx pins 100 W TJ Junction temperature 150 °C Bump temperature (soldering) Infrared (15s) 220 Vapor phase (60s) 215 Lead temperature (soldering, 10s) 300 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 ESD Ratings—JEDEC Specification

TPD4E001 in DRS, DRL, and DPK Packages V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/ JEDEC JS-001(1) All pins except 1, 2, 4, and 5 ±2000 VPins 1, 2, 4, and 5 ±15000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) All pins ±1000 TPD4E001 in DBV and DCK Packages V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/ JEDEC JS-001(1) All pins except 1, 3, 4, and 6 ±2000 VPins 1, 3, 4, and 6 ±15000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) All pins ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 ESD Ratings—IEC Specification

TPD4E001 in DRS, DRL, and DPK Packages V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge All pins ±8000 V IEC 61000-4-2 air-gap discharge All pins ±15000 TPD4E001 in DBV and DCK Packages V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge All pins ±8000 V IEC 61000-4-2 air-gap discharge All pins ±15000

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT TA Operating free-air temperature –40 85 °C Operating voltage VCC pin 0.9 5.5 V IO1, IO2 pins 0 VCC TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 www.ti.com

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5.5 Thermal Information

THERMAL METRIC(1) TPD4E001 UNITDRL (SOT) DBV (SOT) DCK (SC70) DPK (USON) DRS (SON)

6 PINS 6 PINS 6 PINS 6 PINS 6 PINS

ψJB Junction-to-board characterization parameter 61 107.1 54.1 209.3 64.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 29.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted), VCC = 5 V ± 10% PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VCC Supply voltage 0.9 5.5 V ICC Supply current 1 100 nA VF Diode forward voltage IF = 10mA 0.65 0.95 V VBR Breakdown Voltage IBR = 10mA 11 V VC Channel clamp voltage TA = 25°C, ±15kV HBM, IF = 10A Positive transients VCC + 25 V Negative transients –25 TA = 25°C, ±8kV contact discharge (IEC 61000-4-2), IF = 24A Positive transients VCC + 60 Negative transients –60 TA = 25°C, ±15kV air-gap discharge (IEC 61000-4-2), IF = 45A Positive transients VCC + 100 Negative transients –100 Surge strike on IO pin, GND pin grounded, IPP = 5A, 8/20µs(2) Positive transients 17 VRWM Reverse stand-off voltage IO pin to GND pin 5.5 V II/O Channel leakage current Vi/o = GND to VCC ±1 nA CI/O Channel input capacitance VCC = 5V, bias of VCC/2; ƒ = 10MHz 1.5 pF (1) Typical values are at VCC = 5V and TA = 25°C. (2) Non-repetitive current pulse 8/20µs exponentially decaying waveform according to ICE61000-4-5. www.ti.com TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5

5.7 Typical Characteristics

IO Voltage (V) 1.00 1.20 1.40 1.60 1.80 2.00 2.20 IO Capacitance (pF) Figure 5-1. IO Capacitance vs IO Voltage (VCC = 5V) 100 1000 –40 25 45 65 85 Temperature□(°C) IO□Leakage□Current□(pA) Figure 5-2. IO Leakage Current vs Temperature (VCC = 5.5V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 5 10 15 20 25 30 35 40 45 50 Time ( s) μ 100 I (A)PK P (W) PK Power (W) Current (A) Figure 5-3. Peak Pulse Waveform, VCC = 5.5V TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 www.ti.com

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6 Detailed Description

6.1 Overview

The TPD4E001 is a four-channel transient voltage suppressor (TVS) based ESD protection diode array. The TPD4E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device has a 1.5pF IO capacitance per channel, making it ideal for use in high- speed data IO interfaces. The ultra-low leakage current (<1nA maximum) is suitable for precision analog measurements in applications like glucose meters and heart rate monitors.

6.2 Functional Block Diagram

6.3 Feature Description

The TPD4E001 is a uni-directional ESD protection device with low capacitance. The device is constructed with a central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. This central ESD clamp is also connected to V CC to provide protection for the V CC line. Each IO line is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 level 4 international standard. The TPD4E001's low loading capacitance makes it ideal for protection high-speed signal terminals.

6.4 Device Functional Modes

The TPD4E001 is a passive-integrated circuit that activates whenever voltages above V BR or below the lower diodes Vforward (–0.6V) are present upon the circuit being protected. During ESD events, voltages as high as ±15kV can be directed to ground and V CC via the internal diode network. Once the voltages on the protected lines fall below the trigger voltage of the TPD4E001 (usually within 10s of nano-seconds) the device reverts back to a high-impedance state. www.ti.com TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

7.1 Application Information

The TPD4E001 is a diode array type Transient Voltage Suppressor (TVS) which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low R DYN of the triggered TVS holds this voltage, V CLAMP, to a tolerable level to the protected IC.

7.2 Typical Application

0.1□µF VCC USB Controller RT VBUS GND VBUS GND Figure 7-1. Typical Application Schematic

7.2.1 Design Requirements

For this design example, a single TPD4E001 is used to protect all the pins of two USB2.0 connectors. Given the USB application, the following parameters in Table 7-1 are known. Table 7-1. Design Parameters DESIGN PARAMETER VALUE Signal range on IO1, IO2, IO3, and IO4 0V to 3.6V Signal voltage range on VCC 0V to 5.25V Operating Frequency 240MHz

7.2.2 Detailed Design Procedure

When placed near the USB connectors, the TPD4E001 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD4E001 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/ design guidelines must be followed: 1. Place the TPD4E001 solution close to the connectors. This allows the TPD4E001 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 www.ti.com

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  1. Place a 0.1μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event. 3. Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD4E001 consumes nA leakage current. But during the ESD event, VCC and GND may see 15A to 30A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike. 4. Leave the unused IO pins floating. In this example of protecting two USB ports, none of the IO pins are left unused. 5. The VCC pin can be connected in two different ways: a. If the VCC pin is connected to the system power supply, the TPD4E001 works as a transient suppressor for any signal swing above VCC + VF. A 0.1μF capacitor on the device VCC pin is recommended for ESD bypass. b. If the VCC pin is not connected to the system power supply, the TPD4E001 can tolerate higher signal swing in the range up to 10V. Please note that a 0.1μF capacitor is still recommended at the VCC pin for ESD bypass.

7.2.3 Application Curve

Figure 7-2 is a capture of the voltage clamping waveform of TPD4E001DRL on IO3 during an 8kV Contact IEC61000-4-2 ESD strike. T i m e ( n s ) Voltage (V) - 1 5 0 1 5 3 0 4 5 6 0 7 5 9 0 1 0 5 1 2 0 1 3 5 1 5 0 - 4 0 - 2 0 2 0 4 0 6 0 8 0 1 0 0 P in 4 Figure 7-2. TPD4E001DRL IEC61000-4-2 Voltage Clamp Waveform 8kV Contact Power Supply Recommendations This device is a passive ESD protection device so there is no need to power it. Take care to make sure that the maximum voltage specifications for each pin are not violated.

8 Layout

8.1 Layout Guidelines

  • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
  • Route the protected traces as straight as possible.
  • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. www.ti.com TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9

8.2 Layout Example

The following is a layout example for protecting two interface ports with the TPD4E001. One example is two USB 2.0 ports, as was discussed in the Section 7 section. For the USB 2.0 example, IO1 and IO2 is D+ and D–, respectively, of USB port 1. IO3 and IO4 is D– and D+, respectively, of USB port 2. VCC GND IO3 IO4 = VIA to GND IO1 IO2 GND 0.1µF Figure 8-1. Routing With DRL Package TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 www.ti.com

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9 Device and Documentation Support

9.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

  • Texas Instruments, Reading and Understanding an ESD Protection Datasheet
  • Texas Instruments, ESD Layout Guide

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

FireWire™ is a trademark of Apple Inc. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision O (July 2019) to Revision P (January 2025) Page Changes from Revision N (March 2018) to Revision O (July 2019) Page www.ti.com TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11

Changes from Revision M (May 2017) to Revision N (March 2018) Page Changes from Revision L (May 2016) to Revision M (May 2017) Page Changes from Revision K (January 2015) to Revision L (May 2016) Page Changes from Revision J (December 2013) to Revision K (October 2014) Page

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information Changes from Revision I (September 2012) to Revision J (November 2013) Page Changes from Revision H (August 2012) to Revision I (September 2012) Page Changes from Revision G (December 2011) to Revision H () Page Changes from Revision F (May 2011) to Revision G (December 2011) Page Changes from Revision E (April 2011) to Revision F (May 2011) Page Changes from Revision C (April 2007) to Revision D (December 2010) Page TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 www.ti.com

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPD4E001 SLLS682P – JULY 2006 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13

www.ti.com 7-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPD4E001DBVR Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (NFY5, NFYF) (NFYP, NFYS) TPD4E001DBVR.B Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 (NFY5, NFYF) (NFYP, NFYS) TPD4E001DCKR Active Production SC70 (DCK) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 (2CF, 2CR) (2CP, 2CP) 2CH TPD4E001DCKR.B Active Production SC70 (DCK) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 (2CF, 2CR) (2CP, 2CP) 2CH TPD4E001DCKRG4 Active Production SC70 (DCK) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2CF 2CP TPD4E001DCKRG4.B Active Production SC70 (DCK) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2CF 2CP TPD4E001DPKR Active Production USON (DPK) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 TPD4E001DPKR.B Active Production USON (DPK) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 TPD4E001DPKRG4 Active Production USON (DPK) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 TPD4E001DPKRG4.B Active Production USON (DPK) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 TPD4E001DPKT Active Production USON (DPK) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 TPD4E001DPKT.B Active Production USON (DPK) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2C7 TPD4E001DRLR Active Production SOT-5X3 (DRL) | 6 4000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2C7, 2CR) (2CG, 2CH) TPD4E001DRLR.B Active Production SOT-5X3 (DRL) | 6 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 (2C7, 2CR) (2CG, 2CH) TPD4E001DRLRG4 Active Production SOT-5X3 (DRL) | 6 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 (2C7, 2CR) (2CG, 2CH) TPD4E001DRSR Active Production SON (DRS) | 6 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWM TPD4E001DRSR.B Active Production SON (DRS) | 6 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWM TPD4E001DRSRG4 Active Production SON (DRS) | 6 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWM TPD4E001DRSRG4.B Active Production SON (DRS) | 6 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWM TPD4E001RDBVR Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 NRYF TPD4E001RDBVR.B Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 NRYF Addendum-Page 1

www.ti.com 7-Nov-2025 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPD4E001 :

  • Automotive : TPD4E001-Q1 NOTE: Qualified Version Definitions:
  • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD4E001DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TPD4E001DCKR SC70 DCK 6 3000 180.0 180.0 18.0 TPD4E001DCKRG4 SC70 DCK 6 3000 180.0 180.0 18.0 TPD4E001DPKR USON DPK 6 5000 184.0 184.0 19.0 TPD4E001DPKRG4 USON DPK 6 5000 184.0 184.0 19.0 TPD4E001DPKT USON DPK 6 250 184.0 184.0 19.0 TPD4E001DRLR SOT-5X3 DRL 6 4000 210.0 185.0 35.0 TPD4E001DRSR SON DRS 6 1000 353.0 353.0 32.0 TPD4E001DRSRG4 SON DRS 6 1000 353.0 353.0 32.0 TPD4E001RDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.15 2.4 1.8 4X 0.65 1.1 0.8 0.1

0.0 TYP

6X 0.30 0.15 NOTE 5 0.46

0.26 TYP

0 TYP

1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 SOT - 1.1 max heightDCK0006A SMALL OUTLINE TRANSISTOR 4214835/D 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Falls within JEDEC MO-203 variation AB. INDEX AREA PIN 1 NOTE 5

0.1 C A B

0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

6X (0.9) 6X (0.4) (2.2) 4X (0.65) (R0.05) TYP 4214835/D 11/2024 SOT - 1.1 max heightDCK0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) 4X(0.65) 6X (0.9) 6X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0006A SMALL OUTLINE TRANSISTOR 4214835/D 11/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE 1.7 1.5 4X 0.5 2X 1 6X 0.3 0.1

0.6 MAX

6X 0.18 0.08 6X 0.4 0.2 0.05

0.00 TYP

6X 0.27 0.15 2X 0 -10 2X 4 -15 1.3 1.1 1.7 1.5 NOTE 3 SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE 4223266/F 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-293 Variation UAAD 1 6 PIN 1 ID AREA 3 4 SEATING PLANE 0.05 C SCALE 8.000 0.05 C SYMM SYMM A B C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

6X (0.67) 6X (0.3) (1.48) 4X (0.5) (R0.05) TYP 4223266/F 11/2024 SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria. SYMM LAND PATTERN EXAMPLE SCALE:30X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDERMASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN (1.48) 4X (0.5) 6X (0.67) 6X (0.3) (R0.05) TYP SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE 4223266/F 11/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X SYMM SYMM 3 4

www.ti.com PACKAGE OUTLINE C 0.22 0.25 3.0 2.6 2X 0.95 1.45 0.90 0.15 6X 0.50 0.25 0.6

0.3 TYP

1.9 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/G 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT 6X (1.1) 6X (0.6) (2.6) 2X (0.95) (R0.05) TYP 4214840/G 08/2024 SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/G 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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