TPD3E001_15 TI1 | Alldatasheet
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0.1µF ID Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design TPD3E001 SLLS683F –JULY 2006–REVISED OCTOBER 2015 TPD3E001Low-Capacitance3-ChannelESD-ProtectionforHigh-SpeedDataInterfaces
1 Features 3 Description
The TPD3E001 is a three-channel Transient Voltage 1• IEC61000-4-2 Level-4 ESD Protection Suppressor (TVS) based Electrostatic Discharge– ±8-kV IEC 61000-4-2 Contact Discharge (ESD) protection diode array. The TPD3E001 is rated – ±15-kV IEC 61000-4-2 Air-Gap Discharge to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard• 5.5-A Peak Pulse Current (8/20-µs Pulse) (Level 4). This device has a 1.5-pF IO capacitance• I/O Capacitance: 1.5 pF (Typical) per channel, making it ideal for use in high-speed
- Low Leakage Current: 1-nA (Maximum) data IO interfaces. The ultra low leakage current (<1 nA max) is suitable for precision analog• Low Supply Current: 1-nA (Typical) measurements in applications like glucose meters• 0.9-V to 5.5-V Supply-Voltage Range and heart rate monitors.• Space-Saving DRY, DRL, and DRS Package The TPD3E001 is available in space saving DRYOptions (USON), DRL (SOT), and DRS (WSON) packages• Alternate 2-, 4-, and 6-Channel Options Available: and is specified for –40°C to 85°C operation. AlsoTPD2E2U06, TPD4E1U06, and TPD6E001 see TPD2E2U06, TPD4E1U06, and TPD6E001 which are 2, 4, and 6 channel ESD protection
2 Applications options, respectively, for ESD protection diode arrays
with a different number of channels. The TPD2E2U06• End Equipments provides a higher level of IEC ESD protection, when– Blood Glucose Meters compared to the TPDxE001 family, and removes the – Video Surveillance Equipment need for an input capacitor. The TPD4E1U06 removes the need for an input capacitor, provides– Portable Data Terminal higher IEC ESD protection, and provides lower– Industrial Monitor capacitance, when compared to the TPDxE001
- Interfaces family. – USB2.0 Device Information(1) – SDIO PART NUMBER PACKAGE BODY SIZE (NOM)– Precision Analog Interface SOT (5) 1.60 mm × 1.20 mm – SVGA Video Connections TPD3E001 WSON (6) 3.00 mm × 3.00 mm USON (6) 1.45 mm × 1.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Application Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLLS683F –JULY 2006–REVISED OCTOBER 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2013) to Revision F Page
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
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N.C. GND IO2 IO1 1 3 4 GND IO1 GND IO2 3 4 IO3
51 VCC
N.C. 3 4 TPD3E001 www.ti.com SLLS683F –JULY 2006–REVISED OCTOBER 2015
5 Pin Configuration and Functions
NAME DRY NO. DRL NO. DRS NO. IOx 1, 2, 4 1, 2, 4 1, 2, 4 I/O ESD-protected channel GND 3 3 3 GND Ground Power-supply input. Bypass VCC to GND with a 0.1-μFVCC 6 5 6 Power ceramic capacitor. N.C. 5 – 5 – No connection. Not internally connected. Exposed EP – – Thermal GND Exposed thermal pad. Connect to GND or leave floating. Pad Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPD3E001
SLLS683F –JULY 2006–REVISED OCTOBER 2015 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC –0.3 7 V VI/O IO voltage tolerance –0.3 VCC + 0.3 V TJ Junction temperature 150 °C Lead temperature (soldering, 10 s) 300 °C Peak pulse power (tp = 8/20 µs) 90 W Peak pulse power (tp = 8/20 µs) 5.5 A Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±15000 Charged-device model (CDM), per JEDEC specification JESD22- ±1500 C101(2) V(ESD) Electrostatic discharge V IEC 61000-4-2 Contact Discharge ±8000 IEC 61000-4-2 Air-gap Discharge ±15000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Pin 0.9 5.5 Operating Voltage V IOx Pin 0 VCC Operating free-air temperature, TA -40 85 °C
6.4 Thermal Information
THERMAL METRIC(1) DRL (SOT) DRS (WSON) DRY (USON) UNIT
5 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 266.3 91.9 374.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 111.5 106.9 223.4 °C/W RθJB Junction-to-board thermal resistance 84.5 64.8 227.8 °C/W ψJT Junction-to-top characterization parameter 16.0 10.2 52.9 °C/W ψJB Junction-to-board characterization parameter 84.0 64.9 224.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 29.9 87.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
(1) Typical values are at VCC = 5 V and TA = 25°C. (2) Channel clamp voltage is not production tested.
6.6 Typical Characteristics
Figure 1. IO Capacitance vs IO Voltage Figure 2. IO Leakage Current vs Temperature
SLLS683F –JULY 2006–REVISED OCTOBER 2015 www.ti.com
7 Detailed Description
7.1 Overview
The TPD3E001 is a three-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array. The TPD3E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device has a 1.5-pF IO capacitance per channel, making it ideal for use in high-speed data IO interfaces. The ultra low leakage current (< 1 nA maximum) is suitable for precision analog measurements in applications like glucose meters and heart rate monitors. The wide voltage range on VCC (up to 5.5V) gives this device the flexibility to be used in a wide variety applications. Having 3- channels of ESD protection makes this device particularly well suited to protect a micro-AB USB connector, which has three signal lines to be protected (D+, D-, ID). The VBUS pin can also be protected by connecting it to VCC on TPD3E001. Therefore, TPD3E001 is a one-chip solution to provide Level 4 IEC 61000-4-2 ESD protection on every pin of the micro-AB USB connector.
7.2 Functional Block Diagram
7.3 Feature Description
TPD3E001 is a uni-directional ESD protection device with low capacitance. The device is constructed with a central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. This central ESD clamp is also connected to VCC to provide protection for the VCC line. Each IO line is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 level 4 international standard. The TPD3E001's low loading capacitance makes it ideal for protection high-speed signal terminals.
7.4 Device Functional Modes
TPD3E001 is a passive-integrated circuit that activates whenever voltages above VBR or below the lower diodes Vforward (–0.6V) are present upon the circuit being protected. During ESD events, voltages as high as ±15 kV can be directed to ground and VCC via the internal diode network. Once the voltages on the protected lines fall below the trigger voltage of the TPD3E001 (usually within 10's of nano-seconds) the device reverts back to a high- impedance state.
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. tolerable level to the protected IC.
8.2 Typical Application
Figure 3. Typical Application Schematic
8.2.1 Design Requirements
perform the "A" role or the "B' role. This functionality the ID offers is part of the USB On-the-Go (OTG) Standard. AB style connector, plus VCC (VBUS, D+, D-, ID). Given the USB application, the following parameters are known. Table 1. Design Parameters
8.2.2 Detailed Design Procedure
- Place the TPD3E001 solution close to the connectors. This allows the TPD3E001 to take away the energy
associated with ESD strike before it reaches the internal circuitry of the system board.
- Place a 0.1-μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin
during the ESD strike event.
- Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD3E001
enables safe discharge of all the energy associated with the ESD strike.
- Leave the unused IO pins floating. In this example of protecting a micro-AB type USB port, none of the IO
- The VCC pin can be connected in two different ways:
8.2.3 Application Curve
Figure 4. TPD3E001 +8kV Contact IEC61000-4-2 Voltage Clamping Waveform
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9 Power Supply Recommendations
maximum voltage specification for the VCC pin is not violated.
10 Layout
10.1 Layout Guidelines
- The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
- Route the protected traces as straight as possible.
- Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
USB micro-AB connector from IEC ESD, as discussed in the Application and Implementation section. Figure 5. Routing with the DRL Package
SLLS683F –JULY 2006–REVISED OCTOBER 2015 www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following: 1. TPD2E2U06 Data Sheet, SLLSEG9 2. TPD4E1U06 Data Sheet, SLVSBQ9 3. TPD6E001 Data Sheet, SLLS685
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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www.ti.com 25-Feb-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPD3E001DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2BR 2BH TPD3E001DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2BR 2BH TPD3E001DRSR ACTIVE SON DRS 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWL TPD3E001DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2B TPD3E001DRYRG4 ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 2B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
www.ti.com 25-Feb-2015 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Feb-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD3E001DRLR SOT DRL 5 4000 202.0 201.0 28.0 TPD3E001DRSR SON DRS 6 1000 367.0 367.0 35.0 TPD3E001DRYR SON DRY 6 5000 203.0 203.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Feb-2015 Pack Materials-Page 2
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