TPD3E001 TI | Alldatasheet
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(TOP VIEW) DRL PACKAGE (TOP VIEW) QFN□PACKAGE (TOP VIEW) VCCIO1 GND IO2 IO1 GND IO2 IO3 N.C. 3 4 3 4 IO3
51 VCC
N.C. GND IO2 IO1 1 3 4 GND N.C.□-□Not□internally□connected TPD3E001 LOW-CAPACITANCE 3-CHANNEL 15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES SLLS683D JULY 2006 REVISED APRIL 2007 USB 2.0 ESD Protection Exceeds Ethernet 15-kV Human-Body Model (HBM) FireWire 8-kV IEC 61000-4-2 Contact Discharge Video 15-kV IEC 61000-4-2 Air-Gap Discharge Cell Phones Low 1.5-pF Input Capacitance SVGA Video Connections Low 1-nA (Max) Leakage Current Glucosemeters Low 1-nA Supply Current 0.9-V to 5.5-V Supply-Voltage Range 3-Channel Device Space-Saving DRL, DRY, and QFN Package Options Alternate 2-, 4-, and 6-Channel Options Available: TPD2E001, TPD4E001, and TPD6E001 The TPD3E001 is a low-capacitance 15-kV ESD-protection diode array designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steer ESD current pulses to V CC or GND. The TPD3E001 protects against ESD pulses up to 15-kV Human-Body Model (HBM), 8-kV Contact Discharge, and 15-kV Air-Gap Discharge, as specified in IEC 61000-4-2. This device has a 1.5-pF capacitance per channel, making it ideal for use in high-speed data IO interfaces. The TPD3E001 is a triple-ESD structure designed for USB On-the-Go (OTG) and video applications. The TPD3E001 is available in DRL, DRY, and thin QFN packages and is specified for C to C operation. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING 1.6 1.6 SOP DRL TPD3E001DRLR 2BR C to C 1.45 SON DRY TPD3E001DRYR QFN DRS TPD3E001DRSR ZWL (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. FireWire is a trademark of Apple Computer, Inc. PRODUCTION DATA information is current as of publication date. Copyright 2006 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
www.ti.com IO3 GND IO2IO1 VCC TPD3E001 LOW-CAPACITANCE 3-CHANNEL 15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES SLLS683D JULY 2006 REVISED APRIL 2007 LOGIC BLOCK DIAGRAM PIN
DESCRIPTION
NO. NO. NO. IOx ESD-protected channel GND Ground Power-supply input. Bypass V CC to GND with a 0.1- µ F ceramic V CC capacitor. N.C. No connection. Not internally connected. EP EP Exposed pad. Connect to GND. Submit Documentation Feedback
www.ti.com Absolute Maximum Ratings (1) Electrical Characteristics ESD Protection TPD3E001 LOW-CAPACITANCE 3-CHANNEL 15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES SLLS683D JULY 2006 REVISED APRIL 2007 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC 0.3 V V I/O 0.3 V CC 0.3 V T stg Storage temperature range 150 C T J Junction temperature 150 C Infrared (15 220 Bump temperature (soldering) C Vapor phase (60 215 Lead temperature (soldering, 300 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V CC V 10%, T A -40 c to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT V CC Supply voltage 0.9 5.5 V I CC Supply current 100 nA V F Diode forward voltage I F mA 0.65 0.95 V VBR Breakdown Voltage I BR 10mA V Positive transients V CC T A 15-kV HBM, I F A Negative transients T A Positive transients V CC 8-kV Contact Discharge V C Channel clamp voltage (2) V Negative transients (IEC 61000-4-2), I F A T A Positive transients V CC 100 15-kV Air-Gap Discharge Negative transients 100 (IEC 61000-4-2), I F A I i/o Channel leakage current V i/o GND or V CC nA C io Channel input capacitance V CC bias of V CC 1.5 pF (1) Typical values are at V CC V and T A (2) Channel clamp voltage is not production tested. PARAMETER TYP UNIT HBM kV IEC 61000-4-2 Contact Discharge kV IEC 61000-4-2 Air-Gap Discharge kV Submit Documentation Feedback
www.ti.com TYPICAL OPERATING CHARACTERISTICS IO Voltage (V) 1.00 1.20 1.40 1.60 1.80 2.00 2.20 IO Capacitance (pF) 100 1000 –40 25 45 65 85 Temperature□(°C) IO□Leakage□Current□(pA) TPD3E001 LOW-CAPACITANCE 3-CHANNEL 15-kV ESD-PROTECTION ARRAY FOR HIGH-SPEED DATA INTERFACES SLLS683D JULY 2006 REVISED APRIL 2007 IO CAPACITANCE vs IO VOLTAGE CC 5.0 IO LEAKAGE CURRENT vs TEMPERATURE CC 5.5 Submit Documentation Feedback
www.ti.com APPLICATION INFORMATION IO3 GND IO2 IO1 VBUS GND 0.1 µF VCC USB Controller RT RT Detailed connector, the TPD3E001 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD3E001 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/ design guidelines should be followed: Place the TPD3E001 solution close to the connector. This allows the TPD3E001 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. Place a 0.1- µ F capacitor very close to the V CC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event. Ensure that there is enough metallization for the V CC and GND loop. During normal operation, the TPD3E001 consumes nA leakage current. But during the ESD event, V CC and GND may see A to A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike. Leave the unused IO pins floating. The V CC pin can be connected in two different ways: a If the V CC pin is connected to the system power supply, the TPD3E001 works as a transient suppressor for any signal swing above V CC V F A 0.1- µ F capacitor on the device V CC pin is recommended for ESD bypass. b If the V CC pin is not connected to the system power supply, the TPD3E001 can tolerate higher signal swing in the range up to Please note that a 0.1- µ F capacitor is still recommended at the V CC pin for ESD bypass. Submit Documentation Feedback
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPD3E001DRLR ACTIVE SOP DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD3E001DRLRG4 ACTIVE SOP DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD3E001DRSR ACTIVE SON DRS 6 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPD3E001DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPD3E001DRYRG4 ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2007 Addendum-Page 1
TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TPD3E001DRLR DRL 5 SITE 35 180 9 1.78 1.78 0.69 4 8 Q3 TPD3E001DRSR DRS 6 SITE 41 330 12 3.3 3.3 1.1 8 12 Q2 TPD3E001DRYR DRY 6 SITE 48 179 8 1.2 1.65 0.7 4 8 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Pack Materials-Page 1
Device Package Pins Site Length (mm) Width (mm) Height (mm) TPD3E001DRLR DRL 5 SITE 35 202.0 201.0 28.0 TPD3E001DRSR DRS 6 SITE 41 346.0 346.0 29.0 TPD3E001DRYR DRY 6 SITE 48 220.0 205.0 50.0 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Pack Materials-Page 2
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