TPD2E2U06DCK

TPD2E2U06 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 23

Technical content

USB 2.0 Transceiver USB 2.0 Connector GND Vbus Power Supply Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD2E2U06 SLLSEG9C –JUNE 2013–REVISED DECEMBER 2019 TPD2E2U06Dual-ChannelHigh-SpeedESDProtectionDevice

1 Features

1• IEC 61000-4-2 Level 4 – ±25 kV (Contact discharge) – ±30 kV (Air-gap discharge)

• IEC 61000-4-5 Surge protection – 5.5-A Peak pulse current (8/20 µs Pulse)
• IO Capacitance 1.5 pF (Typ)
• DC Breakdown voltage 6.5 V (Min)
• Ultra-Low leakage current 10 nA (Max)
• Low ESD clamping voltage
• Industrial temperature range: –40°C to +125°C
• Small easy-to-route DRL and DCK package

2 Applications

• End Equipment – Set Top Box – Notebook – Server – Electronic Point of Sale (EPOS)
• Interfaces – USB 2.0 – Ethernet – MIPI Bus – LVDS – I2C

3 Description

The TPD2E2U06 is a dual-channel low capacitance TVS diode ESD protection device. The device offers ±25-kV contact and ±30-kV air-gap ESD protection in accordance with the IEC 61000-4-2 standard. The 1.5-pF line capacitance of the TPD2E2U06 makes the device suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C™ . Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPD2E2U06DRL SOT (5) 1.60 mm × 1.20 mm TPD2E2U06DCK SC70 (3) 2.0 mm × 1.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic

SLLSEG9C –JUNE 2013–REVISED DECEMBER 2019 www.ti.com Product Folder Links: TPD2E2U06 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Table of Contents

11.2 Receiving Notification of Documentation Updates 12

12 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision B (May 2015) to Revision C Page Changes from Revision A (June 2013) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

4 GND

www.ti.com SLLSEG9C –JUNE 2013–REVISED DECEMBER 2019 Product Folder Links: TPD2E2U06 Submit Documentation FeedbackCopyright © 2013–2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

IO1 3 1 I/O The IO1 and IO2 pins are an ESD protected channel. Connect these pins to the data line as close to the connector as possible.IO2 5 2 I/O NC 1, 2 — - This pin is not connected and is left floating, grounded, or connected to VCC. GND 4 3 G The GND (ground) pin is connected to ground. (1) Measured at 25°C.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT IPP Peak pulse current (tp = 8/20 μs) 5.5(1) A PPP Peak pulse power (tp = 8/20 μs) DRL package 85(1) W PPP Peak pulse power (tp = 8/20 μs) DCK package 75(1) W Operating temperature –40 125 °C Storage temperature –65 155 °C

SLLSEG9C –JUNE 2013–REVISED DECEMBER 2019 www.ti.com Product Folder Links: TPD2E2U06 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1500 EC 61000-4-2 contact ±25000 EC 61000-4-2 air-gap ±30000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIO Input Pin Voltage 0 5.5 V TA Operating Free Air Temperature -40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TPD2E2U06 UNITDRL DCK

5 PINS 3 PINS

RθJA Junction-to-ambient thermal resistance 286.8 308.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 130.7 170.7 RθJB Junction-to-board thermal resistance 104.8 89.2 ψJT Junction-to-top characterization parameter 25.6 34.2 ψJB Junction-to-board characterization parameter 104.3 88.6 (1) Transmission Line Pulse with 10-ns rise time, 100-ns width. (2) Extraction of RDYN Using least squares fit of TLP characteristics between I = 20 A and I = 30 A. (3) Measured at 25°C.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO < 10 µA 5.5 V VCLAMP IO to GND IPP = 1 A, TLP(1) 9.7 V IPP = 5 A, TLP(1) 12.4 VCLAMP GND to IO IPP = 1 A, TLP(1) 1.9 V IPP = 5 A, TLP(1) 4 RDYN Dynamic resistance DRL package IO to GND(2) 0.5 Ω RDYN Dynamic resistance DRL package GND to IO(2) 0.25 Ω RDYN Dynamic resistance DCK package IO to GND(2) 0.6 Ω RDYN Dynamic resistance DCK package GND to IO(2) 0.4 Ω CL Line capacitance f = 1 MHz, VBIAS = 2.5 V(3) 1.5 1.9 pF CCROSS Channel-to-channel input capacitance Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between channel pins(3) 0.02 0.03 pF

www.ti.com SLLSEG9C –JUNE 2013–REVISED DECEMBER 2019 Product Folder Links: TPD2E2U06 Submit Documentation FeedbackCopyright © 2013–2019, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆CIO-TO-GND Variation of channel input capacitance Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V, channel_x pin to GND – channel_y pin to GND(3) 0.03 0.1 pF VBR Break-down voltage IIO = 1 mA 6.5 8.5 V ILEAK Leakage current VIO = 2.5 V 1 10 nA

6.6 Typical Characteristics

Figure 1. TLP, Data to GND Figure 2. TLP, GND to Data Figure 3. IEC 61000-4-2 Clamping Voltage, +8 kV Contact Figure 4. IEC 61000-4-2 Clamping Voltage, –8 kV Contact Figure 5. IV Curve Figure 6. ILEAK vs Temperature

SLLSEG9C –JUNE 2013–REVISED DECEMBER 2019 www.ti.com Product Folder Links: TPD2E2U06 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPD2E2U06 is a dual-channel low capacitance TVS diode ESD protection device. The device offers ±25-kV contact and ±30-kV air-gap ESD protection in accordance with the IEC 61000-4-2 standard. The 1.5-pF line capacitance of the TPD2E2U06 makes the device suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C.

7.2 Functional Block Diagram

7.3 Feature Description

The TPD2E2U06 is a dual-channel low capacitance TVS diode ESD protection device. The device offers ±25-kV contact and ±30-kV air-gap ESD protection in accordance with the IEC 61000-4-2 standard. The 1.5-pF line capacitance of the TPD2E2U06 makes the device suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C.

7.3.1 IEC 61000-4-2 Level 4

The I/O pins can withstand ESD events up to ±25-kV contact and ±30-kV air. An ESD/surge clamp diverts the current to ground.

7.3.2 IO Capacitance

The capacitance between each I/O pin to ground is 1.5 pF. These capacitances support data rates in excess of 1.5 Gbps.

7.3.3 DC Breakdown Voltage

The DC breakdown voltage of each I/O pin is a minimum of 6.5 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of 5.5 V.

7.3.4 Ultra-Low Leakage Current

The I/O pins feature an ultra-low leakage current of 10 nA (Max) with a bias of 2.5 V.

7.3.5 Low ESD Clamping Voltage

The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.7 V (IPP = 1 A).

www.ti.com SLLSEG9C –JUNE 2013–REVISED DECEMBER 2019 Product Folder Links: TPD2E2U06 Submit Documentation FeedbackCopyright © 2013–2019, Texas Instruments Incorporated Feature Description (continued)

7.3.6 Industrial Temperature Range

This device is designed to operate from –40°C to 125°C.

7.3.7 Small Easy-to-Route Package

The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout.

7.4 Device Functional Modes

TPD2E2U06 is a passive integrated circuit that triggers when voltages are above VBR or below the lower diodes Vf (–0.6 V). During ESD events, voltages as high as ±30 kV (air) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below the trigger levels of TPD2E2U06 (usually within 10’s of nano-seconds) the device reverts to passive.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.

8.2 Typical Application

Figure 10. Typical USB Application Diagram

8.2.1 Design Requirements

Given the USB 2.0 application, the following parameters are known.

8.2.2 Detailed Design Procedure

• Signal range of all the protected lines
• Operating frequency

8.2.2.1 Signal Range

8.2.2.2 Operating Frequency

The TPD2E2U06 has a capacitance of 1.5 pF (Typ), supporting USB 2.0 data rates.

8.2.3 Application Curves

Figure 11. Insertion Loss Graph

9 Power Supply Recommendations

sure that the maximum voltage specifications for each line are not violated.

10 Layout

10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Example

Figure 12. Routing with DRL Package

11 Device and Documentation Support

11.1 Trademarks

E2E is a trademark of Texas Instruments. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners.

11.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPD2E2U06DCKR Active Production SC70 (DCK) | 3 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1GH TPD2E2U06DCKR.B Active Production SC70 (DCK) | 3 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1GH TPD2E2U06DCKRG4.B Active Production SC70 (DCK) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1GH TPD2E2U06DRLR Active Production SOT-5X3 (DRL) | 5 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 DT TPD2E2U06DRLR.B Active Production SOT-5X3 (DRL) | 5 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 DT TPD2E2U06DRLRG4.B Active Production SOT-5X3 (DRL) | 5 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 DT (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 23-May-2025 OTHER QUALIFIED VERSIONS OF TPD2E2U06 :

• Automotive : TPD2E2U06-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD2E2U06DCKR SC70 DCK 3 3000 210.0 185.0 35.0 TPD2E2U06DRLR SOT-5X3 DRL 5 4000 183.0 183.0 20.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 1.7 1.5 2X 0.5 2X 1 5X 0.3

0.10.6 MAX

5X 0.18 0.08 5X 0.4 0.2 0.05

0.00 TYP

5X 0.27 0.15 2X 0 -10 2X 4 -15 1.3 1.1 1.7 1.5 NOTE 3 SOT - 0.6 mm max heightDRL0005A PLASTIC SMALL OUTLINE 4220753/E 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-293 Variation UAAD-1 1 5 PIN 1 ID AREA 3 4 SEATING PLANE 0.05 C SCALE 8.000

0.1 C A B

0.05 C SYMM SYMM A B C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

5X (0.67) 5X (0.3) (1.48) 2X (0.5) (R0.05) TYP (1) 4220753/E 11/2024 SOT - 0.6 mm max heightDRL0005A PLASTIC SMALL OUTLINE NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:30X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDERMASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN (1.48) 2X (0.5) 5X (0.67) 5X (0.3) (R0.05) TYP (1) SOT - 0.6 mm max heightDRL0005A PLASTIC SMALL OUTLINE 4220753/E 11/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X SYMM SYMM 3 4

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.15 2.4 1.8 0.65

1.1 MAX

0.1

0.0 TYP

3X 0.30 0.15 0.46

0.26 TYP

0 TYP

1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 (0.9) SOT-SC70 - 1.1 max heightDCK0003A SMALL OUTLINE TRANSISTOR SC70 4220745/F 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

3X (0.95)3X (0.4) (2.2) (1.3) (0.65) (R0.05) TYP 4220745/F 11/2024 SOT-SC70 - 1.1 max heightDCK0003A SMALL OUTLINE TRANSISTOR SC70 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) (0.65) 3X (0.95)3X (0.4) (R0.05) TYP SOT-SC70 - 1.1 max heightDCK0003A SMALL OUTLINE TRANSISTOR SC70 4220745/F 11/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated