TPD2E1B06_V01 TI | Alldatasheet
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Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD2E1B06 SLVSC77D –AUGUST 2013– REVISED APRIL 2016 TPD2E1B06Dual-ChannelHigh-SpeedESDProtectionDevice
1 Features
1• Provides System Level ESD Protection for Low Voltage IO Interface
- IEC 61000-4-2 Level 4 ESD Rating
- Low IO Capacitance: 0.85 pF (Typical)
- DC Breakdown Voltage: 7 V (Minimum)
- Ultra-Low Leakage Current: 10 nA (Maximum)
- Low ESD Clamping Voltage
- Temperature Range: –40°C to 125°C
- Small Easy-to-Route DRL package
2 Applications
- Gaming Machines
- eBooks
- Portable Media Players
- Digital Cameras
3 Description
The TPD2E1B06 device is a dual-channel, ultra-low capacitance ESD protection device. It offers ±10-KV IEC contact ESD protection. Its 1-pF line capacitance makes it suitable for a wide range of applications. Typical application interfaces are USB 2.0, LVDS, and I2C. The TPD2E1B06 device has two common layout methods, and both are highlighted in Layout. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPD2E1B06 SOT (6) 1.60 mm × 1.20 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Schematic
SLVSC77D – AUGUST 2013– REVISED APRIL 2016 www.ti.com Product Folder Links: TPD2E1B06 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Table of Contents
12 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2013) to Revision D Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision B (September 2013) to Revision C Page Changes from Revision A (August 2013) to Revision B Page Changes from Original (July 2013) to Revision A Page
www.ti.com SLVSC77D – AUGUST 2013– REVISED APRIL 2016 Product Folder Links: TPD2E1B06 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
NAME NO. IOA1 1 I/O ESD protected channel See Application Information. IOA2 5 I/O IOB1 2 I/O IOB2 4 I/O NC 3, 6 NC No connect Can be left floating, grounded, or connected to VCC (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Using Routing Option 1 or 2 as shown in Figure 13 or Figure 14.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Operating temperature –40 125 °C IPP Peak pulse current (tp = 8/20 μs)(2) 2.5 A PPP Peak pulse power (tp = 8/20 μs)(2) 35 W Tstg Storage temperature –65 155 °C (1) Using Routing Option 1 or 2 as shown in Figure 13 or Figure 14.
6.2 ESD Ratings
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge(1) ±10000 V IEC 61000-4-2 air-gap discharge(1) ±15000
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIO Pin IOA1 to IOA2; Pin IOB1 to IOB2 –5.5 5.5 V TA Operating free-air temperature –40 125 °C (1) For more information about traditional and new thermal metrics, the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted) THERMAL METRIC(1) TPD2E1B06 UNITDRL (SOT)
6 PINS
RθJA Junction-to-ambient thermal resistance 349.7 ºC/W RθJC(top) Junction-to-case (top) thermal resistance 120.5 ºC/W RθθJB Junction-to-board thermal resistance 171.4 ºC/W ψJT Junction-to-top characterization parameter 10.8 ºC/W ψJB Junction-to-board characterization parameter 169.4 ºC/W (1) Transmission line pulse with rise time 10 ns and pulse width 100 ns. (2) TA = 25°C (3) Using Routing Option 1, Figure 13. (4) Using Routing Option 2, Figure 14.
6.5 Electrical Characteristics
over operating free-air temperature range. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRWM Reverse standoff voltage 5.5 V VCLAMP Clamp voltage with ESD strike IPP = 1 A, TLP, I/O to GND(1)(2) 11 V IPP = 5 A, TLP, I/O to GND(1)(2) 15 VCLAMP Clamp voltage with ESD strike IPP = 1 A, TLP, GND to I/O (1)(2) 11 V IPP = 5 A, TLP, GND to I/O (1)(2) 15 RDYN Dynamic resistance 0.9 Ω CL1 Pin 2 and 5 capacitance Pin 1 and 4 = GND, f = 1 MHz, VBIAS = 2.5 V(2)(3) 0.85 pF CL2 Pin 1 and 4 capacitance Pin 2 and 5 = GND, f = 1 MHz, VBIAS = 2.5 V(2)(4) 1.05 pF VBR Break-down voltage IIO = 1 mA 7 9.5 V ILEAK Leakage current VBIAS = +2.5 V 1 10 nA
6.6 Typical Characteristics
Figure 1. IV Curve Figure 2. Maximum Surge Rating Figure 3. ILEAK vs Temperature Figure 4. +8-kV Contact ESD Clamping Figure 5. –8-kV Contact ESD Clamping Figure 6. Insertion Loss
Copyright © 2016 Texas Instruments Incorporated TPD2E1B06 www.ti.com SLVSC77D – AUGUST 2013– REVISED APRIL 2016 Product Folder Links: TPD2E1B06 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TPD2E1B06 is a bidirectional, low-capacitance, two-channel ESD clamping device. It has more than IEC 61000-4-2 Level 4 ESD Rating. The low IO capacitance makes the device a good fit for a wide range of data speeds. Common applications include USB 2.0, LVDS, and I2C.
7.2 Functional Block Diagram
7.3 Feature Description
The TPD2E1B06 device provides robust system level IEC protection. This device protects circuit from ESD strikes up to ±10-kV contact and ±15-kV air-gap specified in the IEC 61000-4-2 level 4. It also handles up to 2.5-A surge current (IEC61000-4-5 8/20 µs). The I/O capacitance of 0.85 pF supports high data rates. The device has a small dynamic resistance of 0.9 Ω, making clamping voltage low when the device is actively protecting other circuits. With low capacitance and dynamic resistance, the TPD2E1B06 is a good fit for interfaces like USB 2.0, LVDS, and I2C. The breakdown is bidirectional so that this protection device is especially good for bidirectional signals like audio lines. Low leakage allows the diode to conserve power when working below the VRWM. The temperature range of –40°C to 125°C makes this ESD device work at extensive temperatures in most environments.
7.4 Device Functional Modes
The TPD2E1B06 is a passive clamp that has low leakage during normal operation when the voltage across each channel is below VRWM and activates when the it goes above VBR. During IEC ESD events, transient voltages will be clamped. When the voltages on the protected lines fall below the trigger voltage, the device reverts back to the low-leakage passive state.
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
current from ESD passes through the device, only a small voltage drop is present across the diode structure. to a tolerable level to the protected IC.
8.2 Typical Application
Figure 10. Typical Application Schematic
8.2.1 Design Requirements
In this design example, a TPD2E1B06 is used to protect audio channels. Table 1 lists the system parameters. Table 1. Design Parameters
8.2.2 Detailed Design Procedure
- Voltage range on the protected line must not exceed the reverse standoff voltage of the TVS diode(s) (VRWM)
- Operating frequency is supported by the I/O capacitance CIO of the TVS diode
- IEC 61000-4-2 protection requirement is covered by the IEC performance of the TVS diode For this application, the audio signal voltage range is –3 V to 3 V. The VRWM for the TVS is –5.5 V to 5.5 V; therefore, the bidirectional TVS will not break down during normal operation. Next, consider the frequency content of this audio signal. In this application with the class AB amplifier, the frequency content is from 20 Hz to 20 kHz; ensure that the TVS I/O capacitance will not distort this signal by filtering it. With TPD2E1B06 typical capacitance of 0.85 pF, which leads to a typical 3-dB bandwidth of more than 3 GHz, this diode has way sufficient bandwidth to pass the audio signal without distorting it. Finally, the human interface in this application requires above standard Level 4 IEC 61000-4-2 system-level ESD protection (±8-kV Contact and ±15-kV Air-Gap). TPD2E1B06 can survive at least ±10-kV Contact and ±15-kV Air-Gap. Therefore, the device can provide sufficient ESD protection for the interface, even though the requirements are stringent. For any TVS diode to provide the full range of ESD protection capabilities, as well as to minimize the noise and EMI disturbances the board will see during ESD events, a system designer must use proper board layout of their TVS ESD protection diodes. See Layout for instructions on properly laying out the TPD2E1B06.
8.2.3 Application Curves
Figure 11. +8-kV Contact ESD Clamping Figure 12. –8-kV Contact ESD Clamping
9 Power Supply Recommendations
requirements. Take care not to violate the maximum voltage specifications for each pin.
10 Layout
10.1 Layout Guidelines
- The optimum placement of the TPD2E1B06 is as close to the connector as possible. EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. The printed-circuit board (PCB) designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces, which are between the TVS and the connector.
- Route the protected traces as straight as possible.
- Avoid sharp corners on the protected traces. Electric fields tend to build up on corners, increasing EMI coupling.
- Use thick and short traces for the ground pins
10.2 Layout Examples
Figure 13. Routing Option 1 Figure 14. Routing Option 2
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPD2E1B06DRLR Active Production SOT-5X3 (DRL) | 6 4000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (DUH, DUL) DUG TPD2E1B06DRLR.B Active Production SOT-5X3 (DRL) | 6 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (DUH, DUL) DUG TPD2E1B06DRLRG4 Active Production SOT-5X3 (DRL) | 6 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 DUL TPD2E1B06DRLRG4.B Active Production SOT-5X3 (DRL) | 6 4000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 DUL (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD2E1B06DRLR SOT-5X3 DRL 6 4000 210.0 185.0 35.0 TPD2E1B06DRLRG4 SOT-5X3 DRL 6 4000 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE 1.7 1.5 4X 0.5 2X 1 6X 0.3 0.1
0.6 MAX
6X 0.18 0.08 6X 0.4 0.2 0.05
0.00 TYP
6X 0.27 0.15 2X 0 -10 2X 4 -15 1.3 1.1 1.7 1.5 NOTE 3 SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE 4223266/F 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-293 Variation UAAD 1 6 PIN 1 ID AREA 3 4 SEATING PLANE 0.05 C SCALE 8.000
0.1 C A B
0.05 C SYMM SYMM A B C
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
6X (0.67) 6X (0.3) (1.48) 4X (0.5) (R0.05) TYP 4223266/F 11/2024 SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria. SYMM LAND PATTERN EXAMPLE SCALE:30X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDERMASK DETAILS
www.ti.com EXAMPLE STENCIL DESIGN (1.48) 4X (0.5) 6X (0.67) 6X (0.3) (R0.05) TYP SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE 4223266/F 11/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X SYMM SYMM 3 4
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