TPD2E009 TI | Alldatasheet
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D+D– Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design TPD2E009 SLVS953B –JUNE 2009– REVISED AUGUST 2015 TPD2E0092-ChannelESDSolutionforHigh-Speed(6-Gbps)DifferentialInterface
1 Features 3 Description
The TPD2E009 device provides two ESD protection 1• Supports Data Rates up to 6 Gbps diodes with flow-through pin mapping for ease of• IEC 61000-4-2 ESD Protection board layout. This device has been designed to – ±8-kV Contact Discharge protect sensitive components which are connected to ultra high-speed data and transmission lines. The– ±8-kV Air-Gap Discharge TPD2E009 offers transient voltage suppression for• IEC 61000-4-5 Surge Protection Level 4 of IEC 61000-4-2 Contact ESD protection. – 5 A (8/20 µs) TVS protection up to a 5-A (8/20 μs) peak pulse- current rating per the IEC 61000-4-5 (lightning)• Low Capacitance specification is also provided.– DRT: 0.7-pF (Typ) The monolithic silicon technology allows matching– DBZ: 0.9-pF (Typ) between the differential signal pairs. The less than• 0.05-pF Matching Capacitance Between the 0.05-pF differential capacitance ensures that theDifferential Signal Pair differential signal distortion due to added ESD circuit
- Dual-Matching TVS Diodes to Protect the protection remains minimal. The low capacitance Differential Data and Clock Lines of HDMI, LVDS, (0.7-pF) is suitable for high-speed data rates up to SATA, Ethernet, or USB Interfaces 6 Gbps.
- Space-Saving DRT and DBZ Package Options The TPD2E009 TVS diode is offered in a DRT
- Flow-Through Pin Mapping for the High-Speed (1 mm × 0.8 mm) package for space-saving portable Lines Ensures Zero Additional Skew Due to Board applications. The industry standard DBZ (2.92 mm × Layout While Placing the ESD-Protection Chip 1.3 mm) package offers additional flexibility in the board layout for the system designer.Near the Connector Typical applications for the TPD2E009 line of ESD2 Applications protection products are: HDMI, USB, eSATA, and ethernet interfaces in notebooks, DVD and media• End Equipment: players, set-top boxes, and portable computers.– Notebooks – Set-Top Boxes Device Information(1) – Portable Computers PART NUMBER PACKAGE BODY SIZE (NOM) – DVD Players 2.92 mm × 1.30 mm TPD2E009 SOT (3) 1.00 mm × 0.80 mm– Media Players
- Interfaces: (1) For all available packages, see the orderable addendum at the end of the data sheet.– HDMI 2.0 – USB 3.0 – eSATA – Ethernet TPD2E009 Circuit An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLVS953B – JUNE 2009– REVISED AUGUST 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2009) to Revision B Page
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
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Product Folder Links: TPD2E009
2D– GND TPD2E009 www.ti.com SLVS953B – JUNE 2009– REVISED AUGUST 2015
5 Pin Configuration and Functions
DBZ, DRT Packages 3-Pin SOT TOP VIEW Pin Functions PIN TYPE DESCRIPTION NAME NO. D+ 1 ESD port High-speed ESD clamp provides ESD protection to the high-speed differential data lines D– 2 GND 3 GND Ground
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Operating temperature –40 85 °C I/O voltage tolerance 0 6 V Peak pulse current (tp = 8/20 μs) D+, D– pins 5 A Peak pulse power (tp = 8/20 μs) 45 W Storage temperature, Tstg –65 125 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±15000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000ElectrostaticV(ESD) Vdischarge IEC 61000-4-2 contact discharge D+, D– pins ±8000 IEC 61000-4-2 air-gap discharge D+, D– pins ±8000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Operating free-air temperature, TA –40 85 °C Operating voltage Pin 1 or 2 to 3 or Pin 3 to 1 or 2 0 5.5 V Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPD2E009
SLVS953B – JUNE 2009– REVISED AUGUST 2015 www.ti.com
6.4 Thermal Information
THERMAL METRIC(1) DBZ (SOT) DRT (SOT) UNIT
3 PINS 3 PINS
RθJA Junction-to-ambient thermal resistance 461.8 610 °C/W RθJC(top) Junction-to-case (top) thermal resistance 216.2 288 °C/W RθJB Junction-to-board thermal resistance 195.6 118.4 °C/W ψJT Junction-to-top characterization parameter 70.1 20.2 °C/W ψJB Junction-to-board characterization parameter 193.7 116.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRWM Reverse stand-off voltage D+, D– pins to ground 5.5 V VCLAMP Clamp voltage D+, D– pins to ground, IIO = 1 A 8 V IIO Current from I/O port to supply pins VIO = 2.5 V 0.01 0.1 μA D+, D– pins, VIO = 2.5 V, ID = 8 mA 0.6 0.8 0.95lower clamp diode, VD Diode forward voltage VD+, D– pins, upper clamp diode, VCC = 0 V, ID = –8 mA 0.6 0.8 0.95 DRY package RDYN Dynamic resistance D+, D– pins, I = 1 A 1 Ω D+, D– pins, DBZ VIO = 2.5 V, f = 10 MHz 0.9 pFPackage CIO I/O capacitance D+, D– pins, DRT VIO = 2.5 V, f = 10 MHz 0.7 pFPackage VBR Break-down voltage IIO = 1 mA 7 V
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6.6 Typical Characteristics
Figure 1. I/O Capacitance vs I/O Voltage (TA= 25°C) Figure 2. Leakage Current vs Temperature (VIO = 2.5 V) Figure 4. D+, D– Transmission Line Pulser PlotFigure 3. Peak Pulse Waveforms, Figure 5. IEC Clamping Waveforms (8-kV Contact) Figure 6. IEC Clamping Waveforms (–8-kV Contact)
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7 Detailed Description
7.1 Overview
TPD2E009 is a two-channel ESD TVS that provides ±8-kV IEC 61000-4-2 contact and air-gap ESD protection. The 0.7-pF unidirectional diode architecture is suitable for signals that range from 0 V to 5.5 V and can support data rates up to 6 Gbps. The industry-standard packages are convenient for placement in applications with limited space.
7.2 Functional Block Diagram
7.3 Feature Description
TPD2E009 is a unidirectional TVS offering IEC 61000-4-2 Level 4 Contact ESD protection. This device protects circuits from ESD strikes up to ±8-kV contact and ±8-kV air-gap. The device can also handle up to 5-A surge current (IEC 61000-4-5 8/20 μs). The low capacitance of 0.7 pF supports a data rate up to 6 Gbps. TPD2E009 has a small dynamic resistance of 1 Ω, which makes the clamping voltage low when the device is actively protecting other circuits. For example, the clamping voltage is only 8 V when the device is taking a 1-A transient current. Low leakage allows the diode to conserve power when working below the VRWM.
7.4 Device Functional Modes
The TPD2E009 device is a passive clamp that has low leakage during normal operation when the voltage between an I/O pin and GND is below VRWM. The device activates when the voltage is between an I/O pin and GND goes above VBR. During ESD events, transient voltages as high as ±8 kV can be clamped between the protected line and ground. When the voltages on the protected lines fall below the trigger voltage, the device reverts back to the low-leakage passive state.
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application
- HDMI
- USB
- eSATA
- ethernet interfaces
Figure 7. TPD2E009 in a High-Speed Interface
8.2.1 Design Requirements
shown in the following table.
8.2.2 Detailed Design Procedure
- The signal voltage range on the protected lines
- The maximum operating frequency Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPD2E009
8.2.3 Application Curves
Figure 8. Eye Diagram With TPD2E009 Figure 9. Eye Diagram Without TPD2E009 Figure 11. Eye Diagram Without TPD2E009Figure 10. Eye Diagram With TPD2E009 Figure 13. Eye Diagram Without TPD2E009Figure 12. Eye Diagram With TPD2E009
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9 Power Supply Recommendations
must be taken to avoid violating the maximum-voltage specification to ensure that the device functions properly. The D+ and D– lines share a TVS diode that can tolerate up to 5.5 V.
10 Layout
10.1 Layout Guidelines
stubs in the board traces, which creates significant disruption in the line impedance in the high-speed signal path. the signals. TI recommends coupling the differential traces closely to reduce the EMI interference. rate). The flow-through package offers flexibility for board routing with traces up to 15 mils (0.38 mm) wide.
10.2 Layout Examples
Figure 14. TPD2E009DRTR at eSATA Connector Interface
Figure 15. TPD2E009DBZR at eSATA Connector Interface
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www.ti.com SLVS953B – JUNE 2009– REVISED AUGUST 2015
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPD2E009
www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPD2E009DBZR Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (NFLO, NFLR) TPD2E009DBZR.B Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 (NFLO, NFLR) TPD2E009DBZRG4 Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 NFLR TPD2E009DBZRG4.B Active Production SOT-23 (DBZ) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 NFLR TPD2E009DRTR Active Production SOT-9X3 (DRT) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 4T TPD2E009DRTR.B Active Production SOT-9X3 (DRT) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 4T TPD2E009DRTRG4 Active Production SOT-9X3 (DRT) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 4T TPD2E009DRTRG4.B Active Production SOT-9X3 (DRT) | 3 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 4T (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1
www.ti.com 10-Nov-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD2E009DBZR SOT-23 DBZ 3 3000 183.0 183.0 20.0 TPD2E009DBZRG4 SOT-23 DBZ 3 3000 183.0 183.0 20.0 TPD2E009DRTR SOT-9X3 DRT 3 3000 202.0 201.0 85.0 TPD2E009DRTRG4 SOT-9X3 DRT 3 3000 202.0 201.0 85.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.20
0.08 TYP
0.25 2.64 2.10
1.12 MAX
0.10
0.01 TYP
3X 0.5 0.3 0.6
0.2 TYP
1.9 0.95 0 -8 TYP 4X 0 -15 4X 4 -15 A 3.04 2.80 B1.4 1.2 (0.95) (0.15) (0.125) SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/F 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length. 4. Support pin may differ or may not be present. 5. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
3X (1.3) 3X (0.6) (2.1) 2X (0.95) (R0.05) TYP 4214838/F 08/2024 SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:15X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS
www.ti.com EXAMPLE STENCIL DESIGN (2.1) 2X(0.95) 3X (1.3) 3X (0.6) (R0.05) TYP SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/F 08/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM PKG
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