TPD2E007 TI | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD2E007 SLVS796I –SEPTEMBER 2008–REVISED MARCH 2016 TPD2E0072-ChannelESDProtectionArrayforAC-Coupled/Negative-RailDataInterfaces
1 Features
1• IEC 61000-4-2 Level 4 ESD Protection – ±8-kV IEC 61000-4-2 Contact Discharge – ±15-kV IEC 61000-4-2 Air-Gap Discharge
- IEC 61000-4-5 Surge Protection – 4.5-A Peak Pulse Current (8/20-µs Pulse)
- IO Capacitance 15 pF (Max)
- Low 50-nA Leakage Current
- Space-Saving PicoStar™ and SOT Package
2 Applications
- Cell Phones
- Audio Interface Connections
- Consumer Electronics (DVR, Set-Top Box, TV)
- Industrial Interfaces (RS-232, RS-485, RS-422, LVDS)
3 Description
This device is a transient voltage suppressor (TVS) based electrostatic discharge (ESD) protection device designed to offer system level ESD solutions for wide range of portable and industrial applications. The back-to-back diode array allows AC-coupled or negative-going data transmission (audio interface, LVDS, RS-485, RS-232, and so forth) without compromising signal integrity. This device exceeds the IEC 61000-4-2 (Level 4) ESD protection and is ideal for providing system level ESD protection for the internal ICs when placed near the connector. The TPD2E007 is offered in a 4-bump PicoStar and 3-pin SOT (DGK) packages. The PicoStar package (YFM), with only 0.15 mm (Max) package height, is recommended for ultra space saving application where the package height is a key concern. The PicoStar package can be used in either embedded PCB board applications or in surface mount applications. The industry standard SOT package offers straightforward board layout option in legacy designs. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPD2E007 SOT (3) 2.00 mm x 1.25 mm PicoStar (4) 0.77 mm x 0.77 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Example Schematic Equivalent Schematic Representation
SLVS796I –SEPTEMBER 2008–REVISED MARCH 2016 www.ti.com Product Folder Links: TPD2E007 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Table of Contents
12 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (January 2016) to Revision I Page Changes from Revision G (December 2015) to Revision H Page Changes from Revision F (August 2014) to Revision G Page
- Updated the Handling Ratings table to an ESD Ratings table and moved Tstg to the Absolute Maximum Ratings Changes from Revision E (August 2010) to Revision F Page
- Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information Changes from Revision D (October 2009) to Revision E Page
3 GND
www.ti.com SLVS796I –SEPTEMBER 2008–REVISED MARCH 2016 Product Folder Links: TPD2E007 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
0.8 mm × 0.8 mm (0.4 mm pitch) Pin Functions PIN I/O DESCRIPTION NAME DCK NO. YFM NO. GND 3 B1, B2 G Ground IO1 1 A1 IO ESD protected channel IO2 2 A2 IO ESD protected channel
SLVS796I –SEPTEMBER 2008–REVISED MARCH 2016 www.ti.com Product Folder Links: TPD2E007 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VIO –13.5 13.5 V Continuous power dissipation (TA = 70°C) YFM package 270 mW DCK package 218 Operating temperature –40 85 °C TJ Junction temperature 150 °C Bump temperature (soldering) Infrared (15 s) 220 Vapor phase (60 s) 215 Lead temperature (soldering, 10 s) 300 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±15000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500
6.3 ESD Ratings: Surge Protection
V(ESD) Electrostatic discharge IEC 61000-4-2 ESD ratings Contact ±8000 V Air gap ±15000
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIO Operating voltage –13 13 V Operating temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Thermal Information
THERMAL METRIC(1) TPD2E007 UNITDCK (SOT) YFM (PicoStar)
3 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 251.9 175.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 115.4 39.2 °C/W RθJB Junction-to-board thermal resistance 42.4 28.7 °C/W ψJT Junction-to-top characterization parameter 9.4 8.3 °C/W ψJB Junction-to-board characterization parameter 42.2 28.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) Typical values are at VCC = 5 V and TA = 25°C.
6.6 Electrical Characteristics
6.7 Typical Characteristics
Figure 1. 8-kV Contact Figure 2. –8-kV Contact Figure 3. Capacitance vs Input Voltage at TA = 27°C Figure 4. Diode Breakdown Voltage Data at TA = 27°C
7 Detailed Description
7.1 Overview
level ESD protection for the internal ICs when placed near the connector.
7.2 Functional Block Diagram
Figure 5. Equivalent Schematic Representation
7.3 Feature Description
level ESD protection for the internal ICs when placed near the connector.
7.3.1 IEC 61000-4-2 Level 4 ESD Protection
7.3.2 IEC 61000-4-5 Surge Protection
7.3.3 IO Capacitance
The capacitance between each I/O pin to ground is 15 pF.
7.3.4 Low 50-nA Leakage Current
The I/O pins feature a low 50-nA (max) leakage current.
7.3.5 Space-Saving PicoStar and SOT Package
This device is offered in both a space-saving PicoStar package, as well as a standard DCK package.
7.4 Device Functional Modes
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
8.2 Typical Application
Figure 6. Example Schematic
8.2.1 Design Requirements
For this design example, a single TPD2E007 is used to protect an RS232 3-wire connector. Given the application, the following parameters are known. Table 1. Design Parameters
8.2.2 Detailed Design Procedure
- Signal voltage range on all protected lines
- Surge Withstand
8.2.2.1 Signal Range on IO1 and IO2 Pins
The TPD2E007 has 2 IO pins which can support up to ±13 V.
8.2.2.2 Surge Withstand
The TPD2E007 can withstand up to 170W of IEC 61000-4-5 8/20-µs surge.
8.2.3 Application Curve
Figure 7. Surge Pulse Waveform
9 Power Supply Recommendations
I/O specification (±13 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
- The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
- Route the protected traces as straight as possible.
- Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
Figure 8. Layout Recommendation
www.ti.com SLVS796I –SEPTEMBER 2008–REVISED MARCH 2016 Product Folder Links: TPD2E007 Submit Documentation FeedbackCopyright © 2008–2016, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.2 Trademarks
PicoStar, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPD2E007DCKR Active Production SC70 (DCK) | 3 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 45U TPD2E007DCKR.A Active Production SC70 (DCK) | 3 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 45U TPD2E007DCKR.B Active Production SC70 (DCK) | 3 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 45U TPD2E007YFMTG4 Obsolete Production DSLGA (YFM) | 4 - - Call TI Call TI -40 to 85 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 20-Apr-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 20-Apr-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD2E007DCKR SC70 DCK 3 3000 213.0 191.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.15 2.4 1.8 0.65
1.1 MAX
0.1
0.0 TYP
3X 0.30 0.15 0.46
0.26 TYP
0 TYP
1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 (0.9) SOT-SC70 - 1.1 max heightDCK0003A SMALL OUTLINE TRANSISTOR SC70 4220745/F 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side
0.1 C A B
0.1 C SCALE 5.600
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
3X (0.95)3X (0.4) (2.2) (1.3) (0.65) (R0.05) TYP 4220745/F 11/2024 SOT-SC70 - 1.1 max heightDCK0003A SMALL OUTLINE TRANSISTOR SC70 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) (0.65) 3X (0.95)3X (0.4) (R0.05) TYP SOT-SC70 - 1.1 max heightDCK0003A SMALL OUTLINE TRANSISTOR SC70 4220745/F 11/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG
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