TPD2E001DRLR

TPD2E001 TI | Alldatasheet

Document overview

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Technical content

0.1 µF USB Controller RT RT VBUS GND GND IO2 IO1 VCC Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD2E001 SLLS684I –JULY 2006–REVISED MARCH 2016 TPD2E001Low-Capacitance2-ChannelESD-ProtectionforHigh-SpeedDataInterfaces

1 Features

1• IEC 61000-4-2 ESD Protection (Level 4) – ±8-kV Contact Discharge – ±15-kV Air-Gap Discharge

• IO Capacitance: 1.5 pF (Typ)
• Low Leakage Current: 1 nA (Maximum)
• Low Supply Current: 1 nA
• 0.9 V to 5.5 V Supply-Voltage Range
• Space-Saving DRL, DRY, and QFN Package Options
• Alternate 3, 4, 6-Channel options Available: TPD3E001, TPD4E001, TPD6E001

2 Applications

• USB 2.0
• Ethernet
• FireWire™
• LVDS
• SVGA Video Connections
• Glucose Meters
• Medical Imaging

3 Description

The TPD2E001 is a two-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array. The TPD2E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 Level 4 international standard. The DRS package (3.00 mm x 3.00 mm) is also available as a non-magnetic package for medical imaging applications. See also TPD2E2U06DRLR which is p2p compatible to TPD2E001DRLR and offers higher IEC ESD Protection, lower clamping voltage, and eliminates the input capacitor requirement. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPD2E001 SOT (5) 1.60 mm x 1.20 mm WSON (6) 3.00 mm x 3.00 mm USON (6) 1.45 mm x 1.00 mm SOP (4) 2.90 mm x 1.30 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Schematic

SLLS684I –JULY 2006–REVISED MARCH 2016 www.ti.com Product Folder Links: TPD2E001 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Table of Contents

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (August 2014) to Revision I Page

• Updated the Handling Ratings table to an ESD Ratings table and moved the Tstg to the Absolute Maximum Ratings Changes from Revision G (November 2013) to Revision H Page
• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information Changes from Revision F (Feburary 2012) to Revision G Page Changes from Revision E (June 2008) to Revision F Page
• Added "The 3x3 mm DRS package is also available as a non-magnetic package for medical imaging application." to

N.C. IO1 IO2 3 4 GND VCC N.C. IO1 IO2 N.C. GND4 IO1 N.C. N.C. IO2 GND VCC TPD2E001 www.ti.com SLLS684I –JULY 2006–REVISED MARCH 2016 Product Folder Links: TPD2E001 Submit Documentation FeedbackCopyright © 2006–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

N.C. – Not internally connected 5-Pin SOT Top View N.C. – Not internally connected 6-Pin WSON Top View N.C. – Not internally connected 4-Pin SOP Top View Pin Functions PIN

DESCRIPTION

NO. DRL NO. DRS NO. DZD NO. EP — — EP — Exposed pad. Connect to GND. GND 4 4 4 1 Ground IOx 3, 6 3, 5 3, 6 2, 3 ESD-protected channel N.C. 2, 5 2 2, 5 — No connection. Not internally connected. VCC 1 1 1 4 Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor.

SLLS684I –JULY 2006–REVISED MARCH 2016 www.ti.com Product Folder Links: TPD2E001 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Power pin voltage –0.3 7 V VIO IO pin voltage –0.3 VCC + 0.3 V TJ Junction temperature 150 °C Bump temperature (soldering) Infrared (15 s) 220 Vapor phase (60 s) 215 Lead temperature (soldering, 10 s) 300 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±15000 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000

6.3 ESD Ratings: Surge Protection

V(ESD) Electrostatic discharge IEC 61000-4-2 contact ±8000 V IEC 61000-4-2 air-gap discharge ±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT TA, operating free-air temperature –40 85 °C Operating voltage VCC pin 0.9 5.5 V IO1, IO2 pins 0 VCC (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Thermal Information

THERMAL METRIC(1) TPD2E001 UNITDRY (USON) DRL (SOT) DRS (WSON) DZD (SOP)

5 PINS 5 PINS 6 PINS 4 PINS

RθJA Junction-to-ambient thermal resistance 374.2 257.6 91.9 213.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 223.4 97.6 106.9 93.5 °C/W RθJB Junction-to-board thermal resistance 227.8 74.2 64.8 56.8 °C/W ψJT Junction-to-top characterization parameter 52.9 7.5 10.2 4.2 °C/W ψJB Junction-to-board characterization parameter 224.8 73.7 64.9 56.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 87.5 N/A 29.9 N/A °C/W

(2) Channel clamp voltage is not production tested.

6.6 Electrical Characteristics

6.7 Typical Characteristics

Figure 1. IO Capacitance vs IO Voltage (VCC = 5 V) Figure 2. IO Leakage Current vs Temperature (VCC = 5 V) Figure 3. TLP IO to GND (DRS Package) Figure 4. TLP GND to IO (DRS Package)

SLLS684I –JULY 2006–REVISED MARCH 2016 www.ti.com Product Folder Links: TPD2E001 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPD2E001 is a two-channel transient voltage suppressor (TVS) based ESD protection diode array. The TPD2E001 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 Level 4 international standard.

7.2 Functional Block Diagram

7.3 Feature Description

TPD2E001 is a uni-directional ESD protection device with low capacitance. The device is constructed with a central ESD clamp that features two hiding diodes per line to reduce the capacitive loading. This central ESD clamp is also connected to VCC to provide protection for the VCC line. Each IO line is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 level 4 international standard. The TPD2E001's low loading capacitance makes it ideal for protection high-speed signal terminals.

7.4 Device Functional Modes

TPD2E001 is a passive integrated circuit that activates whenever voltages above VBR or below the lower diodes Vforward (–0.6V) are present upon the circuit being protected. During ESD events, voltages as high as ±15 kV can be directed to ground and VCC via the internal diode network. Once the voltages on the protected lines fall below the trigger voltage of the TPD2E001 (usually within 10s of nanoseconds) the device reverts back to a high impedance state.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. tolerable level to the protected IC.

8.2 Typical Application

Figure 5. Typical USB Application Diagram

8.2.1 Design Requirements

For this design example, a single TPD2E001 is used to protect all pins of a USB 2.0 connector. Table 1. Design Parameters

8.2.2 Detailed Design Procedure

• Signal voltage range on all the protected lines
• Operating frequency The VCC pin can be connected in two different ways: 1. If the VCC pin is connected to the system power supply, the TPD2E001 works as a transient suppressor for any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD

1. If the VCC pin is not connected to the system power supply, the TPD2E001 can tolerate higher signal swing

8.2.2.1 Signal Range on IO1 and IO2 and VCC Pins

connected to a VCC line or has a 0.1 µF capacitor to ground).

9 Power Supply Recommendations

sure that the maximum voltage specifications for each line are not violated.

10 Layout

10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Example

This application is typical of a differential data pair application, such a USB 2.0. Figure 6. Routing With DRL Package

www.ti.com SLLS684I –JULY 2006–REVISED MARCH 2016 Product Folder Links: TPD2E001 Submit Documentation FeedbackCopyright © 2006–2016, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.2 Trademarks

E2E is a trademark of Texas Instruments. FireWire is a trademark of Apple Computer, Inc. All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.4 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPD2E001DRLR Active Production SOT-5X3 (DRL) | 5 4000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2AR, 2AZ) (2AH, 2AW) TPD2E001DRLR.B Active Production SOT-5X3 (DRL) | 5 4000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2AR, 2AZ) (2AH, 2AW) TPD2E001DRLRG4 Active Production SOT-5X3 (DRL) | 5 4000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2AR, 2AZ) (2AH, 2AW) TPD2E001DRSR Active Production SON (DRS) | 6 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWK TPD2E001DRSR.B Active Production SON (DRS) | 6 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWK TPD2E001DRSRG4 Active Production SON (DRS) | 6 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWK TPD2E001DRSRG4.B Active Production SON (DRS) | 6 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWK TPD2E001DRST-NM Active Production SON (DRS) | 6 250 | SMALL T&R Yes SN Level-2-260C-1 YEAR -40 to 85 ZWKNM TPD2E001DRST-NM.B Active Production SON (DRS) | 6 250 | SMALL T&R Yes SN Level-2-260C-1 YEAR -40 to 85 ZWKNM TPD2E001DRYR Active Production SON (DRY) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2A TPD2E001DRYR.B Active Production SON (DRY) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2A TPD2E001DRYRG4 Active Production SON (DRY) | 6 5000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2A TPD2E001DZDR Active Production SOT-23 (DZD) | 4 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 NFGO TPD2E001DZDR.B Active Production SOT-23 (DZD) | 4 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 NFGO TPD2E001DZDRG4 Active Production SOT-23 (DZD) | 4 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 NFGO TPD2E001DZDRG4.B Active Production SOT-23 (DZD) | 4 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 NFGO (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 10-Nov-2025 (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPD2E001 :

• Automotive : TPD2E001-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD2E001DRLR SOT-5X3 DRL 5 4000 183.0 183.0 20.0 TPD2E001DRSR SON DRS 6 1000 353.0 353.0 32.0 TPD2E001DRSRG4 SON DRS 6 1000 353.0 353.0 32.0 TPD2E001DRST-NM SON DRS 6 250 213.0 191.0 35.0 TPD2E001DRYR SON DRY 6 5000 189.0 185.0 36.0 TPD2E001DZDR SOT-23 DZD 4 3000 200.0 183.0 25.0 TPD2E001DZDRG4 SOT-23 DZD 4 3000 200.0 183.0 25.0 Pack Materials-Page 2

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4207181/G

www.ti.com PACKAGE OUTLINE C 6X 0.25 0.15 0.5 5X 0.35 0.25

0.6 MAX

0.05 0.00 3X 0.6 0.4 0.3 B 1.05 0.95 A 1.5 1.4 (0.05) TYP (0.127) TYP 4222894/A 01/2018 USON - 0.6 mm max heightDRY0006A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.08 C 3 4 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 C SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 8.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

0.05 MAX

5X (0.3) 6X (0.2) 4X (0.5) (0.6) (R0.05) TYP (0.35) 4222894/A 01/2018 USON - 0.6 mm max heightDRY0006A PLASTIC SMALL OUTLINE - NO LEAD SYMM 3 4 SYMM LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X NOTES: (continued) METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 5X (0.3) 6X (0.2) 4X (0.5) (0.6)(R0.05) TYP (0.35) 4222894/A 01/2018 USON - 0.6 mm max heightDRY0006A PLASTIC SMALL OUTLINE - NO LEAD NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X SYMM 3 4 SYMM

www.ti.com PACKAGE OUTLINE 1.7 1.5 2X 0.5 2X 1 5X 0.3

0.10.6 MAX

5X 0.18 0.08 5X 0.4 0.2 0.05

0.00 TYP

5X 0.27 0.15 2X 0 -10 2X 4 -15 1.3 1.1 1.7 1.5 NOTE 3 SOT - 0.6 mm max heightDRL0005A PLASTIC SMALL OUTLINE 4220753/E 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-293 Variation UAAD-1 1 5 PIN 1 ID AREA 3 4 SEATING PLANE 0.05 C SCALE 8.000 0.05 C SYMM SYMM A B C

www.ti.com EXAMPLE BOARD LAYOUT 5X (0.67) 5X (0.3) (1.48) 2X (0.5) (R0.05) TYP (1) 4220753/E 11/2024 SOT - 0.6 mm max heightDRL0005A PLASTIC SMALL OUTLINE NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:30X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDERMASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN (1.48) 2X (0.5) 5X (0.67) 5X (0.3) (R0.05) TYP (1) SOT - 0.6 mm max heightDRL0005A PLASTIC SMALL OUTLINE 4220753/E 11/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X SYMM SYMM 3 4

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