TPD1E01B04 TI | Alldatasheet
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TPD1E01B04 (x4) TPD1E01B04 (x4) Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD1E01B04 SLVSDG3C –MARCH 2016–REVISED DECEMBER 2016 TPD1E01B041-ChannelESDProtectionDiodeforUSBType-CandThunderbolt3
1 Features
1• IEC 61000-4-2 Level 4 ESD Protection – ±15-kV Contact Discharge – ±17-kV Air Gap Discharge
- IEC 61000-4-4 EFT Protection – 80 A (5/50 ns)
- IEC 61000-4-5 Surge Protection – 2.5 A (8/20 µs)
- IO Capacitance: – 0.18 to 0.20 pF (Typical) – 0.20 to 0.23 pF (Maximum)
- DC Breakdown Voltage: 6.4 V (Typical)
- Ultra Low Leakage Current: 10-nA (Maximum)
- Low ESD Clamping Voltage: 15 V at 16 A TLP
- Low Insertion Loss: 26.9 GHz (–3 dB Bandwidth, DPL)
- Supports High Speed Interfaces up to 20 Gbps
- Industrial Temperature Range: –40°C to +125°C
- Industry Standard 0201 and 0402 footprints
2 Applications
- End Equipment – Laptops and Desktops – Mobile and Tablets – Set-Top Boxes – TV and Monitors – USB Dongles – Docking Stations
- Interfaces – USB Type-C – Thunderbolt 3 – USB 3.1 Gen 2 – HDMI 2.0/1.4 – USB 3.0 – DisplayPort 1.3 – PCI Express 3
3 Description
The TPD1E01B04 is a bidirectional TVS ESD protection diode array for USB Type-C and Thunderbolt 3 circuit protection. The TPD1E01B04 is rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4). This device features a 0.18 to 0.20-pF (typical) IO capacitance making it ideal for protecting high-speed interfaces up to 20 Gbps such as USB 3.1 Gen2 and Thunderbolt 3. The low dynamic resistance and low clamping voltage ensure system level protection against transient events. The TPD1E01B04 is offered in the industry standard 0201 (DPL) package and 0402 (DPY) packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPD1E01B04 X2SON (2) 0.60 mm x 0.30 mm X1SON (2) 1.00 mm x 0.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application
SLVSDG3C –MARCH 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: TPD1E01B04 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Table of Contents
12 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (May 2016) to Revision C Page Changes from Revision A (March 2016) to Revision B Page Changes from Original (March 2016) to Revision A Page
www.ti.com SLVSDG3C –MARCH 2016–REVISED DECEMBER 2016 Product Folder Links: TPD1E01B04 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
NO. NAME 1 IO I/O ESD Protected Channel. If used as ESD IO, connect pin 2 to ground 2 IO I/O ESD Protected Channel. If used as ESD IO, connect pin 1 to ground
SLVSDG3C –MARCH 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: TPD1E01B04 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Electrical fast transient IEC 61000-4-5 (5/50 ns) 80 A Peak pulse IEC 61000-4-5 power (tp - 8/20 µs) 27 W IEC 61000-4-5 current (tp - 8/20 µs) 2.5 A TA Operating free-air temperature –40 125 °C Tstg Storage temperature –65 155 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000
6.3 ESD Ratings— IEC Specification
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±15000 V IEC 61000-4-2 air-gap discharge ±17000
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIO Input pin voltage –3.6 3.6 V TA Operating free-air temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Thermal Information
THERMAL METRIC(1) TPD1E01B04 UNITDPL (X2SON) DPY (X1SON)
2 PINS 2 PINS
RθJA Junction-to-ambient thermal resistance 582 442.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 264.5 243.8 °C/W RθJB Junction-to-board thermal resistance 394.4 162.5 °C/W ψJT Junction-to-top characterization parameter 36.4 154.1 °C/W ψJB Junction-to-board characterization parameter 394.4 163.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
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6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO < 10 nA –3.6 3.6 V VBRF Breakdown voltage, IO pin to GND Measured as the maximum voltage before device snaps back into VHOLD voltage 6.4 V VBRR Breakdown voltage, GND to IO pin –6.4 V VHOLD Holding voltage IIO = 1 mA, TA = 25°C 5 5.9 6.5 V VCLAMP Clamping voltage IPP = 1 A, TLP, from IO to GND 7 V IPP = 5 A, TLP, from IO to GND 9.2 IPP = 16 A, TLP, from IO to GND 15 IPP = 1 A, TLP, from GND to IO 7 IPP = 5 A, TLP, from GND to IO 9.2 IPP = 16 A, TLP, from GND to IO 15 ILEAK Leakage current, IO to GND VIO = ±2.5 V 10 nA RDYN Dynamic resistance IO to GND 0.57 Ω GND to IO 0.57 CL Line capacitance TA = 25°C 0.18 0.20 pF
6.7 Typical Characteristics
Figure 1. Positive TLP Curve Figure 2. Negative TLP Curve Figure 3. 8-kV IEC Waveform Figure 4. –8-kV IEC Waveform Figure 5. Surge Curve (tp = 8/20µs), IO pin to GND Figure 6. Capacitance vs. Bias Voltage (DPL Package)
Copyright © 2016, Texas Instruments Incorporated TPD1E01B04 www.ti.com SLVSDG3C –MARCH 2016–REVISED DECEMBER 2016 Product Folder Links: TPD1E01B04 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TPD1E01B04 device is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra- low capacitance makes this device ideal for protecting any super high-speed signal pins including Thunderbolt 3. The low capacitance allows for extremely low losses even at RF frequencies such as USB 3.1 Gen 2, Thunderbolt 3, or antenna applications.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±15-kV contact and ±17-kV air gap. An ESD-surge clamp diverts the current to ground.
7.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω impedance). An ESD-surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2.5 A and 27 W (8/20 µs waveform). An ESD-surge clamp diverts this current to ground.
7.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 0.18 pF (typical) and 0.20 pF (maximum). This device supports data rates up to 20 Gbps.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is ±6.4 V (typical). This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of ±3.6 V.
7.3.6 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.2 V (IPP = 5 A).
7.3.8 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 20 Gbps, because of the extremely low IO capacitance.
7.3.9 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
SLVSDG3C –MARCH 2016–REVISED DECEMBER 2016 www.ti.com Product Folder Links: TPD1E01B04 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Feature Description (continued)
7.3.10 Easy Flow-Through Routing Package
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPD1E01B04 device is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During ESD events, voltages as high as ±17 kV (air) can be directed to ground via the internal diode network. When the voltages on the protected line fall below the trigger levels of TPD1E01B04 (usually within 10s of nano-seconds) the device reverts to passive.
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
Figure 14. USB Type-C for Thunderbolt 3 ESD Schematic
8.2.1 Design Requirements
USB Type-C for Thunderbolt 3 application. This provides a complete ESD protection scheme. Given the Thunderbolt 3 application, the parameters listed in Table 1 are known. Table 1. Design Parameters
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
the CC, SBU, and DP-DM lines.
8.2.2.2 Operating Frequency
8.2.3 Application Curves
Figure 15. USB 3.1 Gen 2 10-Gbps Eye Diagram Figure 16. USB 3.1 Gen 2 10-Gbps Eye Diagram Figure 17. Insertion Loss
9 Power Supply Recommendations
I/O specification to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
- The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
- Route the protected traces as straight as possible.
- Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
Figure 18. USB Type-C Mid-Mount, Hybrid Connector ESD Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following: TPD1E01B04 Evaluation Module User's Guide, SLVUAN5
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPD1E01B04DPLR Active Production X2SON (DPL) | 2 15000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 7 TPD1E01B04DPLR.B Active Production X2SON (DPL) | 2 15000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 7 TPD1E01B04DPLT Active Production X2SON (DPL) | 2 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 7 TPD1E01B04DPLT.B Active Production X2SON (DPL) | 2 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 7 TPD1E01B04DPLTG4 Active Production X2SON (DPL) | 2 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 7 TPD1E01B04DPLTG4.B Active Production X2SON (DPL) | 2 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 7 TPD1E01B04DPYR Active Production X1SON (DPY) | 2 10000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 5C TPD1E01B04DPYR.B Active Production X1SON (DPY) | 2 10000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5C TPD1E01B04DPYT Active Production X1SON (DPY) | 2 250 | SMALL T&R Yes NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 5C TPD1E01B04DPYT.B Active Production X1SON (DPY) | 2 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5C TPD1E01B04DPYTG4 Active Production X1SON (DPY) | 2 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5C TPD1E01B04DPYTG4.B Active Production X1SON (DPY) | 2 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5C (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1
www.ti.com 10-Nov-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPD1E01B04 :
- Automotive : TPD1E01B04-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD1E01B04DPLR X2SON DPL 2 15000 205.0 200.0 33.0 TPD1E01B04DPLT X2SON DPL 2 250 205.0 200.0 33.0 TPD1E01B04DPLTG4 X2SON DPL 2 250 205.0 200.0 33.0 TPD1E01B04DPYR X1SON DPY 2 10000 210.0 185.0 35.0 TPD1E01B04DPYT X1SON DPY 2 250 210.0 185.0 35.0 TPD1E01B04DPYTG4 X1SON DPY 2 250 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. X1SON - 0.45 mm max heightDPY 2 PLASTIC SMALL OUTLINE - NO LEAD1 x 0.6 mm 4231484/A
www.ti.com PACKAGE OUTLINE C 0.45 0.30 0.05 0.00 0.65
0.1 C A B
2X 0.55 0.45 2X 0.3 0.2 A 1.1 0.9 B 0.7 0.5 4224561/C 07/2024 X1SON - 0.45 mm max heightDPY0002A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.08 C 1 2
0.05 C A B
(45 X 0.1) NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M 2. This drawing is subject to change without notice. SCALE 11.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND0.07 MAX ALL AROUND (R0.05) TYP (0.7) 2X (0.5) 2X (0.3) 4224561/C 07/2024 X1SON - 0.45 mm max heightDPY0002A PLASTIC SMALL OUTLINE - NO LEAD SYMM 1 2 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:60X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED (PREFERRED)
www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP (0.7) 2X (0.5) 2X (0.3) (0) 4224561/C 07/2024 X1SON - 0.45 mm max heightDPY0002A PLASTIC SMALL OUTLINE - NO LEAD NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:60X SYMM 1 2 SYMM PCB PAD METAL UNDER SOLDER PASTE
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