TPD12S521_08 TI | Alldatasheet
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Technical content
FEATURES
5V_SUPPLY LV_SUPPLY GND TMDS_D2+ TMDS_GND TMDS_D2± TMDS_D1+ TMDS_GND TMDS_D1± TMDS_D0+ TMDS_GND TMDS_D0± TMDS_CK+ TMDS_GND TMDS_CK± CE_REMOTE_IN DDC_CLK_IN DDC_DAT_IN HOTPLUG_DET_IN 5V_OUT ESD_BYP GND TMDS_D2+ TMDS_GND TMDS_D2± TMDS_D1+ TMDS_GND TMDS_D1± TMDS_D0+ TMDS_GND TMDS_D0± TMDS_CK+ TMDS_GND TMDS_CK± CE_REMOTE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT DBT P ACKAGE (TOP VIEW)
APPLICATIONS
www.ti.com SLVS639A OCTOBER 2007 REVISED NOVEMBER 2008 SINGLE-CHIP HDMI TRANSMITTER PORT PROTECTION AND INTERFACE DEVICE Single-Chip ESD Solution for High-Definition Multimedia Interface (HDMI) Driver Supports HDMI 1.3 Data Rate dB Frequency GHz) 0.8-pF Capacitance for High-Speed Transition Minimized Differential Signaling (TMDS) Lines 0.05-pF Matching Capacitance Between the Differential Signal Pair Integrated Level Shifting for the Control Lines 8-kV Contact ESD Protection on External Lines 38-Pin Thin Shrink Small-Outline Package (TSSOP) Provides Seamless Layout Option With HDMI Connector Backdrive Protection Lead-Free Package On-Chip Current Regulator With 55-mA Current Output PCs Consumer Electronics Set-Top Boxes DVDRW Players The TPD12S521 is a single-chip ESD solution for the high-definition multimedia interface (HDMI) transmitter port. In many cases, the core ICs, such as the scalar chipset, may not have robust ESD cells to sustain system-level ESD strikes. In these cases, the TPD12S521 provides the desired system-level ESD protection, such as the the IEC61000-4-2 (Level ESD, by absorbing the energy associated with the ESD strike. While providing the ESD protection, the TPD12S521 adds little or no additional glitch in the high-speed differential signals (see Figure and Figure The high-speed transition minimized differential signaling (TMDS) lines add only 0.9-pF capacitance to the lines. In addition, the monolithic integrated circuit technology ensures that there is excellent matching between the two-signal pair of the differential line. This is a direct advantage over discrete ESD clamp solutions where variations between two different ESD clamps may significantly degrade the differential signal quality. The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line ESD clamps add 3.5-pF capacitance to the control lines. The 38-pin DBT package offers seamless layout routing option to eliminate the routing glitch for the differential signal pair. The TPD12S521 provides an on-chip regulator with current output ratings of mA at pin 38. This current enables HDMI receiver detection even when the receiver device is powered off. DBT package pitch (0.5 mm) matches with HDMI connector pitch. In addition, pin mapping follows the same order as the HDMI connector pin mapping. This HDMI receiver port protection and interface device is specifically designed for next-generation HDMI transmitter protection. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2007 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TMDS_D2+ TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– TMDS_CK+ TMDS_GND TMDS_CK– 5V_SUPPLY DDC_DAT_OUT HOTPLUG_DET_OUT ESD_BYP LV Supply LV Supply CE_REMOTE_IN CE_REMOTE_OUT DDC_DAT_IN LV Supply LV Supply DDC_CLK_IN DDC_CLK_OUT HOTPLUG_DET_IN 55-mA Overcurrent Switch 5V_OUT5V_SUPPLY TPD12S521 SLVS639A OCTOBER 2007 REVISED NOVEMBER 2008 www.ti.com ORDERING INFORMATION T A PACKAGE (1) (2) ORDERABLE PART NUMBER (3) TOP-SIDE MARKING C to C TSSOP-38 DBT TPD12S521DBTR PN521 (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com (3) Parts are shipped in tape-and-reel form, unless otherwise specified. ELECTRICAL SCHEMATIC Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TPD12S521
VIA Connected□to□LV□Plane VIA Connected□to□5V□Plane VIA Connected□to□GND□Plane GND 5□V□out High-speed□lines Control□lines 1 38 TPD12S521 HDMI□Core□Chip HDMI Connector CLK– GND CLK+ D0– GND D0+ D1– GND D1+ D2– GND D2+ HTDT 5OUT GND D_DT D_CK NC CE_R TPD12S521 www.ti.com SLVS639A OCTOBER 2007 REVISED NOVEMBER 2008 External bypass capacitors and resistor components not included Figure Board Layout for HDMI Transmitter Using TPD12S521DBTR Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPD12S521
www.ti.com PIN
DESCRIPTION
NO. ESD LEVEL 5V_SUPPLY kV (1) Current source for 5V_OUT LV_SUPPLY kV (1) Bias for CE/DDC/HOTPLUG level shifters 11,14, GND, TMDS_GND NA TMDS ESD and parasitic GND return (2) 25, 28, 31, 34, TMDS_D2+ kV (3) TMDS 0.8-pF ESD protection (4) TMDS_D2 kV (3) TMDS 0.8-pF ESD protection (4) TMDS_D1+ kV (3) TMDS 0.8-pF ESD protection (4) TMDS_D1 kV (3) TMDS 0.8-pF ESD protection (4) TMDS_D0+ 10, kV (3) TMDS 0.8-pF ESD protection (4) TMDS_D0 12, kV (3) TMDS 0.8-pF ESD protection (4) TMDS_CK+ 13, kV (3) TMDS 0.8-pF ESD protection (4) TMDS_CK 15, kV (3) TMDS 0.8-pF ESD protection (4) CE_REMOTE_IN kV (1) LV_SUPPLY referenced logic level into ASIC DDC_CLK_IN kV (1) LV_SUPPLY referenced logic level into ASIC DDC_DAT_IN kV (1) LV_SUPPLY referenced logic level into ASIC HOTPLUG_DET_IN kV (1) LV_SUPPLY referenced logic level into ASIC HOTPLUG_DET_OUT kV (3) V_SUPPLY referenced logic level out, plus 3.5-pF ESD (5) to connector DDC_DAT_OUT kV (3) V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector DDC_CLK_OUT kV (3) V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector CE_REMOTE_OUT kV (3) V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector ESD_BYP kV (1) ESD bypass. This pin must be connected to a 0.1- µ F ceramic capacitor. 5V_OUT kV (1) 5-V regulator output (1) Human-Body Model (HBM) per MIL-STD-833, Method 3015, C DISCHARGE 100 pF, R DISCHARGE 1.5 k Ω 5V_SUPPLY and LV_SUPPLY within recommended operating conitions, GND and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1- µ F ceramic capacitor connnected to GND. (2) These pins should be routed directly to the associated GND pins on the HDMI connector, with single-point ground vias at the connector. (3) Standard IEC 61000-4-2, C DISCHARGE 150 pF, R DISCHARGE 330 Ω 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1- µ F ceramic capacitor connected to GND. (4) These two pins must be connected together inline on the PCB. (5) This output can be connected to an external 0.1- µ F ceramic capacitor, resulting in an increased ESD withstand voltage rating. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TPD12S521
(1) RECOMMENDED OPERATING CONDITIONS TPD12S521 www.ti.com SLVS639A OCTOBER 2007 REVISED NOVEMBER 2008 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V 5V_SUPPLY Supply voltage V V LV_SUPPLY V I/O DC voltage at any channel input GND 0.5 V T stg Storage temperature range 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. MIN NOM MAX UNIT Operating supply voltage 5V_SUPPLY 5.5 V Bias supply voltage LV_SUPPLY 3.3 5.5 V Operating temperature C Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPD12S521
www.ti.com over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I CC5 Operating supply current 5V_SUPPLY V 110 130 µ A I CC3 Bias supply current LV_SUPPLY 3.3 V µ A V DROP 5V_OUT overcurrent output drop 5V_SUPPLY I OUT mA 150 200 mV I SC 5V_OUT short-circuit current limit 5V_SUPPLY= 5V_OUT GND 135 175 mA OFF-state leakage current, I OFF LV_SUPPLY V 0.1 µ A level-shifting NFET TMDS_D[2:0]+/ TMDS_CK+/ CE_REMOTE_OUT, Current conducted from output pins to I BACKDRIVE 5V_SUPPLY V CH_OUT DDC_DAT_OUT, 0.1 µ A V_SUPPLY rails when powered down DDC_CLK_OUT, HOTPLUG_DET_OUT, 5V_OUT Voltage drop across level-shifting NFET V ON LV_SUPPLY 2.5 V S GND, I DS mA 140 mV when ON Top diode 0.85 I F mA, V F Diode forward voltage V T A C (1) Bottom diode 0.85 Pins 10, 13, 24, 27, 30, (1) (2) IEC V ESD ESD withstand voltage kV Pins 19, 37, (1) (3) HBM Positive transients Channel clamp voltage V CL T A C (1) (3) V at 8-kV HBM ESD Negative transients Positive transients R DYN Dynamic resistance I T A C (4) Ω Negative transients 1.5 I LEAK TMDS channel leakage current T A C (1) 0.01 µ A C IN 5V_SUPPLY= Measured at MHz, TMDS channel input capacitance 0.8 1.0 pF TMDS V BIAS 2.5 V (1) Δ C IN TMDS channel input capacitance 5V_SUPPLY= Measured at MHz, 0.05 pF TMDS matching V BIAS 2.5 V (1) (5) Mutual capacitance between signal pin 5V_SUPPLY= Measured at MHz, C MUTUAL 0.07 pF and adjacent signal pin V BIAS 2.5 V (1) DDC 3.5 Level-shifting input capacitance, 5V_SUPPLY= Measured at 100 KHz, C IN CEC 3.5 pF capacitance to GND V BIAS 2.5 V (1) HP 3.5 (1) This parameter is specified by design and verified by device characterization. (2) Standard IEC 61000-4-2, C DISCHARGE 150 pF, R DISCHARGE 330 Ω (3) Human-Body Model (HBM) per MIL-STD-883, Method 3015, C DISCHARGE 100 pF, R DISCHARGE 1.5 k Ω (4) These measurements performed with no external capacitor on ESD_BYP. (5) Intrapair matching, each TMDS pair (i.e., D+, D Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s): TPD12S521
–15 –13 –11 Frequency (Hz) Insertion Loss (dB) DC Bias = 0 V DC Bias = 3.0 V TPD12S521 www.ti.com SLVS639A OCTOBER 2007 REVISED NOVEMBER 2008 Figure Insertion Loss Performance Across Frequency Figure Test Board to Measure Eye Diagram for the TPD12S521 (Refer to Eye Diagram Plot) Figure HDMI 1.65Gbps Eye Diagram With TPD12S521 Figure HDMI 1.65Gbps Eye Diagram Without on a Test Board TPD12S521 in the Socket in the Test Board Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPD12S521
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPD12S521DBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPD12S521DBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2008 Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 21-Nov-2008 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD12S521DBTR TSSOP DBT 38 2000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 21-Nov-2008 Pack Materials-Page 2
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