TPC1020AVE-044

TPC10 TI | Alldatasheet

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CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SRFSOO1F — 09864, DECEMBER 1989 — REVISED FEBRUARY 1993, ai aS Sa © Four Arrays With up to 2000 Usable Equivalent Gates VO and Peripheral Circuits COO © Ti Action Logic™ System (TI-ALS) Software .)aSSSpzzz === s for: | SaaS z=—EES— — Mentor™ 3 z ~ OrCAD/SDT Il ™ Z — Hi - Cadence™/Valia™ ; —— Fi © Reliable Antifuse Interconnect 3) Goo |S © Built-In Clock Distribution Network e — 2 © Silicon-Gate CMOS Technology Toorop © Desktop TI-ALS Creates Design Files for: [__| Wohin Periphéral Cibuits — W/O Pin Assignment — Design Validation = Place and Route Rows of Logic Modules - Circuit Timing Analysis Interconnect Tracks — Array Antifuse Programming ~ Test and Debug TPC10 Series FPGA Die Architecture

description

The Texas Instruments (Tl) TPC10 Series comprises four field-programmable gate arrays (FPGAs). The TPC1010A, TPC1010B, TPC1020A, and TPC1020B FPGAs are fabricated using the TI silicon-gate CMOS process. The process features polysilicon gate, source, drain elements, and two levels of copper-doped-aluminum metallization to reduce internal resistance and enhance performance. Typical die architecture is illustrated above. These field-programmable devices combine gate-array flexibility with desktop programmability. This combination allows the designer to avoid fabrication cycle times and nonrecurring engineering charges associated with conventional mask-programmed gate arrays. The FPGAs are unique in that the arrays are fabricated, tested, and shipped to the user for programming. The FPGA contains user-configurable inputs, outputs, logic modules, and minimum-skew clock driver with hardwired distribution network. The FPGA also includes on-chip diagnostic probe capabilities and security fuses to protect the proprietary design. Table 1. Product Family Profile Cadence/Valid are trademarks of Cadence Design Systems, Inc. OrCAD/SOT Ills a trademark of Orad Systems Corporation. ViewLogicis a trademark of Viewlogic System, Incorporated.

combination facilitates logic design and FPGA programming on popular CAE workstations with minimum effort. workstations, and ViewLogic- or Valid/Cadence-equipped Sun-4 workstations. functions that can be called into the design. provides an overview of the design flow. Figure 1. Design Flow

26 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75268

Table 2. TI-ALS Design Configurations (see Note 1) Table 3. TI-ALS Programming Configurations (see Note 2) HARDWARE CAE HOST DESIGN SUPPORT. TLSUSTEM.

CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SRFS001F — 03864, DECEMBER 1989 — REVISED FEBRUARY 1993, SED FEBRUARY 1993 interconnect tracks The channeled interconnect tracks consist of isolated metal segments that can be connected by addressing and Programming antifuses. Each channel has 25 horizontal routing tracks, 22 are for logic, one is for clock, one is for power, and one is for ground. In addition, there are 13 vertical routing tracks per logic module column. Both horizontal and vertical tracks, in combination with the approximately 340 antifuses per logic module, produce a network that is capable of interconnecting up to 90 percent of the equivalent gates. Based on the placement of macros, the programming process selects and activates antifuses that both create the logic module macros. and I/Os, and interconnect the entire array. VO buffers Each I/O pin is configurable as an input or an output. In addition, /O pins configured as outputs can be defined as totem-pole, 3-state, or bidirectional. Inputs can be driven by CMOS or TTL levels and output levels are compatible with standard CMOS and TTL specifications. Outputs sink or source a current of 4 mA at TTL output levels. See the de characteristics for additional I/O butfer specifications. The I/Os can be manually assigned to any available package pin, or the ALS software can automatically place the /Os in the. optimum configuration. diagnostic probe pins TPC10 Series devices have two independent diagnostic Probe pins, PRA and PRB. The pins allow the user to observe any internal signals by entering the appropriate net name in the diagnostic software. Signals may be viewed on an oscilloscope, logic analyzer, or with the workstation diagnostics using the Actionprobe diagnostic tools. The probe pins can also be used as user-defined /Os, depending on the level of the mode control pin. When configured as user-defined I/Os, the pins have the same characteristics as other I/O pins. security fuses The TPC10 Series security fuses can be used to permanently disable further diagnostics and testing. After the security fuses are programmed, access to the architecture is not available. This makes the FPGA. design difficult to copy. cr INSTRUMENTS POST OFFICE BOX 655303 © DALLAS, TEXAS 75285 29

CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SRFS001F — 03864, DECEMBER 1989 — REVISED FEBRUARY 1993 FPGA array performance logic module size A mask-programmed gate array cell with four transistors usually implements only one logic level. The TPC10 Series array logic module is more complex and typically implements multiple logic levels within a single module. This reduces intermodule wiring and associated RC delays. In effect, the TPC 10 logic module implements the equivalent of a net compression that enhances performance. TERMINAL FUNCTIONS ee ee CLK ‘Clock. TTL clock input for global clock distribution network. The clock input is butfered prior to clocking the logic modules. This pin can also be used as an VO. DCLK Diagnostic clock. TTL clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is high. This pin functions as an /O when the MODE pin is low. | GNO_ | 1 _ | Ground. input low supply voltage. vO Inpuvoutput. VO pin functions as an input, output, 3-state, or bidirectional butter. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically set low by the ALS software, Mode. The MODE pin controls the use of multifunction pins (DCLK, PRA, PRB, SDI). When the MODE pinis high, the special functions are active. When the MODE pin is low, the pins function as VOs. [nc |__| Noconnection. This pin is not connected to circuitry within the device. PRA Probe A. The probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the probe B pin to allow real-time diagnostic output of any signal path within the device. The probe A pin can be used as a user-defined /O when debugging has been completed, The pin's probe capabilities can be permanently disabled to protect the programmed design’s confidentiality. PRA is active when the MODE pin is high. This pin functions as an VO when the MODE pin is low. PRB Probe B. The probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the probe A pin to allow real-time diagnostic output of any signal path within the device. The probe B pin can be used as a user-defined l/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect the programmed design's confidentiality. PRB is active when the MODE pin is high. This pin functions as an /O when the MODE pin is low. SDI Serial data input. Serial data input for diagnostic probe and device programming. SD1is active when the MODE pin is high. This pin functions as an VO when the MODE pin is low. [Voc [| [Supply voltage. Input high supply voltage. Vpp Programming voltage. Input supply voltage used for device programming. This pin must be connected to Vcc during normal operation. Seen el INSTRUMENTS 2:10 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265

CMOS FIELD-PROGRAMMABLE GATE ARRAYS SRFS001F — 03864, DECEMBER 1989 - REVISED FEBRUARY 1993 a SED FEBRUARY 1953 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t Supply voltage range , VOC «2... eevee cece ec ee ec eeet eerste eter eteeessteesereeeses 0.5 Vt07V Output clamp current8, lox (Vo <0 Or VQ >Voc) . 6-2. ee ee cececeeeee ec ceveeereeeeeeeeseeve, $20MA Continuous output currents, (Vo = OO VEE) - oer eee ee cece cece e eee ee eee eee eee ees £25 MA t Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. + Applies for input and bidirectional butters § Applies for bidirectional and output butters recommended operating conditions a Cd Voc Supply votage a [ep Prosrampinvohage (hie netpramming) Sd Veg Vo | [Eonmenar [0 70] a ey [Tg Operating case temperature Mitary 85 | od a _ TEXAS % INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265 211

CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SRFSOO1F — 09864, DECEMBER 1989 REVISED FEBRUARY 1993 electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted) test [csurrx [isurrix [| msurrx | CONDITIONS Tyet max] win tet Max Highievelouiputvotage [lon=-4ma [sae YOM (eee tite 3) liov=-sema [ar iC Low-level output voltage . a A li iputcurent[vievoowo [| of OS _cureniseonatea) [Yoo =10—voo | -10 _~1oo 1010 Standby supply Vi= Voc ord, lec Servo [eater [eof at] | Inpuvoutput capacitance | Vo = 0, leo omg [ieee Pt Pd | Typical values are at Voc = 5 V. Ta = 25°C. NOTES: 3. These limits apply when all other outputs are open. 4. Whentesting TPC1010A and TPC1020A, not more than one output should be shorted at atime, and duration of the shor circuit should not exceed one second. The log parameter does not apply to TPC 10108 or TPC1020B. 5. These limits apply for each user VO pin. switching characteristics The following tables summarize switching characteristics of various classes of TPC10 Series logic module hardwired macros. An unloaded logic module propagation delay time is 4 ns. All other delays shown include the module delay time and statistical estimates for wiring delays based on 85% to 95% FPGA logic module utilization. Module utilization above 95% can result in performance degradation. Actual delay values are determined after place and route is accomplished using the ALS. ALS provides for assigning criticality to nets, automatic balancing of clock buffer loads, and utilizing long horizontal or vertical nets for connecting noncritical functions. For specific timing parameters pertaining to a hardwired logic module, refer to the individual macro library specification. The ALS provides a capability to assign one of four levels of criticality to logic module output nets. The switching characteristics reflect the delay time differences for nets with criticality and without criticality assigned. Nets assigned as critical will be limited to a fan-out of 6 loads by the ALS. Clock load balancing, selectable by the designer, can be specified as moderate, strong, or very strong to control clock skew. SS INSTRUMENTS 212 POST OFFICE BOX 655303 ® DALLAS. TEXAS 75265

CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SRFS001F — 09864, DECEMBER 1989 — REVISED FEBRUARY 1993 NN eR timing requirements over recommended operating conditions, no further derating required a [tclock Clock requency dS [fow2 es tw Pulse duration CLK, PRE, or CLR [isu Seuptime, Tifa | Asyncfrenovs pos bales dock wanstion | 33] ns _] ‘Al synchronous inputs betore clock i sync it fore ‘ey Setuptine, atch hoped a [th __Hold time, flip-flop or latch [All synchronous inputs after clock transition [ons typical switching characteristics single-level logic module hardwired macro (module count = 1) , Voc = 5 V, Ty = 25°C, typical process PARAMETER | OUTPUT-NET CRITICALITY ranma | oururerenmensry Fase post | weet | ea] CC CO a CH double-level logic module hardwired macro (module count = 2) , Vcc = 5 V, Ty = 25°C, typical process ONT STONY [ross Foza [rosa [ rosa | roe | = a A flip-flop and latch hardwired macro, Vcc = 5 V, Ty = 25°C, typical process x OUIPUTNEY GRIMGALITY [| fo=1 | Fo-2 [| fo=3 [ Foz« | Fo-e | a La | Nateteat oT er 7 Tes t08 Tos | NOTES: 6. An unloaded logic module propagation delay time is 4 ns. All delays shown include the module delay time and statistical estimates for wiring delays based on 85% to 95% FPGA logic module utilization, 7. Critical nets are limited to a fan-out of 6 loads. long net, Vcc = 5 V, Ty = 25°C, typical process Long nets include long horizontal and vertical routing resources used for noncritical signals and interconnecting logic macros separated by large distances. Long nets are used by the autorouter when no other means exist to complete the interconnection. Delays due to the use of long nets range from 15 ns to 35 ns. Typically less than one percent of all nets in a design require the use of a long net. eS INSTRUMENTS POST OFFICE BOX 655303 © DALLAS, TEXAS 75265, 2413

CMOS FIELD-PROGRAMMABLE GATE ARRAYS SAFSOO1F - 03864, DECEMBER 1969 REVISED FEBRUARY 1299 typical switching characteristics input buffer and bidirectional-input bufter, Vcc = 5 V, Ty = 25°C, typical process (NpuT) qoureun_[ Ffo=1 | Fo=2 [ Fo=3 [ Fo-a | Fo=8 | [ee Te [oy Pe pe pe pe fe Lote [so [es 7 Tes ea output buffer, Vcc = 5 V, Ty = 25°C, typical process FROM To DRIVING DRIVING [raraneren [gen | coutmm | cowmone | cucsvonos | reconos | O | [38] cee ce ee eel ns/pF The BIBUF macro’s output section exhibits the same delays as the OUTBUF macro. The delta numbers can be extrapolated down to 15 pF minimum. Example: Delay for an OUTBUF output buffer driving a 100-pF TTL load 3-state and bidirectional output buffer, Vcc = 5 V, Ty = 25°C, typical process FROM To DRIVING DRIVING [rasaweren | iret | couttun _[veereomamons | cyortonos | revouos | O | ee | ee ee ania | texz | re ee [-tezH | [es ag [teze | ee | Pad See test loads F Ea “ imrgues [007 | oo | | Ateuz | a ee a | Reto fm | [08 [2000] clock buffer, Vcc = 5 V, Ty = 25°C, typical process (see Note 8) [ ranaweren | rrow | 0 | Form Troster | Se ee eee eee ; = = | NOTE 8: The ALS software provides user-selectable options for choosing four levels of automatic clock load balancing. There is no limit to the number of loads that may be connected to the clock buffer (CLKBUF) macro. i TEXAS % INSTRUMENTS 2-14 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265.

CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SRFSO01F — 09864, DECEMBER 1989 — REVISED FEBRUARY 1993. extended output current operation The TPC10 Series devices are capable of driving larger sink current loads by derating the low-level output voltage to 0.5 V and high-level output voltage to 2.4 V. The derating factors for commercial and military devices are illustrated in Figure 4 and Figure 5. The commercial devices are derated up to 8 mA and military devices are derated for up to 6 mA. LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE vs vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT oT Te lek T EET TT TTT > 05 > 5 ‘ oT IA ; i Z| 2 3 04 =a s 4 Pa i g Td) 3 03 Commercial Devices 3 3 4 = j we) LL} es % 0.2} For Military Devices z 2} — Military Devices |e. wittary Devices

3 Voc=45V Ed Yoo=45V

1, Ty= 125°C i Ty= 125°C 2 "F cor commercial Devices 5) For Commercial Devices| Ve =4.75V Voc =4.75V lL TES ° Tj=70°C o 41 2 3 4 5 6 7 8 -8 -7 -6 -5 -4 -3 -2 -1 0 loL ~ Low-Level Output Current - mA lol — High-Level Output Current - mA Figure 4 Figure 5 slow input transition (rise and fall) times Slow signal transition is a condition that commonly occurs even in today's high-performance systems. A typical example is the signal degradation encountered with signals coming off of a highly capacitive bus. These slow signal transitions can cause undesirable results when traveling through the threshold region of a CMOS input. Texas Instruments recommends that input signal transitions be limited to 500 ns or less to ensure device integrity. worst-case delay time Unlike mask-programmed gate arrays, performance variations of TPC10 Series arrays caused by voltage and temperature changes are due primarily to the changes in the active elements. Voltage and temperature delay time factors are shown in Figure 6 and Figure 7. o_o INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265 215

recommended operating conditions for TPC 10 commercial, industrial, and military applications. postlayout timing specifications for each circuit implementation. Table 4. Timing Derating Factor (x typical) (see Note 9)

Figure 8. Symbols, Test Loads, and Voltage Waveforms.

LOAD CIRCUIT FOR PROPAGATION DELAY TIMES. LOAD CIRCUIT FOR ENABLE AND DISABLE TIMES. Figure 8. Symbols, Test Loads, and Voltage Waveforms (Continued)

CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SRFSOO1F — 03864, DECEMBER 1989 — REVISED FEBRUARY 1993 an a a dynamic power calculations The formula for calculating typical dynamic die power consumption in mW is: Total die power = (0.20N x f1) + (0.085M x f2) + (0.80P x £3) where: f1 = Average logic module switching rate in MHz f2 = Average clock pin switching rate in MHz (see Note 10) 3 = Average I/O switching rate in MHz M = Number of logic modules connected to the clock pin (see Note 10) N = Number of logic modules used on the chip (including M) P = Number of I/Os used with 50-pF load NOTE 10: The F2 and M factors can be ignored if the CLKBUF macro is not used. For example, if a TPC1010A design has 200 logic modules used, 40 of which are connected to the high-fan-out clock buffer running at 20 MHz and the rest running at 4 MHz, plus 50 I/Os (25 outputs, 25 inputs) running at an average of 4 MHz, it will dissipate the following amount of power: Total die power = (0.20N x f1) + (0.085M x {2) + (0.80P x £3) = 0.20 (200 x 4) + 0.085 (40 x 20) + 0.80 (25 x 4) = 308 mw ESD rating ESD characterization of Texas Instruments FPGAs is performed in accordance with Method 3015 of MIL-STD-883, This calls out the human body model which included discharging a 10-pF capacitor through a 1.5-kQ resistor. Three positive and three negative pulses are discharged into each pin at each voltage level. After pulsing, the units are tested on a VLSI tester. Testing is performed for initial device qualification and product redesign only. All devices have been designed for ESD protection. OE Texas INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265 249

CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SRFSOO1F — 03964, DECEMBER 1989 REVISED FEBRUARY 1993 a eee eeeeeeeeeeeeeEEEeEeEeEeEeEeEeEeEeEeEeEeee package thermal characteristics The device junction to case thermal characteristic is Ra jc, and the junction to ambient air characteristic is Raja. The thermal characteristics for Reya are shown with two different air-flow rates. Maximum junction temperature is 150°C for short durations. However, a maximum junction temperature of 140°C is recommended for continuing operation. A sample calculation of the maximum power dissipation for a PLCC 84-pin package at commercial temperature is as follows: Max. junction temp. (°C) ~ Max. commercial temp. (°C) __ 150°C - 70°C _ > w Rogan (CW) “40°C Rosa Rosa [mena [mor [ne [ait | aie [| Ceramic Pin Grid Array emer fw Te Pe mw Ceramic Quad Flat [romeo | Ts Pm 44 13 65 a1 84 40 40 27 Plastic Quad Flat Package corr |e Pe Poe foe Tw Package Case Air Flow ae \\ aa — Device Junction LS INSTRUMENTS 2-20 POST OFFICE BOX 655900 ® DALLAS, TEXAS 75265

CMOS FIELD-PROGRAMMABLE GATE ARRAYS SRFSoO1F — D2964, DECEMBER 1989 REVISED FEBRUARY 1983 TPC1010A device availability and resources Commercial PACKAGE toGie USER Os TPE MODULES [so | 4 | [sw [ ard a Industrial PACKAGE LOGIC SPEED GRADE TYPE MODULES [sm [saa Cn a a Military PACKAGE toGie a Bé-pin COFP =e | ow; 3} — +} + R = released P = planned, consult your local TI sales representative for current availability. TPC1020A device availability and resources Commercial PACKAGE LOGIC SPEED GRADE TYPE MODULES ee [=| a | a _| [a [a | ra 547 a ES Industrial PACKAGE LOGIC SPEED GRADE TYPE MODULES a | spin PLEO | Gépin PLEO a | “ a a a < Military Loaic MODULES [= [| = | a -pin CPGA S47 84-pin COFP | R = released P = planned, consult your local TI sales representative for current availability. a INSTRUMENTS POST OFFICE BOX 655303 ® DALLAS, TEXAS 75285 2-21

CMOS FIELD-PROGRAMMABLE GATE ARRAYS SRFS001F — 03864, DECEMBER 1989 — REVISED FEBRUARY 1993, TPC1010B device availability and resources Commercial PACKAGE [seep anaes (CKAG! Loic USER VOs ‘SPEED GRADE TYPE MODULES ee A 295 [7 [ | a |_| A Industrial PACKAGE Loaic SPEED GRADE Tyee | _mooutés a a a A R = released P = planned, consult your local T| sales representative for current availability. TPC1020B device availability and resources Commercial PACKAGE] LOGIC Geen ioe TYPE MODULES Se a a 547 a [ee ee Industrial Logic ‘SPEED GRADE MODULES a A 547 a a A R= released P = planned, consult your local TI sales representative for current availabilty. ed INSTRUMENTS 2-22 POST OFFICE BOX 655909 © DALLAS, TEXAS 75265,

CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SRFS001F — 03864, DECEMBER 1969 — REVISED FEBRUARY 1993.

ordering information

Configurations of the TPC10 Series devices can be ordered using the part numbers in the examples below. Commercial and industrial versions can be ordered as follows: EXAMPLE ————> TPC 1010 A FN-068C 14 PREFIX ne LL SPEED GRADE (optional) DEVICE TYPE TEMPERATURE RANGE 1010= 1200 Equivalent Gate Array C = OC 10 70°C | 1020 = 2000 Equivalent Gate Array 1 = =40°C to 85°C DEVICE REVISION DEVICE PINS ‘A= TI 1.2-{1m CMOS Technology 044 = 44 pins B = TI 1.0-1m CMOS Tech 068 = 68 pins ail novo 084 = 84 pins 100 = 100 pins PACKAGE TYPE FN = Plastic leaded chip carrier VE = Plastic quad flat package Military versions can be ordered as follows: EXAMPLE ————® IPC 1010 A M GB 84 B-1 B = Class B processing DEVICE TYPE 4010= 1200 Equivalent Gates Beg ace equivalent 1020 = 2000 Equivalent Gates lank = Commercial processing DEVICE PINS DEVICE REVISION 84= 84 pins ‘A= TI 1.2-Uum CMOS Technology PACKAGE TYPE ‘GB = Ceramic pin grid array HT = Ceramic quad flat package HFG = Ceramic quad flat package with nonconductive tie bar TEMPERATURE RANGE M = ~55°C to 125°C DEFENSE ELECTRONIC SYSTEM CENTER (DESC) NUMBER DEVICE NAME proceesina NUMBER TPC1010AM Class B 5962-9096401M ‘TPC1020AM Class B 5962-9096501M Space Equivalent macro library The TPC10 Series is supported by a macro library of more than 250 hardwired and soft macro functions. The macros range from primitive logic gates to MSI-level complex functions such as counters, decoders, and comparators. The hardwired macro characteristics are provided in the electrical and switching characteristics. The software macros have characteristics similar to the components of the macro but need the place and route data back annotated into the design to establish actual performance. The FPGA logic module implements logic functions with inverted inputs as efficiently as noninverted inputs, without an increase in propagation delay. By taking advantage of the various combinations of input polarity, the use of separate inverters can be virtually eliminated. ee TEXAS % INSTRUMENTS POST OFFICE BOX 655909 © DALLAS, TEXAS 75265, 2:23

CMOS FIELD-PROGRAMMABLE GATE ARRAYS ‘SAFS0O1F — D3864, DECEMBER 1989 - REVISED FEBRUARY 1993 Se TPC10 SERIES SOFTWARE MACROS MACRO NAME DESCRIPTION MODULE COUNT LOGIC LEVELS t These MSI functions are hardwired, SS Texas B INSTRUMENTS 2:24 POST OFFICE BOX 655903 @ DALLAS, TEXAS 75265,

Figure 11. 4-Input Gates

8 B 8

Figure 12. XOR/XNOR Gates Figure 13. XOR-OR/XNOR-OR Gates Figures 14. XOR-AND/

8 B B

Figure 15. AND-XOR/AND-XNOR Gates

Figure 16. AND-OR/AND-NOR Gates

4 Indicates extra delay input

Figure 17. OR-AND/OR-NAND Gates

Figure 20. Multiplexers

Figure 21. Adders

Figure 22. D-Type Latches 2-32 POST OFFICE BOX 655303 ® DALLAS, TEXAS 75265.

Figure 22. D-Types Latches (Continued)

Figure 23. D-Type Flip-Flops

3 E 3 3

Figure 24. D-Type Flip-Flops With Enable

Figure 25. J-K Flip-Flops

‘SRFS001F — 03864, DECEMBER 1989 — REVISED FEBRUARY 1993. MULTIPLEXED-INPUT FLIP-FLOPS WITH CLEAR.

8 B Q 8 8

Figure 26. Multiplexed-Input Flip-Flops

40 A7:0] Al15:0] acer

Figure 29. Comparators/Parity Checker Figure 30. Counters

Figure 31. Decoders

‘SRFS001F — D3864, DECEMBER 1989 — REVISED FEBRUARY 1993 Dae eee eee ee package pin assignments 9 2 2 3 6 5 43 2 14443424140 fo 7q F= 39 PRB or 10 aq |= 38 PRA or V0 9c [37 DCLK OR VO GND 10 4 {> 36 SDI or VO uc F 35 Voc 244 }] 34 MODE P VIEW) 3 (ror VIEW) Fi a3 cLk or vo Veo 144 F= 32 GND 6c =e Vpp 16 CJ F 30 wa I 29 TUUUUUUUUUo 18 19 20 2122 23 2425 2627 28 g 8 co) > NOTES: A. All pins marked GND are ground connections and must be connected to circuit ground. B. Ypp mustbe teminaled © Voc excet ‘during programming c. and PRB, the diagnostic probe outputs, should remain open it not used as /Os. D. MODE must be terminated to circuit ground except during programming.t E. SDI and DCLK should be terminated to circuit ground during normal operation if not used as /Os.t F. Unused V/O pins are automatically designated by the Action Logic System as outputs and should remain unconnected. Unused VO pins are driven low by design. G. All unidentified pins on the pin assignment drawings are standard /Os. t The security fuse must be programmed for SDI and DCLK to function as /Os. For device debugging on the user's circuit board, MODE, SDI, and DCLK should be terminated to circuit ground through a 10-kQ (or greater) resistor. They can be tied to ground if not debugging, Figure 35, 44-Pin PLCC Pin Assignment Se Teas INSTRUMENTS 2-42 POST OFFICE BOX 655309 @ DALLAS, TEXAS 75265

NOTES: A. All pins marked GND are ground connections and must be connected to circuit ground. C. PRA and PRB, the diagnostic probe outputs, should remain open if not used as /Os. G. All unidentified pins on the pin assignment drawings are standard I/Os. and DCLK should be terminated to circuit ground through a 10-kQ2 (or greater) resistor. They can be tied to ground if not debugging. Figure 36. 68-Pin PLCC Pin Assignment

6 P71

B. Vpp must be terminated to Vcc except during programming. C. PRA and PRB, the diagnostic probe outputs, should remain open if not used as V/Os. pins are driven low by design. G. All unidentified pins on the pin assignment drawings are standard /Os. and DCLK should be terminated to circuit ground through a 10-kQ (or greater) resistor. They can be tied to ground if not debugging. Figure 37. 84-Pin PLCC Pin Assignment

2.44 POST OFFICE BOX 655903 © DALLAS, TEXAS 75265,

C. PRA and PRB, the diagnostic probe outputs, should remain open if not used as Os. pins are driven low by design. G. All unidentified pins on the pin assignment drawings are standard /Os. H. Orientation pin C3 is connected internally to pin C2. Figure 38. 84-Pin CPGA Pin Assignment

NOTES: A. All pins marked GND are ground connections and must be connected to circuit ground. B. Vpp must be terminated to Vc except during programming. pins are driven low by design. G. All unidentified pins on the pin assignment drawings are standard Os. Figure 39. TPC1010A 84-Pin CQFP Pin Assignment

NOTES: A. All pins marked GND are ground connections and must be connected to circuit ground. C. PRA and PRB, the diagnostic probe outputs, should remain open if not used as Os. pins are driven low by design. G. All unidentified pins on the pin assignment drawings are standard 1/Os. Figure 40. TPC1020A 84-Pin CQFP Pin Assignment

2222 Fa & S22222

NOTES: A. All pins marked GND are ground connections and must be connected to circuit ground. B. Vpp must be terminated to Voc except during programming. C. PRA and PRB, the diagnostic probe outputs, should remain open if not used as /Os. pins are driven low by design. G. All unidentified pins on the pin assignment drawings are standard V/Os. Figure 41. TPC1010A 100-Pin PQFP Pin Assignment

961 Fr 35

Vpp mustbbe terminated to Vcc except during programming.

C. PRA and PRB, the diagnostic probe outputs, should remain open if not used as /Os. pins are driven low by design. G. All unidentified pins on the pin assignment drawings are standard VOs. and DCLK should be terminated to circuit ground through a 10-kQ2 (or greater) resistor. They can be tied to ground if not debugging. Figure 42. TPC1020A 100-Pin PQFP Pin Assignment

CMOS FIELD-PROGRAMMABLE GATE ARRAYS SRFSOO1F — 03864, DECEMBER 1989 — REVISED FEBRUARY 1993 ee ee actionprobe pin assignments There are four types of Actionprobes available: 44-, 68-, and 84-pin PLCC, and 84-pin PGA. At the time your order is placed, please specify which Actionprobe you need. The Actionprobes are detailed in Figure 43 through Figure 46. . ROROReKG) ®™@e@ e@ iC) ° 3 ene 5 3 @ @ Index Notch 0) ee \\J|@ ©OOGC®e @ Indicates no connection NOTE: The view shown is from the TOP with pin 1 of the device facing down. Figure 43, 44-Pin PLCC Actionprobe Teas INSTRUMENTS 2-50 POST OFFICE BOX #85903 © OALLAS, TEXAS 75265

NOTE: The view shown is from the TOP with pin 1 of the device facing down. Figure 44. 68-Pin PLCC Actionprobe

CMOS FIELD-PROGRAMMABLE GATE ARRAYS actionprobe pin assignments (continued) @ HOG OOOODOG® e®@ e@ @®@ @ @ @ © @@ ®®@ @ @ @ (TOP VIEW) @ ® @ oa) OKC) © @®@ Index Notch \\ ® t Rc) , OX) ®®9O@O8 OOOOO®O @ Indicates no connection NOTE: The view shown is from the TOP with pin 1 of the device facing down. Figure 45, 84-Pin PLCC Actionprobe eS TEXAS % ose rn NSE RUMENTS

1 Js 3 2 1 20 19 yeh [e]o18 (007 STeS| AG) Fe |

NOTES: A. All dimensions conform to JEDEC Specification MO-047AWVAF. Dimensions and tolerancing are per ANSI Y14.5M-1982. D. Datum [-H-| is located at top of leads where they exit plastic body. Figure 47. Plastic Leaded Chip Carriers

radius relative to the center of the ceramic. B. Orientation pin C3 is connected internally to pin C2. Figure 48. 84-Pin Ceramic Pin-Grid-Array Package

Figure 49. 84-Pin Ceramic Quad Flat Package

Figure 50. 84-Pin Ceramic Quad Flat Package With Nonconductive Tie Bar

0.05 MM/MM]A- B)

Figure 51. Plastic Quad Flat Packages 2-58 POST OFFICE BOX 655903 ® DALLAS, TEXAS 75265.

CMOS FIELD-PROGRAMMABLE GATE ARRAYS SRFS001F — 03864, DECEMBER 1989 - REVISED FEBRUARY 1993 g g 5 me : i 5 5 HI ig ot #8 ge SE 2s j 22 ES ee iigieley SD eres g(a] = 3 24 3 g2 3 il PEE GE Pep afte eee 4AAAAR MA gle Tous B sor INSTRUMENTS. as

Following are the pin loadings for the TPC 10 Series 1.2-m and 1.0-ym CMOS Field-Programmable Gate Arrays. Use this with the TPC10 Series Data Sheet and the Critical Path Analysis for FPGAs application report located in the Applications Chapter in this manual, to estimate manually the achievable system speed for a design implemented ina TI TPC10 Series FPGA. The index below will help you find the desired item in this supplement. Name Page Table Name Page Table Name Page Table AND2 2-62 1 DECES3X8A 2-73 61 DFME1A = 2-70 46 AND2A 2-62 1 DF1 2-68 39 DFP1 2-69 at AND2B 2-62 1 DFIA 2-68 39 DFPIA 2-69 41 AND3 2-62 2 OF1B 2-68 39 OFP1B 2-69 4 AND3A 2-62 2 DFIC 2-68 39 DFP1C 2-69 41 AND3B 2-62 2 DFC1 2-69 40 DFP1D 2-69 41 AND3C 2-62 2 DFCIA 2-69 40 DFPIE 2-69 4a AND4 2-63 3 DFC1B 2-69 40 DFP1F 2-69 41 AND4A 2-63 3 DFC1C 2-69 40 DFPIG 2-69 41 AND4B 2-63 3 DFC1D 2-69 40 DFPC 2-69 42 AND4C 2-63 3 DFCIE 2-69 40 DFPCA 2-69 42 AND4D 2-63 3 DFC1F 2-69 40 DL1 2-67 29 AO1 2-64 8 DFCIG 2-69 40 DLIA 2-67 29 AOIA 2-64 8 DFE 2-69 43 DLIB 2-67 29 AO1B 2-64 8 DFE1B 2-69 43, DLIC 2-67 29 AO1C 2-64 8 DFE1C 2-69 43 DL2A 2-67 33 AO2 2-64 8 DFE2D 2-70 44 DL2B 2-67 33 AO2A 2-64 8 DFESA 2-70 44 DL2C 2-67 33 AOS 2-64 8 DFE3B 2-70 44 DL2D 2-67 33 AO4A 2-64 8 DFE3C 2-70 44 DLC 2-67 30 AO5A 2-64 8 DFE3D 2-70 44 DLC1 2-67 30 AON 2-64 8 DFE4 2-70 44 DLC1A 2-67 30 AOHMA 2-64 8 DFE4A 2-70 44 DLC1F 2-67 30 AONB 2-64 8 DFE4B 2-70 44 DLC1G 2-67 30 AOI2A 2-64 8 DFE4C 2-70 44 DLC8A 2-67 3 AOI2B 264 8 DFEA 2-69 43 DLCA 2-67 30 AOI3A 2-64 8 DFEB 2-70 44 DLE 2-68 34 AOI4 2-64 8 DFEC 2-70 44 DLE1D 2-68 34 AX1 2-63 7 DFED 2-70 44 DLE2A 2-68 35 AXIA 2-63 7 DFM 2-70 46 DLE2B 2-68 35 AX1B 2463 7 DFMA 2-70 46 DLE2C 2-68 35 BIBUF 2-65 1 DFMB 2-70 46 DLE3A 2-68 35 BUF 2-64 10 DFM1B 2-70 46 DLE3B 2-68 35 BUFA 2-64 10 DFM1C 2-70 46 DLE3C 2-68 35 CLKBUF 2-65 1 DFM3 2-70 46 DLE8 2-68 36 CLKBIBUF 2-65 1 DFM3B 2-70 46 DLEA 2-68 34 CNT4A 2-72 56 DFM3E 2-70 46 OLEB 2-68 34 CNT4B 2-72 56 DFM3F 2-70 46 OLEC 2-68 34 CM8A 2-73 68 DFM3G 2-70 46 DLM 2-68 37 DEC2X4 2-72 60 DFM4 2-71 47 DLM2A 2-68 37 DEC2X4A 2-72 60 DFM4A 2-71 47 OLMA 2-68 37 DEC3X8 2-73 61 DFM4B 2-71 47 OLM8 2-68 38 DEC3X8A 2-73 61 DFM4C— 2-71 47 DLME1A 2-68 37 DEC4X16A 2-73 62 DFM4D 2-71 47 OLP1 2-67 32 DECE2xX4 2-72 60 DFM4E 2-71 47 DLPIA 2-67 32 DECE2X4A 2-72 60 DFM5A 2-71 48 OLP1B 2-67 32 DECE3X8 2-73 61 DFM5B 2-71 48 DLP1C 267 32 LS TEXAS % INSTRUMENTS 2-60 POST OFFICE BOX 655203 ® DALLAS, TEXAS 75268

Name Page Table Name Page Table Name Page Table DLP1D 2-67 32 MXC1 2-65 15 OR4C 2-63 3 DLPIE 2-67 32 MXT 2-65 14 OR4D 2-63 3 FAI 2-66 22 NAND2 2-62 1 OUTBUF 2-65 WW FAIA 2-66 22 NAND2A 2-62 1 REGE8A 2-71 51 FAIB 2-66 22 NAND2B_ 2-62 1 REGE8B 2-71 51 FA2A 2-66 23 NAND3 2-62 2 SMULT8 = 2-73. 67 . FADD12 =2-66 25 NAND3A 2-62 2 SREG4A 2-73 63 FADD16 2-66. 26 NAND3B 2-62 2 SREG8A 2-73 63 FADD24 2-66 27 NAND3C 2-62 2 TA138 2-73 61 FADD32 = 2-67 28 NAND4 2-63 3 TA139 2-72 60 FADD8 2-66 24 NAND4A 2-63. 3 TA151 2-65 18 GAND2 2-71 49 NAND4B (2-63. 3 TA153 2-66 19 GMX4 271 50 NAND4C 2-63 3 TAI57 2-66 20 GNAND2 2-71 49 NAND4D 2-63 3 TA161 2-72 57 GNOR2 271 49 NOR2 2-62 1 TA164 2-73 64 GOR2 2-71 49 NOR2A 2-62 1 TA169 2-72 57 GxXOR2 2-71 49 NOR2B 2-62 1 TA194 2-73 65 HA 2-66 21 NOR3 2-62 2 TA195 2-73 66 HAIA 2-66 21 NOR3A 2-62 2 TA269 2-72 58 HA1B 2-66 21 NOR3B 2-62 2 TA273 2-71 52 HAIC. 2-66 21 NOR3C 2-62 2 TA280 2-72 55 ICMP4 2-71 53 NOR4 2-63 3 TA377 2-71 52 ICMP8 2-71 53 NOR4A 2-63 3 TRIBUFF 2-65 aa INBUF 2-65 n NOR4B 2-63 3 UDCNT4A 2-72 59 INV 2-64 10 NOR4C 2-63 3 xO1 2-63 5 INVA 2-64 10 NOR4D 2-63 3 XO1A 2-63 5 JKF 2-70 45 OA1 2-64 9 XA1 2-63 6 JKFIB 2-70 45 OAIA 2-64 9 XAIA 2-63 6 JKF2A 2-70 45 OA1B 2-64 9 XNOR 2-63 4 JKF2B 2-70 45 OAIC 2-64 9 XOR 2-63 4 JKF2C 2-70 45 OA2 2-64 9 JKF2D 2-70 45 OA2A 2-64 9 JKF3A 2-70 45 OA3 2-64 9 JKF3B 2-70 45 OA3A 2-64 9 JKF3C 2-70 45 OA3B 2-64 9 JKF3D 2-70 45 OA4A 2-64 9 JKF4B 2-70 45 OAS 2-64 9 JKFPC 2-70 45 OAIt 2-64 9 MAJ3. 2-64 8 OAI2A 2-64 9 MCMP16 2-72 54 OAI3 2-64 9 MCMPC2 2-72 54 OAI3A 2-64 9 MCMPC4 2-72 54 OR2 2-62 1 MCMPC8 2-72 54 OR2A 2-62 1 MX16 2-65 7 OR2B 2-62 1 MX2 2-65 12 OR3 2-62 2 MX2A 2-65 12 OR3A 2-62 2 MX2B 2-65 12 OR3B 2-62 2 MxX2C 2-65 12 OR3C 2-62 2 Mx4 2-65 13 OR4 2-63 3 Mx8 2-65 16 OR4A 2-63 3 MX8A 2-65 16 OR4B 2-63 3 ee TEXAS % INSTRUMENTS post of AL So eSuin © DALLAS, Teves Toes 261

Table 1. 2-Input Gates Table 2. 3-Input Gates

Table 3. 4-Input Gates Table 4. XNOR/XOR Gates . Table 5. XOR-OR/KNOR-OR Gates Table 6. XOR-AND/XNOR-AND Gates Table 7. AND-XOR/AND-XNOR Gates

Table 8. AND-OR/AND-NOR Gates Table 9. OR-AND/OR-NAND Gates Table 10. Buffers

Table 11. /O Buffers Table 12. 2:1 Multiplexers. Table 13. 4:1 Multiplexer Table 14. 4:1 Multiplexer Table 15. Other Multiplexer Table 16. 8:1 Multiplexer Table 17. 16:1 Multiplexer Table 18. 8:1 Multiplexer

Table 19. 4:1 Multiplexer Table 20. 2:1 Multiplexer Table 21. Half Adders Table 22. Full Adders Table 23. Full Adder Table 24. 8-Bit Fast Adder Table 25. 12-Bit Fast Adder Table 26. 16-Bit Fast Adder Table 27. 24-Bit Fast Adder

Table 28. 32-Bit Fast Adder Table 29. D-Type Latches Table 30. D-Type Latches with Clear Table 31. D-Type Latch with Clear Table 32. D-Type Latches with Preset Table 33. D-Type Latches with Clear and Preset

Table 34. D-Type Latches with Enable Table 35. D-Type Latches with Enable, Clear, and Preset Table 36. D-Type Latch with Enable Table 37. D-Type Latches with Multiplexed Inputs Table 38. D-Type Latch with Multiplexed Inputs Table 39. D-Type Flip-Flops

Table 40. D-Type Flip-Flops with Clear Table 41. D-Type Flip-Flops with Preset Table 42. D-Type Flip-Flops with Preset and Clear Table 43. D-Type Flip-Flops with Enable

Table 44. D-Type Flip-Flops with Enable, Preset, and Clear Table 45. J-K Flip-Flops Table 46. Multiplexed-input Flip-Flops

Table 47. Multiplexed-Input Flip-Flops with Preset Table 48. Multiplexed-Input Flip-Flops with Preset and Clear Table 49. Clock Buffer (CLKBUF) Interface Table 50. Clock Buffer (CLKBUF) Interface Table 51. Octal D-Type Flip-Flops and Registers Table 52. Octal D-Type Flip-Flops and Registers. Table 53. Identity Comparators

Table 54. Magnitude Comparators Table 55. Parity Checker Table 56. Binary Counters Table 57. Synchronous Counters Table 58. Synchronous Counter Table 60. 2-to-4 Decoders

Table 61. 3-to-8 Decoders Table 62. 4-to-16 Decoder Table 63. Shift Registers Table 64. Shift Register Table 65. Shift Register Table 66. Shift Register Table 67. 8-Bit Multiplier Table 68. Logic Module

Summary

CMOS FIELD-PROGRAMMABLE GATE ARRAYS

Description