TPA6102A2_14 TI1 | Alldatasheet
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C006850-mW Stereo Output /C0068Low Supply Current. . . 0.75 mA /C0068Low Shutdown Current ...5 0 nA /C0068Minimal External Components Required /C0068Gain Set Internally to 14 dB /C0068Pop Reduction Circuitry /C0068Internal Mid-Rail Generation /C0068Thermal and Short-Circuit Protection /C0068Surface-Mount Packaging − MSOP − SOIC /C00681.6-V to 3.6-V Supply Voltage Range
description
The TPA6102A2 is a stereo audio power amplifier packaged in either an 8-pin SOIC package or an 8-pin MOSP package capable of delivering 50 mW of continuous RMS power per channel into 16-Ω loads. Amplifier gain is internally set to 14 dB (inverting) to save board space by eliminating six external resistors. The TPA6102A2 is optimized for battery applications because of its low-supply current, shutdown current, and THD+N. To obtain the low-supply voltage range, the TPA6102A2 biases BYPASS to V DD /4. When driving a 16-Ω load with 40-mW output power from 3.3 V, THD+N is 0.08% at 1 kHz, and less than 0.2% across the audio band of 20 Hz to 20 kHz. For 30 mW into 32-Ω loads, the THD+N is reduced to less than 0.06% at 1 kHz, and is less than 0.3% across the audio band of 20 Hz to 20 kHz. typical application circuit Audio Input Bias Control VO 1 VO 2 VDD IN1− BYPASS SHUTDOWN VDD /4 C I 20 kΩ 100 kΩ C B C S Audio Input C I IN2− VDD From Shutdown Control Circuit C C C C 100 kΩ 20 kΩ 100 kΩ 100 kΩ BYPASS GND SHUTDOWN IN2− IN1− VO 1 VDD VO 2 D or DGK PACKAGE (TOP VIEW) Copyright 2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGED DEVICE MSOPTA SMALL OUTLINE (D) MSOP (DGK) MSOP SYMBOLIZATION −40°C to 85°C TPA6102A2D TPA6102A2DGK AJN Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION BYPASS 1 I Tap to voltage divider for internal mid-supply bias supply. BYPASS is set at VDD /4. Connect to a 0.1-µF to 1-µF low ESR capacitor for best performance. GND 2 I GND is the ground connection. IN1− 8 I IN1− is the inverting input for channel 1. IN2− 4 I IN2− is the inverting input for channel 2. SHUTDOWN 3 I Active-low input. When held low, the device is placed in a low supply current mode. VDD 6 I VDD is the supply voltage terminal. VO 1 7 O VO 1 is the audio output for channel 1. VO 2 5 O VO 2 is the audio output for channel 2. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 710 mW 5.68 mW/°C 454 mW 369 mW DGK 469 mW 3.75 mW/°C 300 mW 244 mW recommended operating conditions MIN MAX UNIT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage, VDD ÁÁÁÁ ÁÁÁÁ 1.6 ÁÁÁÁÁ ÁÁÁÁÁ 3.6 ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage, VIH (SHUTDOWN ) ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 60% x VDD ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Low-level input voltage, VIL (SHUTDOWN ) ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 25% x VDD ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Operating free-air temperature, TA ÁÁÁÁ ÁÁÁÁ −40 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ
/C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dc electrical characteristics at TA = 25°C, VDD = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOO Output offset voltage AV = 14 dB 5 40 mV PSRR Power supply rejection ratio VDD = 3 V to 3.6 V 72 dB IDD Supply current SHUTDOWN = 3.6 V 0.75 1.5 mA IDD(SD) Supply current in SHUTDOWN mode SHUTDOWN = 0 V 50 250 nA |IIH| High-level input current (SHUTDOWN) VDD = 3.6 V, VI= VDD 1 µA |IIL| Low-level input current (SHUTDOWN) VDD = 3.6 V, VI= 0 V 1 µA ZI Input impedance 20 kΩ ac operating characteristics, VDD = 3.3 V, TA = 25°C, RL = 16 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 14 dB PO Output power (each channel) THD ≤ 0.1%, f = 1 kHz 50 mW THD+N Total harmonic distortion + noise PO = 45 mW, 20−20 kHz 0.4% BOM Maximum output power BW THD < 0.5% > 20 kHz kSVR Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 50 mW 86 dB Vn Noise output voltage (no noise weighting filter) 45 µV(rms) ac operating characteristics, VDD = 3.3 V, TA = 25°C, RL = 32 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 14 dB PO Output power (each channel) THD ≤ 0.1%, f = 1 kHz 35 mW THD+N Total harmonic distortion + noise PO = 30 mW, 20−20 kHz 0.4% BOM Maximum output power BW THD < 0.4% >20 kHz kSVR Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 30 mW 86 dB Vn Noise output voltage (no noise weighting filter) 50 µV(rms)
/C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
dc electrical characteristics at TA = 25°C, VDD = 1.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOO Output offset voltage AV = 14 dB 5 40 mV PSRR Power supply rejection ratio VDD = 1.4 V to 1.8 V 80 dB IDD Supply current SHUTDOWN = 1.6 V 0.65 1.2 mA IDD(SD) Supply current in SHUTDOWN mode SHUTDOWN = 0 V 50 250 nA |IIH| High-level input current (SHUTDOWN) VDD = 1.6 V, VI = VDD 1 µA |IIL| Low-level input current (SHUTDOWN) VDD = 1.6 V, VI = 0 V 1 µA ZI Input impedance 20 kΩ ac operating characteristics, VDD = 1.6 V, TA = 25°C, RL = 16 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 14 dB PO Output power (each channel) THD ≤ 0.5%, f = 1 kHz 10 mW THD+N Total harmonic distortion + noise PO = 9.5 mW, 20−20 kHz 0.06% BOM Maximum output power BW THD < 1% > 20 kHz kSVR Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 10 mW 82 dB Vn Noise output voltage (no noise weighting filter) 32 µV(rms) ac operating characteristics, VDD = 1.6 V, TA = 25°C, RL = 32 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 14 dB PO Output power (each channel) THD ≤ 0.5%, f = 1 kHz 7.5 mW THD+N Total harmonic distortion + noise PO = 6.5 mW, 20−20 kHz 0.05% BOM Maximum output power BW THD < 1% >20 kHz kSVR Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 7.5 mW 84 dB Vn Noise output voltage (no noise weighting filter) 32 µV(rms) TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Frequency 1, 3, 5, 7, 9, 11 THD+N Total harmonic distortion plus noise vs Output power 2, 4, 6, 8, 10, 12THD+N Total harmonic distortion plus noise vs Output voltage 13, 14 PO Output power vs Load resistance 15, 16 kSVR Supply ripple rejection ratio vs Frequency 17, 18 Vn Output noise voltage vs Frequency 19, 20 Crosstalk vs Frequency 21, 22 Closed−loop gain and phase vs Frequency 23, 24, 25, 26 IDD Supply current vs Supply voltage 27 PD Power dissipation vs Output power 28
/C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.0001 0.001 0.01 0.1 20 20 k 100 1 k THD+N − Total Harmonic Distortion Plus Noise − % f − Frequency − Hz TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY VDD = 1.6 V PO = 4.5 mW C B = 1 µF R L = 50 Ω Figure 6 0.001 0.01 0.1 1 100 10 THD+N − Total Harmonic Distortion Plus Noise − % VDD = 1.6 V C B = 1 µF R L = 50 Ω f = 1 kHz TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER PO − Output Power − mW Figure 7 0.0001 0.001 0.01 0.1 20 20 k 100 1 k 10 k THD+N − Total Harmonic Distortion Plus Noise − % f − Frequency − Hz TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY VDD = 3.3 V PO = 45 mW C B = 1 µF R L = 16 Ω Figure 8 0.0001 0.001 0.01 0.1 20 20 k 100 1 k 10 k THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V C B = 1 µF R L = 16 Ω f = 1 kHz TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER PO − Output Power − mW
/C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.001 0.01 0.1 THD+N − Total Harmonic Distortion Plus Noise − % VDD = 1.6 V R L = 10 kΩ Frequency = 20 Hz TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT VOLTAGE VO − Output Voltage − V Figure 14 0.001 0.01 0.1 THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V R L = 10 kΩ Frequency = 20 Hz TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT VOLTAGE VO − Output Voltage − V Figure 15 16 20 24 28 32 36 40 44 48 50 − Output Power − mW OUTPUT POWER vs LOAD RESISTANCE PO VDD = 1.6 V THD+N = 1% Mode = Stereo R L − Load Resistance − Ω Figure 16 100 125 150 16 20 24 28 32 36 40 44 48 50 − Output Power − mW OUTPUT POWER vs LOAD RESISTANCE PO VDD = 3.6 V THD+N = 1% Mode = Stereo R L − Load Resistance − Ω
/C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
−140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 20 20 k 100 1 k 10 k Crosstalk − dB f − Frequency − Hz CROSSTALK vs FREQUENCY VDD = 1.6 V PO = 4.5 mW R L = 50 Ω Figure 22 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 20 20 k 100 1 k 10 k Crosstalk − dB f − Frequency − Hz CROSSTALK vs FREQUENCY VDD = 3.3 V PO = 20 mW R L = 50 Ω −60 −50 −40 −30 −20 −10 10 100 1 k 10 k 100 k 1 M 10 M 100 M Phase Gain VDD = 1.6 V R L = 16 Ω TA = 25°C Closed-Loop Gain − dB f − Frequency − Hz CLOSED-LOOP GAIN AND PHASE vs FREQUENCY Phase Figure 23 180° −180° 60° −60° 150° 120° 30° −30° −120° −150° −90° 90°
/C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
−60 −50 −40 −30 −20 −10 10 100 1 k 10 k 100 k 1 M 10 M 100 M Phase Gain VDD = 3.3 V R L = 32 Ω TA = 25°C Closed-Loop Gain − dB f − Frequency − Hz CLOSED-LOOP GAIN AND PHASE vs FREQUENCY Phase Figure 26 180° −180° 60° −60° 150° 120° 30° −30° −120° −150° −90° 90° Figure 27 −0.2 0.2 0.4 0.6 0.8 − Supply Current − mA SUPPLY CURRENT vs SUPPLY VOLTAGE IDD VDD − Supply Voltage − V VDD Low-to-High Figure 28 01 02 0 4 0 − Power Dissipation − mW POWER DISSIPATION vs OUTPUT POWER 50 7030 60 PO − Output Power − mW PD VDD = 3.3 V
/C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input capacitor, CI In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, CI and RI form a high-pass filter with the corner frequency determined in equation 1. RI is set internally and is fixed at 20 kΩ. (1)fc /C00431 2/C0112R IC I The value of CI is important to consider, as it directly affects the bass (low frequency) performance of the circuit. Consider the example where the specification calls for a flat bass response down to 20 Hz. Equation 1 is reconfigured as equation 2. (2)C I /C00431 2/C0112R Ifc In this example, CI is 0.40 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. A further consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and the feedback resistor (RF) to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at V DD /4, which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application. power supply decoupling, CS The TPA6102A2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF, placed as close as possible to the device V DD lead, works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the power amplifier is recommended. midrail bypass capacitor, CB The midrail bypass capacitor (CB) serves several important functions. During start-up, CB determines the rate at which the amplifier starts up. This helps to push the start-up pop noise into the subaudible range (so low it can not be heard). The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier. The capacitor is fed from a 55-kΩ source inside the amplifier. To keep the start-up pop as low as possible, the relationship shown in equation 3 should be maintained. (3) /C0466C B /C003255 kΩ/C0467 /C01181 /C0466C IR I/C0467 As an example, consider a circuit where CB is 1 µF, CI is 1 µF, and RI is 20 kΩ. Inserting these values into the equation 3 results in: 18.18 ≤ 50 which satisfies the rule. Bypass capacitor (CB) with values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance.
/C0084/C0080/C0065/C0054/C0049/C0048/C0050/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS324B − JUNE 2000 − REVISED SEPTEMBER 2004
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
output coupling capacitor, CC In the typical single-supply single-ended (SE) configuration, an output coupling capacitor (CC ) is required to block the dc bias at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation 4. (4)f c /C00431 2/C0112R LC C The main disadvantage, from a performance standpoint, is that the typically small load impedances drive the low-frequency corner higher. Large values of CC are required to pass low-frequencies into the load. Consider the example where a CC of 68 µF is chosen and loads vary from 32 Ω to 47 kΩ. Table 1 summarizes the frequency response characteristics of each configuration. Table 1. Common-Load Impedances vs Low-Frequency Output Characteristics in SE Mode behaves like an ideal capacitor. swing effectively reduces the maximum undistorted output power.
www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPA6102A2D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 6102A2 TPA6102A2DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 6102A2 TPA6102A2DGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AJN TPA6102A2DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AJN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
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*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA6102A2DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 2
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