TPA6101A2DGKR.A

TPA6101A2 TI | Alldatasheet

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Technical content

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 SLOS331C − AUGUST 2000 − REVISED MARCH 2007 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Minimal External Components Required /C00681.6-V to 3.6-V Supply Voltage Range /C006850-mW Stereo Output /C0068Low Supply Current. . . 0.75 mA /C0068Low Shutdown Current ...5 0 nA /C0068Gain Set Internally to 2 dB /C0068Pop Reduction Circuitry /C0068Internal Mid-Rail Generation /C0068Thermal and Short-Circuit Protection /C0068Surface-Mount Packaging − 3-mm /C0121 5-mm MSOP Package (DGN) − 5-mm /C0121 6-mm SOIC Package (D) − 2,5-mm /C0121 2,5-mm MicroStar Junior/C0069 BGA Package (ZQY)

description

The TPA6101A2 is a stereo audio power amplifier packaged in an 8-pin SOIC package, an 8-pin MSOP package, or a 15-ball BGA package, capable of delivering 50 mW of continuous RMS power per channel into 16-Ω loads. Amplifier gain is internally set to 2 dB (inverting) to save board space by eliminating six external resistors. The TPA6101A2 is optimized for battery applications because of its low supply current, shutdown current, and THD+N. To obtain the low-supply-voltage range, the TPA6101A2 biases BYPASS to V DD /4. When driving a 16-Ω load with 40-mW output power from 3.3 V, THD+N is 0.08% at 1 kHz, and less than 0.2% across the audio band of 20 Hz to 20 kHz. For 30 mW into 32-Ω loads, the THD+N is reduced to less than 0.06% at 1 kHz, and is less than 0.3% across the audio band of 20 Hz to 20 kHz. typical application circuit Audio Input Bias Control VO 1 VO 2 VDD IN1− BYPASS SHUTDOWN VDD /4 C I 80 kΩ R F 80 kΩ C B C S Audio Input C I IN2− VDD From Shutdown Control Circuit C C C C80 kΩ R I 80 kΩ R F 80 kΩNOTE: All internal resistor values are ±20%. 80 kΩ RI MicroStar BGA is a trademark of Texas Instruments. Copyright  2007, Texas Instruments Incorporated BYPASS GND SHUTDOWN IN2− IN1− VO 1 VDD VO 2 D or DGK PACKAGE (TOP VIEW) /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 IN2− IN1− GND BYPASS VO 1 GND (A1) VDDSHUTDOWN VO 2 ZQY PACKAGE (TOP VIEW) (B1) (C1) (D1) (A4) (B4) (C4) (D4)

/C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGED DEVICE MSOP BGATA SMALL OUTLINE (D) MSOP (DGK) BGA (ZQY) MSOP SYMBOLIZATION BGA SYMBOLIZATION −40°C to 85°C TPA6101A2D TPA6101A2DGK TPA6101A2ZQYR AJM AAQI Terminal Functions TERMINAL NO. I/O DESCRIPTION NAME D, DGK ZQY I/O DESCRIPTION BYPASS 1 A1 I Tap to voltage divider for internal mid-supply bias supply. BYPASS is set at VDD /4. Connect to a 0.1-µF to 1-µF low-ESR capacitor for best performance. GND 2 B1 – GND is the ground connection. IN1− 8 A4 I IN1− is the inverting input for channel 1. IN2− 4 D1 I IN2− is the inverting input for channel 2. SHUTDOWN 3 C1 I Active-low input. When held low, the device is placed in a low-supply-current mode. VDD 6 C4 – VDD is the supply voltage terminal. VO 1 7 B4 O VO 1 is the audio output for channel 1. VO 2 5 D4 O VO 2 is the audio output for channel 2. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 710 mW 5.68 mW/°C 454 mW 369 mW DGK 469 mW 3.75 mW/°C 300 mW 244 mW ZQY 2 W 17.1 mW/°C 1.28 W 1.04 W recommended operating conditions MIN MAX UNIT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage, VDD ÁÁÁÁÁ ÁÁÁÁÁ 1.6 ÁÁÁÁÁ ÁÁÁÁÁ 3.6 ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage, VIH (SHUTDOWN ) ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

0.6 VDD

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Low-level input voltage, VIL (SHUTDOWN ) ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

0.25 VDD

ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Operating free-air temperature, TA ÁÁÁÁÁ ÁÁÁÁÁ –40 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ

/C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dc electrical characteristics at TA = 25°C, VDD = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOO Output offset voltage AV = 2 dB 5 40 mV PSRR Power supply rejection ratio VDD = 3 V to 3.6 V 72 dB IDD Supply current SHUTDOWN = 3.6 V 0.75 1.5 mA IDD(SD) Supply current in SHUTDOWN mode SHUTDOWN = 0 V 50 250 nA |IIH| High-level input current (SHUTDOWN) VDD = 3.6 V, VI = VDD 1 µA |IIL| Low-level input current (SHUTDOWN) VDD = 3.6 V, VI = 0 V 1 µA ZI Input impedance 80 kΩ ac operating characteristics, VDD = 3.3 V, TA = 25°C, RL = 16 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 2 dB PO Output power (each channel) THD ≤ 0.1%, f = 1 kHz 50 mW THD+N Total harmonic distortion + noise PO = 45 mW, 20 Hz−20 kHz 0.4% BOM Maximum output power BW THD < 0.5% > 20 kHz kSVR Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 50 mW 86 dB Vn Noise output voltage (no-noise weighting filter) 45 µV(rms) ac operating characteristics, VDD = 3.3 V, TA = 25°C, RL = 32 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 2 dB PO Output power (each channel) THD ≤ 0.1%, f = 1 kHz 35 mW THD+N Total harmonic distortion + noise PO = 30 mW, 20 Hz−20 kHz 0.4% BOM Maximum output power BW THD < 0.4% >20 kHz kSVR Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 30 mW 86 dB Vn Noise output voltage (no-noise weighting filter) 50 µV(rms)

/C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

dc electrical characteristics at TA = 25°C, VDD = 1.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOO Output offset voltage AV = 2 dB 5 40 mV PSRR Power supply rejection ratio VDD = 1.4 V to 1.8 V 80 dB IDD Supply current SHUTDOWN = 1.6 V 0.65 1.2 mA IDD(SD) Supply current in SHUTDOWN mode SHUTDOWN = 0 V 50 250 nA |IIH| High-level input current (SHUTDOWN) VDD = 1.6 V, VI = VDD 1 µA |IIL| Low-level input current (SHUTDOWN) VDD = 1.6 V, VI = 0 V 1 µA ZI Input impedance 80 kΩ ac operating characteristics, VDD = 1.6 V, TA = 25°C, RL = 16 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 2 dB PO Output power (each channel) THD ≤ 0.5%, f = 1 kHz 10 mW THD+N Total harmonic distortion + noise PO = 9.5 mW, 20 Hz−20 kHz 0.06% BOM Maximum output power BW THD < 1% > 20 kHz kSVR Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 10 mW 82 dB Vn Noise output voltage (no-noise weighting filter) 32 µV(rms) ac operating characteristics, VDD = 1.6 V, TA = 25°C, RL = 32 Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Gain 2 dB PO Output power (each channel) THD ≤ 0.5%, f = 1 kHz 7.5 mW THD+N Total harmonic distortion + noise PO = 6.5 mW, 20 Hz−20 kHz 0.05% BOM Maximum output power BW THD < 1% >20 kHz kSVR Supply ripple rejection ratio f = 1 kHz 47 dB SNR Signal-to-noise ratio PO = 7.5 mW 84 dB Vn Noise output voltage (no-noise weighting filter) 32 µV(rms) TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Frequency 1, 3, 5, 7, 9, 11 THD+N Total harmonic distortion plus noise vs Output power 2, 4, 6, 8, 10, 12THD+N Total harmonic distortion plus noise vs Output voltage 13, 14 PO Output power vs Load resistance 15, 16 kSVR Supply ripple rejection ratio vs Frequency 17, 18 Vn Output noise voltage vs Frequency 19, 20 Crosstalk vs Frequency 21, 22 Closed−loop gain and phase vs Frequency 23, 24, 25, 26 IDD Supply current vs Supply voltage 27 PD Power dissipation vs Output power 28

/C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.001 0.01 0.1 20 20 k 100 1 k 10 k THD+N − Total Harmonic Distortion Plus Noise − % f − Frequency − Hz TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY VDD = 1.6 V PO = 4.5 mW C B = 1 µF R L = 50 Ω Figure 5 0.001 0.01 0.1 14 0 51 0 THD+N − Total Harmonic Distortion Plus Noise − % VDD = 1.6 V C B = 1 µF R L = 50 Ω f = 1 kHz TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER PO − Output Power − mW Figure 6 0.001 0.01 0.1 Figure 7 20 20 k 100 1 k 10 k THD+N − Total Harmonic Distortion Plus Noise − % f − Frequency − Hz TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY VDD = 3.3 V PO = 45 mW C B = 1 µF R L = 16 Ω Figure 8 0.001 0.01 0.1 1 200 10 100 THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V C B = 1 µF R L = 16 Ω f = 1 kHz TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT POWER PO − Output Power − mW

/C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.001 0.01 0.1 01 0.1 0.5 THD+N − Total Harmonic Distortion Plus Noise − % VDD = 1.6 V R L = 10 kΩ C B = 1 µF TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT VOLTAGE VO − Output Voltage − V Figure 14 0.001 0.01 0.1 THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V R L = 10 kΩ C B = 1 µF TOTAL HARMONIC DISTORTION PLUS NOISE vs OUTPUT VOLTAGE VO − Output Voltage − V Figure 15 16 20 24 28 32 36 40 44 48 50 Channel 1 Channel 2 − Output Power − mW OUTPUT POWER vs LOAD RESISTANCE PO R L − Load Resistance − Ω VDD = 1.6 V THD+N = 1% Mode = Stereo Figure 16 100 125 150 16 20 24 28 32 36 40 44 48 50 Channel 1 Channel 2 − Output Power − mW OUTPUT POWER vs LOAD RESISTANCE PO R L − Load Resistance − Ω VDD = 3.6 V THD+N = 1% Mode = Stereo

/C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

−140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 20 20 k 100 1 k 10 k Crosstalk − dB f − Frequency − Hz CROSSTALK vs FREQUENCY VDD = 1.6 V PO = 4.5 mW R L = 50 Ω Figure 22 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 20 20 k 100 1 k 10 k Crosstalk − dB f − Frequency − Hz CROSSTALK vs FREQUENCY VDD = 3.3 V PO = 20 mW R L = 50 Ω −60 −50 −40 −30 −20 −10 10 100 1 k 10 k 100 k 1 M 10 M 100 M Phase Gain VDD = 1.6 V R L = 16 Ω TA = 25°C Closed-Loop Gain − dB f − Frequency − Hz CLOSED-LOOP GAIN AND PHASE vs FREQUENCY Phase Figure 23 180° −180° 60° −60° 150° 120° 30° −30° −120° −150° −90° 90°

/C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

−60 −50 −40 −30 −20 −10 10 100 1 k 10 k 100 k 1 M 10 M 100 M Phase Gain VDD = 3.3 V R L = 32 Ω TA = 25°C Closed-Loop Gain − dB f − Frequency − Hz CLOSED-LOOP GAIN AND PHASE vs FREQUENCY Phase Figure 26 180° −180° 60° −60° 150° 120° 30° −30° −120° −150° −90° 90° Figure 27 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 TA = 125°C TA = 25°C TA = −40°C − Supply Current − mA SUPPLY CURRENT vs SUPPLY VOLTAGE IDD VDD − Supply Voltage − V VDD Low-to-High TA = 25°C Figure 28 16 Ω 32 Ω 50 Ω 01 02 03 0 − Power Dissipation − mW POWER DISSIPATION vs OUTPUT POWER 40 50 60 70 PO − Output Power − mW PD VDD = 3.3 V

/C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input capacitor, CI In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, CI and RI form a high-pass filter with the corner frequency determined in equation 1. RI is set internally and is fixed at 80 kΩ. (1)fc /C00431 2/C0112R IC I The value of CI is important to consider, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where the specification calls for a flat bass response down to 20 Hz. Equation 1 is reconfigured as equation 2. (2)C I /C00431 2/C0112R Ifc In this example, CI is approximately 0.1 µF. A further consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and the feedback resistor (RF) to the load. This leakage current creates a dc-offset voltage at the input to the amplifier that reduces useful headroom. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at V DD /4, which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application. power supply decoupling, CS The TPA6101A2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF, placed as close as possible to the device V DD lead, works best. For filtering lower-frequency noise signals, a larger, aluminum electrolytic capacitor of 10 µF or greater placed near the power amplifier is recommended. midrail bypass capacitor, CB The midrail bypass capacitor (CB) serves several important functions. During start-up, CB determines the rate at which the amplifier starts up. This helps to push the start-up pop noise into the subaudible range (so low it can not be heard). The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier. The capacitor is fed from a 55-kΩ source inside the amplifier. To keep the start-up pop as low as possible, the relationship shown in Euation 3 should be maintained. (3) /C0466C B /C003255 kΩ/C0467 /C01181 /C0466C IR I/C0467 As an example, consider a circuit where CB is 1 µF, CI is 0.1 µF, and RI is 80 kΩ. Inserting these values into Euation 3 results in: 18.18 ≤ 125 which satisfies the rule. Bypass capacitor (CB) values of 0.47 µF to 1 µF and ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance.

/C0084/C0080/C0065/C0054/C0049/C0048/C0049/C0065/C0050 /C0053/C0048/C0262/C0109/C0087 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0044 /C0070/C0073/C0088/C0069/C0068/C0262/C0071/C0065/C0073/C0078 /C0083/C0084/C0069/C0082/C0069/C0079 /C0072/C0069/C0065/C0068/C0080/C0072/C0079/C0078/C0069 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

output coupling capacitor, CC In the typical single-supply, single-ended (SE) configuration, an output coupling capacitor (CC ) is required to block the dc bias at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load from a high-pass filter is governed by Equation 4. (4)f c /C00431 2/C0112R LC C The main disadvantage, from a performance standpoint, is that the typically small load impedances drive the low-frequency corner higher. Large values of CC are required to pass low-frequencies into the load. Consider the example where a CC of 68 µF is chosen and loads vary from 32 Ω to 47 kΩ. Table 1 summarizes the frequency response characteristics of each configuration. Table 1. Common Load Impedances vs Low-Frequency Output Characteristics in SE Mode behaves like an ideal capacitor. swing effectively reduces the maximum undistorted output power.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPA6101A2D Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 6101A2 TPA6101A2D.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 6101A2 TPA6101A2DGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AJM TPA6101A2DGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AJM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA6101A2DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPA6101A2D D SOIC 8 75 505.46 6.76 3810 4 TPA6101A2D.A D SOIC 8 75 505.46 6.76 3810 4 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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