TPA6100A2DGKRG4

TPA6100A2 TI | Alldatasheet

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FEATURES

IN2± IN1± V VDD VO2 DGK PACKAGE (TOP VIEW) BYPASS GND SHUTDOWN IN2± IN1± V VDD VO2 D PACKAGE (TOP VIEW)

DESCRIPTION

V VO2 VDD IN1− BYPASS SHUTDOWN VDD/4 CI RI RF CB CS Audio Input CI RI IN2− RF VDD From Shutdown Control Circuit CC CC R R TPA6100A2D SLOS269B JUNE 2000 REVISED SEPTEMBER 2004 50-mW ULTRALOW VOLTAGE STEREO HEADPHONE AUDIO POWER AMPLIFIER 50-mW Stereo Output Low Supply Current 0.75 mA Low Shutdown Current nA Pin Compatible With LM4881 and TPA102 (1) Pop Reduction Circuitry Internal Midrail Generation Thermal and Short-Circuit Protection Surface-Mount Packaging MSOP and SOIC 1.6-V to 3.6-V Supply Voltage Range (1) The polarity of the SHUTDOWN pin is reversed. The TPA6100A2D is a stereo audio power amplifier packaged in either an 8-pin SOIC package or an 8-pin MSOP package capable of delivering mW of continuous RMS power per channel into 16- Ω loads. Amplifier gain is externally configured by a means of three resistors per input channel and does not require external compensation for settings of to 10. The TPA6100A2D is optimized for battery

applications

current, shutdown current, and THD+N. To obtain the low-supply voltage range, the TPA6100A2D biases BYPASS to V DD /4. A resistor with a resistance equal to R F must be added from the inputs to ground to allow the output to be biased at V DD /2. When driving a 16- Ω load with 45-mW output power from 3.3 THD+N is 0.04% at kHz, and less than 0.2% across the audio band of Hz to kHz. For mW into 32- Ω loads, the THD+N is reduced to less than 0.03% at kHz, and is less than 0.2% across the audio band of Hz to kHz. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2000 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS DISSIPATION RATING TABLE RECOMMENDED OPERATING CONDITIONS TPA6100A2D SLOS269B JUNE 2000 REVISED SEPTEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGED DEVICE MSOP T A SYMBOLIZATION SMALL OUTLINE (D) MSOP (DGK) C to C TPA6100A2D TPA6100A2DGK AJL Terminal Functions TERMINAL I/O NO. BYPASS I Tap to voltage divider for internal mid-supply bias supply. BYPASS is set at V DD /4. Connect to a 0.1- µ F to µ F low-ESR capacitor for best performance. GND I GND is the ground connection. IN1- I IN1- is the inverting input for channel IN2- I IN2- is the inverting input for channel SHUTDOWN I Active-low input. When held low, the device is placed in a low supply current mode. V DD I V DD is the supply voltage terminal. V O O V O is the audio output for channel V O O V O is the audio output for channel over operating free-air temperature range (unless otherwise noted) (1) UNIT V DD Supply voltage V V I Input voltage 0.3 V to V DD 0.3 V Continuous total power dissipation Internally limited T J Operating junction temperature range C to 150 C T stg Storage temperature range C to 150 C Lead temperature 1,6 mm (1/16 inch) from case for seconds 260 C (1) Stresses beyond thoselisted under "absolute maximum ratings may cause permanent damage to thedevice. These are stress ratings only, and functional operation of the deviceat these or any other conditions beyond those indicated under "recommendedoperating conditions is not implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect devicereliability. T A C DERATING FACTOR T A C T A C PACKAGE POWER RATING ABOVE T A C POWER RATING POWER RATING D 710 mW 5.68 mW/ C 454 mW 369 mW DGK 469 mW 3.75 mW/ C 300 mW 244 mW MIN MAX UNIT V DD Supply voltage 1.6 3.6 V T A Operating free-air temperature C V IH High-level input voltage SHUTDOWN 0.6 x V DD V V IL Low-level input voltage SHUTDOWN 0.25 x V DD

www.ti.com DC ELECTRICAL CHARACTERISTICS AC OPERATING CHARACTERISTICS AC OPERATING CHARACTERISTICS TPA6100A2D SLOS269B JUNE 2000 REVISED SEPTEMBER 2004 at T A V DD 3.6 V (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OO Output offset voltage A V V/V mV PSRR Power supply rejection ratio V DD 3.0 V to 3.6 V dB I DD Supply current SHUTDOWN 3.6 V 0.75 2.0 mA I DD(SD) Supply current in SHUTDOWN mode SHUTDOWN V 250 nA IH High-level input current SHUTDOWN V DD 3.6 V I V DD µ A IL Low-level input current SHUTDOWN V DD 3.6 V I V µ A Z I Input impedance (IN1-, IN2-) M Ω V DD 3.3 T A R L Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT P O Output power (each channel) THD 0.1%, f kHz mW THD+N Total harmonic distortion noise P O mW, Hz kHz 0.2% B OM Maximum output power BW G THD 0.5% kHz k SVR Supply ripple rejection f kHz dB SNR Signal-to-noise ratio P O mW dB V n Noise output voltage (no noise-weighting filter) µ V(rms) V DD 3.3 T A R L Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT P O Output power (each channel) THD 0.1%, f kHz mW THD+N Total harmonic distortion noise P O mW, Hz kHz 0.2% B OM Maximum output power BW G THD 0.2% kHz k SVR Supply ripple rejection f kHz dB SNR Signal-to-noise ratio P O mW dB V n Noise output voltage (no noise-weighting filter) µ V(rms)

www.ti.com DC ELECTRICAL CHARACTERISTICS AC OPERATING CHARACTERISTICS AC OPERATING CHARACTERISTICS TPA6100A2D SLOS269B JUNE 2000 REVISED SEPTEMBER 2004 at T A V DD 1.6 V (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OO Output offset voltage A V V/V mV PSRR Power supply rejection ratio V DD 1.5 V to 1.7 V dB I DD Supply current SHUTDOWN 1.6 V 1.2 1.5 mA I DD(SD) Supply current in SHUTDOWN mode SHUTDOWN V 250 nA IH High-level input current SHUTDOWN V DD 1.6 V I V DD µ A IL Low-level input current SHUTDOWN V DD 1.6 V I V µ A Z I Input impedance (IN1-, IN2-) M Ω V DD 1.6 T A R L Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT P O Output power (each channel) THD 0.1%, f kHz 9.5 mW THD+N Total harmonic distortion noise P O 9.5 mW, Hz kHz 0.4% B OM Maximum output power BW G dB, THD 0.4% kHz k SVR Supply ripple rejection f kHz dB SNR Signal-to-noise ratio P O 9.5 mW dB V n Noise output voltage (no noise-weighting filter) µ V(rms) V DD 1.6 T A R L Ω PARAMETER TEST CONDITIONS MIN TYP MAX UNIT P O Output power (each channel) THD 0.1%, f kHz 7.1 mW THD+N Total harmonic distortion noise P O 6.5 mW, Hz kHz 0.3% B OM Maximum output power BW G dB, THD 0.3% kHz k SVR Supply ripple rejection f kHz dB SNR Signal-to-noise ratio P O 7.1 mW dB V n Noise output voltage (no noise-weighting filter) µ V(rms)

www.ti.com APPLICATION INFORMATION GAIN SETTING RESISTORS, R F R and R Gain RF RI or Gain (dB) 20 log RF RI (1) Effective Impedance RFRI RF RI (2) fc 1 2RFCF (3) INPUT CAPACITOR, C I fc 1 2RICI (4) CI 1 2RIfc (5) TPA6100A2D SLOS269B JUNE 2000 REVISED SEPTEMBER 2004 The voltage gain for the TPA6100A2D is set by resistors R F and R I according to Equation Given that the TPA6100A2D is an MOS amplifier, the input impedance is high. Consequently, input leakage currents are not generally a concern, although noise in the circuit increases as the value of R F increases. In addition, a certain range of R F values is required for proper start-up operation of the amplifier. Taken together, it is recommended that the effective impedance seen by the inverting node of the amplifier be set between k Ω and k Ω The effective impedance is calculated in Equation As an example, consider an input resistance of k Ω and a feedback resistor of k Ω The gain of the amplifier would be and the effective impedance at the inverting terminal would be k Ω which is within the recommended range. For high-performance applications, metal film resistors are recommended because they tend to have lower noise levels than carbon resistors. For values of R F above k Ω the amplifier tends to become unstable due to a pole formed from R F and the inherent input capacitance of the MOS input structure. For this reason, a small compensation capacitor of approximately pF should be placed in parallel with R F In effect, this creates a low-pass filter network with the cutoff frequency defined in Equation For example, if R F is 100 k Ω and C F is pF, then f c is 318 kHz, which is well outside the audio range. For maximum signal swing and output power at low supply voltages like 1.6 V to 3.3 BYPASS is biased to V DD /4. However, to allow the output to be biased at V DD /2, a resistor, equal to R F must be placed from the negative input to ground. In the typical application, an input capacitor, C I is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, C I and R I form a high-pass filter with the corner frequency determined in Equation The value of C I is important to consider, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where R I is k Ω and the specification calls for a flat bass response down to Hz. Equation is reconfigured as Equation In this example, C I is 0.4 µ so one would likely choose a value in the range of 0.47 µ F to µ A further consideration for this capacitor is the leakage path from the input source through the input network I C I and the feedback resistor F to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high-gain

10). For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at V DD /4, which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application.

www.ti.com POWER SUPPLY DECOUPLING, C S MIDRAIL BYPASS CAPACITOR, C B CB 55 kΩ CIRI (6) OUTPUT COUPLING CAPACITOR, C C fc 1 2RLCC (7) TPA6100A2D SLOS269B JUNE 2000 REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) The TPA6100A2D is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µ placed as close as possible to the device V DD lead, works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of µ F or greater placed near the power amplifier is recommended. The midrail bypass capacitor B serves several important functions. During start-up, C B determines the rate at which the amplifier starts up. This helps to push the start-up pop noise into the subaudible range (so low it can not be heard). The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier. The capacitor is fed from a 55-k Ω source inside the amplifier. To keep the start-up pop as low as possible, the relationship shown in Equation should be maintained. As an example, consider a circuit where C B is µ C I is µ and R I is k Ω Inserting these values into Equation results in: 18.18 which satisfies the rule. Bypass capacitor B values of 0.47- µ F to µ F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. In the typical single-supply, single-ended (SE) configuration, an output coupling capacitor C is required to block the dc bias at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by Equation The main disadvantage, from a performance standpoint, is that the typically small load impedances drive the low-frequency corner higher. Large values of C C are required to pass low frequencies into the load. Consider the example where a C C of µ F is chosen and loads vary from Ω to k Ω Table summarizes the frequency response characteristics of each configuration. Table Common Load Impedances vs Low Frequency Output Characteristics in SE Mode R L C C LOWEST FREQUENCY Ω µ F Hz 10,000 Ω µ F 0.23 Hz 47,000 Ω µ F 0.05 Hz As Table indicates, headphone response is adequate and drive into line level inputs home stereo for example) is good. The output coupling capacitor required in single-supply, SE mode also places additional constraints on the selection of other components in the amplifier circuit. With the rules described earlier still valid, add the following relationship:

www.ti.com CB 55 kΩ CIRI RLCC (8) USING LOW-ESR CAPACITORS 3.3-V VERSUS 1.6-V OPERATION TPA6100A2D SLOS269B JUNE 2000 REVISED SEPTEMBER 2004 Low-ESR capacitors are recommended throughout this application. A real capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. The TPA6100A2D was designed for operation over a supply range of 1.6 V to 3.6 There are no special considerations for 1.6-V versus 3.3-V operation as far as supply bypassing, gain setting, or stability. The most important consideration is that of output power. Each amplifier can produce a maxium output voltage swing within a few hundred millivolts of the rails with a 10-k Ω load. However, this voltage swing decreases as the load resistance decreases and the r DS(on) as the output stage transistors becomes more significant. For example, for a 32- Ω load, the maximum peak output voltage with V DD 1.6 V is approximately 0.7 V with no clipping distortion. This reduced voltage swing effectively reduces the maximum undistorted output power.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPA6100A2D Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 6100A2 TPA6100A2D.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 6100A2 TPA6100A2DGK Active Production VSSOP (DGK) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AJL TPA6100A2DGK.A Active Production VSSOP (DGK) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AJL TPA6100A2DGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AJL TPA6100A2DGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AJL TPA6100A2DGKRG4 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 AJL TPA6100A2DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 6100A2 TPA6100A2DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 6100A2 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 23-May-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA6100A2DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TPA6100A2DR SOIC D 8 2500 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPA6100A2D D SOIC 8 75 505.46 6.76 3810 4 TPA6100A2D.A D SOIC 8 75 505.46 6.76 3810 4 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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