TPA6021A4N

TPA6021A4 TI | Alldatasheet

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-90 -80 -70 -60 -50 -40 -30 -20 -10 Volume [Pin 18] - V DC VOLUME CONTROL Volume - dB BTL Volume PGND ROUT- PV DD RIN+ RIN- V DD LIN- LIN+ PV DD LOUT- ROUT+ SE/BTL VOLUME AGND NC BYPASS FADE SHUTDOWN LOUT+ PGND 10 11 Ci VDD VDD Right Positive Differential Input Signal Left Negative Differential Input Signal Right Negative Differential Input Signal Left Positive Differential Input Signal Ci C C i i Power Supply Power Supply VDD 100 kW 100 kW C 330 F O m C 330 F O m 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm C 10 F S m C 0.47 F (BYP) m In From DAC or Potentiometer (DC Voltage) System Control Right Speaker Left Speaker Headphones 1 kW 1 kW TPA6021A4 SLOS465 JUNE 2005 2-W STEREO AUDIO POWER AMPLIFIER WITH ADVANCED DC VOLUME CONTROL W Into Ω Speakers With External Heatsink The TPA6021A4 is a stereo audio power amplifier that drives W/channel of continuous RMS power DC Volume Control With 2-dB into a Ω load when utilizing a heat sink. Advanced Steps from -40 dB to dB dc volume control minimizes external components Fade Mode and allows BTL (speaker) volume control and SE -85-dB Mute Mode (headphone) volume control. Differential Inputs The 20-pin DIP package allows for the use of a µ A Shutdown Current (Typical) heatsink which provides higher output power. Headphone Mode To ensure a smooth transition between active and shutdown modes, a fade mode ramps the volume up and down. LCD Monitors Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS DISSIPATION RATING TABLE (1) TPA6021A4 SLOS465 JUNE 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGE T A 20-PIN PDIP (N) C to C TPA6021A4N over operating free-air temperature range (unless otherwise noted) (1) UNIT V SS Supply voltage, V DD PV DD 0.3 V to V V I Input voltage, RIN+, RIN-, LIN+,LIN- 0.3 V to V DD +0.3 V Continuous total power dissipation See Dissipation Rating Table T A Operating free-air temperature range C to C T J Operating junction temperature range C to 150 C T stg Storage temperature range C to C Lead temperature 1,6 mm (1/16 inch) from case for seconds 260 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. T A C DERATING FACTOR T A C T A C PACKAGE POWER RATING ABOVE T A C POWER RATING POWER RATING N 1.8 W 14.5 mW/ C 1.16 W 0.94 W (1) All characterization is done using an external heatsink with θ SA C/W. The resulting derating factor is 22.2 mW/

www.ti.com RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS OPERATING CHARACTERISTICS TPA6021A4 SLOS465 JUNE 2005 MIN MAX UNIT V SS Supply voltage, V DD PV DD 5.5 V SE/ BTL FADE 0.8 x V DD V V IH High-level input voltage SHUTDOWN V SE/ BTL FADE 0.6 x V DD V V IL Low-level input voltage SHUTDOWN 0.8 V T A Operating free-air temperature C T A V DD PV DD 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V DD 5.5 Gain dB, SE/ BTL V mV V OO Output offset voltage (measured differentially) V DD 5.5 Gain dB, SE/ BTL V mV PSRR Power supply rejection ratio V DD PV DD V to 5.5 V dB High-level input current (SE/ BTL FADE SHUT- V DD PV DD 5.5 I IH µ A DOWN VOLUME) V I V DD PV DD Low-level input current (SE/ BTL FADE SHUT- I IL V DD PV DD 5.5 V I V µ A DOWN VOLUME) V DD PV DD 5.5 SE/ BTL 7.5 SHUTDOWN V I DD Supply current, no load mA V DD PV DD 5.5 SE/ BTL 5.5 SHUTDOWN V V DD V PV DD SE/ BTL I DD Supply current, max power into a Ω load SHUTDOWN R L Ω 1.3 A RMS P O stereo I DD(SD) Supply current, shutdown mode SHUTDOWN V µ A T A V DD PV DD R L Ω Gain dB, Stereo, External Heatsink (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THD 1%, f kHz 1.5 (1) P O Output power W THD 10%, f kHz, V DD V (1) THD+N Total harmonic distortion noise P O R L Ω f Hz to kHz <0.8% V OH High-level output voltage R L Ω Measured between output and V DD 5.5 V 700 mV R L Ω Measured between output and GND, V OL Low-level output voltage 400 mV V DD 5.5 V V (Bypass) Bypass voltage (Nominally V DD /2) Measured at pin 16, No load, V DD 5.5 V 2.65 2.75 2.85 V BTL dB Supply ripple rejection ratio f kHz, Gain dB, C (BYP) 0.47 µ F SE dB f Hz to kHz, Gain dB, Noise output voltage BTL µ V RMS C (BYP) 0.47 µ F Z I Input impedance (see Figure VOLUME V k Ω (1) Requires an external heatsink with θ SA C/W.

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20 ROUT+PGND

19 SE/BTL

18 VOLUMEPVDD

17 AGNDRIN+

16 BYPASSRIN-

15 FADEVDD

14 SHUTDOWNLIN-

13 NCLIN+

12 LOUT+PVDD

1 PGND1LOUT-

N (PDIP) PACKAGE (TOP VIEW) Terminal Functions TERMINAL I/O NO. BYPASS I Tap to voltage divider for internal midsupply bias generator used for analog reference Places the amplifier in fade mode if a logic low is placed on this terminal; normal operation if a logic high is FADE I placed on this terminal. AGND Analog power supply ground LIN- I Left channel negative input for fully differential input. LIN+ I Left channel positive input for fully differential input. LOUT O Left channel negative audio output LOUT+ O Left channel positive audio output. NC No connection PGND Power ground PVDD Supply voltage terminal for power stage RIN- I Right channel negative input for fully differential input. RIN+ I Right channel positive input for fully differential input. ROUT O Right channel negative audio output ROUT+ O Right channel positive audio output Output control. When this terminal is high, SE outputs are selected. When this terminal is low, BTL outputs SE/ BTL I are selected. SHUTDOWN I Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal VDD Supply voltage terminal VOLUME I Terminal for dc volume control. DC voltage range is to V DD

www.ti.com FUNCTIONAL BLOCK DIAGRAM Power Management32-Step Volume Control Output Control RIN+ ROUT+ SHUTDOWN ROUT- PVDD PGND VDD BYPASS AGND LOUT- LOUT+ RIN- VOLUME FADE BYP BYP BYP EN SE/BTL BYP BYP BYP EN SE/BTL SE/BTL LIN- LIN+ TPA6021A4 SLOS465 JUNE 2005 NOTE: All resistor wipers are adjusted with step volume control.

www.ti.com TYPICAL CHARACTERISTICS Table of Graphs (1) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 20 20 k50 100 200 500 1 k 2 k 5 k 10 k P = 1.5 WO P = 0.25 WO f - Frequency - Hz THD+N - T ot al Harmonic Distortion + Noise (BTL) - % V = 5 V R = 4 Gain = 20 dB C = 0.47 F BTL Stereo DD L I W m P = 1 WO 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 20 20 k50 100 200 500 1 k 2 k 5 k 10 k P = 0.25 WO P = 0.5 WO f - Frequency - Hz THD+N - T ot al Harmonic Distortion + Noise (BTL) - % V = 5 V R = 8 Gain = 20 dB C = 0.47 F BTL Stereo DD L I W m P = 1 WO TPA6021A4 SLOS465 JUNE 2005 FIGURE vs Frequency THD+N Total harmonic distortion plus noise (BTL) vs Output power vs Frequency THD+N Total harmonic distortion plus noise (SE) vs Output power vs Output voltage Closed loop response P D Power Dissipation vs Output power 11, P O Output power vs Load resistance Crosstalk vs Frequency 14, PSRR Power supply ripple rejection (BTL) vs Frequency PSRR Power supply ripple rejection (SE) vs Frequency Z I Input impedance vs BTL gain (1) All graphs were taken using an external heatsink with θ SA C/W. TOTAL HARMONIC DISTORTION NOISE (BTL) TOTAL HARMONIC DISTORTION NOISE (BTL) vs vs FREQUENCY FREQUENCY Figure Figure

www.ti.com 0.01 0.02 0.05 0.1 0.2 0.5 20 20 k50 100 200 500 1 k 2 k 5 k 10 k f - Frequency - Hz THD+N - T ot al Harmonic Distortion + Noise (SE) - % V = 5 V R = 32 Gain = 14 dB C = 0.47 F SE Stereo DD L I W m C = 330 FO m P = 75 WO m 0.01 0.02 0.05 0.1 0.2 0.5 20 20 k50 100 200 500 1 k 2 k 5 k 10 k f - Frequency - Hz THD+N - T ot al Harmonic Distortion + Noise (SE) - % V = 1 VO RMS V = 5 V R = 10 k Gain = 14 dB C = 0.47 F SE Stereo DD L I W m C = 330 FO m 0.01 0.02 0.05 0.1 0.2 0.5 PO - Output Power - W THD+N - T ot al Harmonic Distortion + Noise (BTL) - %

20 Hz V = 5 V

R = 4 Gain = 20 dB C = 0.47 F BTL Stereo DD L I W m 20 kHz 1 kHz 0.01 0.02 0.05 0.1 0.2 0.5 PO - Output Power - W THD+N - T ot al Harmonic Distortion + Noise (BTL) - %1 kHz 20 Hz V = 5 V R = 8 Gain = 20 dB C = 0.47 F BTL Stereo DD L I W m 20 kHz TPA6021A4 SLOS465 JUNE 2005 TOTAL HARMONIC DISTORTION NOISE (SE) TOTAL HARMONIC DISTORTION NOISE (SE) vs vs FREQUENCY FREQUENCY Figure Figure TOTAL HARMONIC DISTORTION NOISE (BTL) TOTAL HARMONIC DISTORTION NOISE (BTL) vs vs OUTPUT POWER OUTPUT POWER Figure Figure

www.ti.com 0.01 0.02 0.05 0.1 0.2 0.5 10 20 30 40 20050 100 PO - Output Power - mW THD+N - T ot al Harmonic Distortion + Noise (SE) - % V = 5 V R = 32 Gain = 14 dB C = 0.47 F SE Stereo DD L I W m C = 330 FO m 20 Hz 1 kHz 20 kHz 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 al Harmonic Distortion + Noise (SE) - % 20 kHz 20 Hz V - Output Voltage - rmsO V = 5 V R = 10 k Gain = 14 dB C = 0.47 F SE Stereo DD L I W m C = 330 FO m 1 kHz 150 120 -30 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1 k 10 k 100 k 1 M -180 -150 -120 -90 -60 180 Gain Phase V = 5 V R = 8 Mode = BTL Gain = 0 dB DD L W f - Frequency - Hz Closed Loop Gain - dB Phase - Degrees 150 120 -30 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1 k 10 k 100 k 1 M -180 -150 -120 -90 -60 180 Gain Phase f - Frequency - Hz Closed Loop Gain - dB Phase - Degrees V = 5 V R = 8 Mode = BTL Gain = 20 dB DD L W TPA6021A4 SLOS465 JUNE 2005 TOTAL HARMONIC DISTORTION NOISE (SE) TOTAL HARMONIC DISTORTION NOISE (SE) vs vs OUTPUT POWER OUTPUT VOLTAGE Figure Figure CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE Figure Figure 10.

www.ti.com 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 PO - Output Power - W 4 W 8 W V = 5 V BTL DD P - Power Dissip ation (Per Channel) - W D 100 120 140 160 180 200 0 100 150 200 250 30050 8 W 16 W 32 W PO - Output Power - mW V = 5 V SE DD P - Power Dissip ation (Per Channel) - mW D 0.5 1.5 4 10 20 30 40 50 60 70 R - Load Resistance -L W P - Output Power - W O THD+N = 10% THD+N = 1% 2.5 V = 5 V Gain = 20 dB BTL Stereo DD -140 -40 -120 -100 -80 -60 20 20 k100 200 1 k 2 k 10 k f - Frequency - Hz Crosst alk - dB Left to Right Right to Left V = 5 V P = 1 W R = 8 Gain = 0 dB BTL DD O L W TPA6021A4 SLOS465 JUNE 2005 POWER DISSIPATION (PER CHANNEL) POWER DISSIPATION (PER CHANNEL) vs vs OUTPUT POWER OUTPUT POWER Figure 11. Figure 12. OUTPUT POWER CROSSTALK vs vs LOAD RESISTANCE FREQUENCY Figure 13. Figure 14.

www.ti.com 20 20 k100 1 k 10 k f - Frequency - Hz PSRR - Power Supply Rejection Ratio (SE) - dB-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Gain = 0 dB Gain = 20 dB V = 5 V R = 8 C = 0.47 F BTL DD L (BYP) W m C = 0.47 FI m -140 -40 -120 -100 -80 -60 20 20 k100 200 1 k 2 k 10 k f - Frequency - Hz Crosst alk - dB Left to Right Right to Left V = 5 V P = 1 W R = 8 Gain = 20 dB BTL DD O L W 20 20 k100 1 k 10 k f - Frequency - Hz PSRR - Power Supply Rejection Ratio (SE) - dB-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Gain = 14 dB Gain = 0 dB V = 5 V R = 32 C = 0.47 F SE DD L (BYP) W m C = 0.47 F C = 330 F I O m m −40 −30 −20 −10 0 10 20 BTL Gain − dB − Input Impedamce − ZI kΩ TPA6021A4 SLOS465 JUNE 2005 CROSSTALK POWER SUPPLY REJECTION RATIO (BTL) vs vs FREQUENCY FREQUENCY Figure 15. Figure 16. POWER SUPPLY REJECTION RATIO (SE) INPUT IMPEDANCE vs vs FREQUENCY BTL GAIN Figure 17. Figure 18.

www.ti.com APPLICATION INFORMATION SELECTION OF COMPONENTS PGND ROUT- PV DD RIN+ RIN- V DD LIN- LIN+ PV DD LOUT- ROUT+ SE/BTL VOLUME AGND NC BYPASS FADE SHUTDOWN LOUT+ PGND 10 11 CiRight Audio Source Left Audio Source Ci Ci Ci Power Supply Power Supply VDD 100 kW 100 kW In From DAC or Potentiometer (DC Voltage) System Control Right Speaker Left Speaker Headphones 1 kW 1 kWC 330 F O m C 330 F O m C 0.47 F (BYP) m 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm VDD VDD C 10 F S m TPA6021A4 SLOS465 JUNE 2005 Figure and Figure are schematic diagrams of typical LCD monitor application circuits. A 0.47- µ F ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise signals, a larger electrolytic capacitor of µ F or greater should be placed near the audio power amplifier. Figure 19. Typical TPA6021A4 Application Circuit Using Single-Ended Inputs and Input MUX

www.ti.com PGND ROUT- PV DD RIN+ RIN- V DD LIN- LIN+ PV DD LOUT- ROUT+ SE/BTL VOLUME AGND NC BYPASS FADE SHUTDOWN LOUT+ PGND 10 11 Ci VDD VDD Right Positive Differential Input Signal Left Negative Differential Input Signal Right Negative Differential Input Signal Left Positive Differential Input Signal Ci C C i i Power Supply Power Supply VDD 100 kW 100 kW C 330 F O m C 330 F O m 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm 0.47 Fm C 10 F S m C 0.47 F (BYP) m In From DAC or Potentiometer (DC Voltage) System Control Right Speaker Left Speaker Headphones 1 kW 1 kW SE/ BTL OPERATION TPA6021A4 SLOS465 JUNE 2005 APPLICATION INFORMATION (continued) A 0.47- µ F ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise signals, a larger electrolytic capacitor of µ F or greater should be placed near the audio power amplifier. Figure 20. Typical TPA6021A4 Application Circuit Using Differential Inputs The ability of the TPA6021A4 to easily switch between BTL and SE modes is one of its most important cost saving features. This feature eliminates the requirement for an additional headphone amplifier in accommodated. Internal to the TPA6021A4, two separate amplifiers drive OUT+ and OUT The SE/ BTL input controls the operation of the follower amplifier that drives LOUT and ROUT When SE/ BTL is held low, the amplifier is on and the TPA6021A4 is in the BTL mode. When SE/ BTL is held high, the OUT amplifiers are in a high output impedance state, which configures the TPA6021A4 as an SE driver from LOUT+ and ROUT+. I DD is reduced by approximately one-third in SE mode. Control of the SE/ BTL input can be from a logic-level CMOS source or, more typically, from a resistor divider network as shown in Figure The trip level for the SE/ BTL input can be found in the recommended operating conditions table.

www.ti.com SE/BTL ROUT+ 20 RIN+4

5 RIN-

(continued) Figure 21. TPA6021A4 Resistor Divider Network Circuit Using a 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When closed the 100-k Ω /1-k Ω divider pulls the SE/ BTL input low. When a plug is inserted, the 1-k Ω resistor is disconnected and the SE/ BTL input is pulled high. When the input goes high, the OUT amplifier is shut down causing the speaker to mute (open-circuits the speaker). The OUT+ amplifier then drives through the output capacitor o into the headphone jack. The TPA6021A4 employs a shutdown mode of operation designed to reduce supply current DD to the absolute minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state, I DD µ SHUTDOWN should never be left unconnected because amplifier operation would be unpredictable. Table SE/ BTL and Shutdown Functions INPUTS (1) AMPLIFIER STATE SE/ BTL SHUTDOWN OUTPUT X Low Mute Low High BTL High High SE (1) Inputs should never be left unconnected. For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown mode and conversely ramp the gain down when going into shutdown. This mode provides a smooth transition between the active and shutdown states and virtually eliminates any pops or clicks on the outputs.

www.ti.com ROUT+ Device Shutdown ROUT+ Device Shutdown TPA6021A4 SLOS465 JUNE 2005 When the FADE input is a logic low, the device is placed into fade-on mode. A logic high on this pin places the amplifier in the fade-off mode. The voltage trip levels for a logic low IL or logic high IH can be found in the recommended operating conditions table. When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin, the channel gain steps down from gain step to gain step at a rate of two clock cycles per step. With a nominal internal clock frequency of Hz, this equates to ms (1/29 Hz) per step. The gain steps down until the lowest gain step is reached. The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown. For example, if the amplifier is in the highest gain mode of dB, the time it takes to ramp down the channel gain is 1.05 seconds. This number is calculated by taking the number of steps to reach the lowest gain from the highest gain, or steps, and multiplying by the time per step, or ms. After the channel gain is stepped down to the lowest gain, the amplifier begins discharging the bypass capacitor from the nominal voltage of V DD to ground. This time is dependent on the value of the bypass capacitor. For a 0.47- µ F capacitor that is used in the application diagram in Figure the time is approximately 500 ms. This time scales linearly with the value of bypass capacitor. For example, if a µ F capacitor is used for bypass, the time period to discharge the capacitor to ground is twice that of the 0.47- µ F capacitor, or second. Figure below is a waveform captured at the output during the shutdown sequence when the part is in fade-on mode. The gain is set to the highest level and the output is at V DD when the amplifier is shut down. When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low, the device begins the start-up process. The bypass capacitor will begin charging. Once the bypass voltage reaches the final value of V DD /2, the gain increases in 2-dB steps from the lowest gain level to the gain level set by the dc voltage applied to the VOLUME pin. In the fade-off mode, the output of the amplifier immediately drops to V DD and the bypass capacitor begins a smooth discharge to ground. When shutdown is released, the bypass capacitor charges up to V DD and the channel gain returns immediately to the value on the VOLUME terminal. Figure below is a waveform captured at the output during the shutdown sequence when the part is in the fade-off mode. The gain is set to the highest level, and the output is at V DD when the amplifier is shut down. The power-up sequence is different from the shutdown sequence and the voltage on the FADE pin does not change the power-up sequence. Upon a power-up condition, the TPA6021A4 begins in the lowest gain setting and steps up dB every clock cycles until the final value is reached as determined by the dc voltage applied to the VOLUME pin. Figure 22. Shutdown Sequence in the Figure 23. Shutdown Sequence in the Fade-on Mode Fade-off Mode

www.ti.com VOLUME OPERATION -90 -80 -70 -60 -50 -40 -30 -20 -10 Volume [Pin 18] - V Volume - dB BTL Volume TPA6021A4 SLOS465 JUNE 2005 The VOLUME pin controls the BTL volume when driving speakers, and the SE volume when driving headphones. This pin is controlled with a dc voltage, which should not exceed V DD The output volume increases in discrete steps as the dc voltage increases and decreases in discrete steps as the dc voltage decreases. There are a total of discrete gain steps of the amplifier and range from -85 dB to dB for BTL operation and -85 dB to dB for SE operation. A pictorial representation of the typical volume control can be found in Figure Figure 24. Typical DC Volume Control Operation

www.ti.com INPUT RESISTANCE C IN Ri Rf Input Signal ƒ 3 dB 1

2 CRi

(1) INPUT CAPACITOR, C I fc(highpass) 1 2RiCi −3 dB fc (2) Ci 1 2Rifc (3) TPA6021A4 SLOS465 JUNE 2005 Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the dB or cutoff frequency also changes by over six times. Figure 25. Resistor on Input for Cut-Off Frequency The input resistance at each gain setting is given in Figure The 3-dB frequency can be calculated using Equation In the typical application an input capacitor I is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, C I and the input impedance of the amplifier I form a high-pass filter with the corner frequency determined in Equation The value of C I is important to consider as it directly affects the bass (low frequency) performance of the circuit. Consider the example where R I is k Ω and the specification calls for a flat-bass response down to Hz. Equation is reconfigured as Equation In this example, C I is 56.8 nF, so one would likely choose a value in the range of nF to µ A further consideration for this capacitor is the leakage path from the input source through the input network I and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most V DD /2, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application.

www.ti.com POWER SUPPLY DECOUPLING, C (S) MIDRAIL BYPASS CAPACITOR, C (BYP) OUTPUT COUPLING CAPACITOR, C (C) fc(high) 1 2RLC(C) −3 dB fc (4) TPA6021A4 SLOS465 JUNE 2005 The TPA6021A4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µ F placed as close as possible to the device V DD lead, works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of µ F or greater placed near the audio power amplifier is recommended. The midrail bypass capacitor (BYP) is the most critical capacitor and serves several important functions. During start-up or recovery from shutdown mode, C (BYP) determines the rate at which the amplifier starts up. The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and THD+N. Bypass capacitor (BYP) values of 0.47- µ F to µ F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. For the best pop performance, choose a value for C (BYP) that is equal to or greater than the value chosen for C I This ensures that the input capacitors are charged up to the midrail voltage before C (BYP) is fully charged to the midrail voltage. In the typical single-supply SE configuration, an output coupling capacitor (C) is required to block the dc bias at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by Equation The main disadvantage, from a performance standpoint, is the load impedances are typically small, which drives the low-frequency corner higher, degrading the bass response. Large values of C (C) are required to pass low frequencies into the load. Consider the example where a C (C) of 330 µ F is chosen and loads vary from Ω Ω Ω k Ω and k Ω Table summarizes the frequency response characteristics of each configuration. Table Common Load Impedances vs Low Frequency Output Characteristics in SE Mode LOWEST R L C (C) FREQUENCY Ω 330 µ F 120 Hz Ω 330 µ F Hz Ω 330 µ F Hz 10,000 Ω 330 µ F 0.05 Hz 47,000 Ω 330 µ F 0.01 Hz

www.ti.com USING LOW-ESR CAPACITORS BRIDGE-TIED LOAD vs SINGLE-ENDED LOAD Power V(rms) RL V(rms) VO(PP) 2 2 (5) RL 2x VO(PP) VO(PP) -VO(PP) VDD VDD TPA6021A4 SLOS465 JUNE 2005 As Table indicates, most of the bass response is attenuated into a Ω load, an Ω load is adequate, headphone response is good, and drive into line level inputs home stereo for example) is exceptional. Low-ESR capacitors are recommended throughout this section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. Figure shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA6021A4 BTL amplifier consists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this differential drive configuration, but, initially consider power to the load. The differential drive to the speaker means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to a ground referenced load. Plugging x V O(PP) into the power equation, where voltage is squared, yields the output power from the same supply rail and load impedance (see Equation Figure 26. Bridge-Tied Load Configuration

www.ti.com f(c) 1 2RLCC (6) RL C(C) VO(PP) VO(PP) VDD -3 dB fc SINGLE-ENDED OPERATION BTL AMPLIFIER EFFICIENCY TPA6021A4 SLOS465 JUNE 2005 In a typical computer sound channel operating at bridging raises the power into an Ω speaker from a singled-ended (SE, ground reference) limit of 250 mW to In sound power that is a 6-dB improvement, which is loudness that can be heard. In addition to increased power there are frequency response concerns. Consider the single-supply SE configuration shown in Figure A coupling capacitor is required to block the dc offset voltage from reaching the load. These capacitors can be quite large (approximately µ F to 1000 µ F), so they tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system. This frequency limiting effect is due to the high-pass filter network created with the speaker impedance and the coupling capacitance and is calculated with Equation For example, a 68- µ F capacitor with an Ω speaker would attenuate low frequencies below 293 Hz. The BTL configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency performance is then limited only by the input network and speaker response. Cost and PCB space are also minimized by eliminating the bulky coupling capacitor. Figure 27. Single-Ended Configuration and Frequency Response Increasing power to the load does carry a penalty of increased internal power dissipation. The increased dissipation is understandable considering that the BTL configuration produces the output power of the SE configuration. Internal dissipation versus output power is discussed further in the crest factor and thermal considerations section. In SE mode (see Figure the load is driven from the primary amplifier output for each channel (OUT+). The amplifier switches single-ended operation when the SE/ BTL terminal is held high. This puts the negative outputs in a high-impedance state, and effectively reduces the amplifier's gain by dB. Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output stage transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage drop that varies inversely to output power. The second component is due to the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from V DD The internal voltage drop multiplied by the RMS value of the supply current DD rms) determines the internal power dissipation of the amplifier. An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure

www.ti.com V(LRMS) VO IDD IDD(avg) Efficiency of a BTL amplifier PL PSUP Where: PL VLrms2 RL , and VLRMS VP 2 , therefore, PL VP 2RL and PSUP VDD IDDavg and IDDavg 1 VP RL sin(t) dt 1 VP RL [cos(t)] 0 2VP RL Therefore, PSUP 2 VDD VP RL (7) Efficiency of a BTL amplifier VP 2 RL

2 VDD VP

4 VDD

PL = Power delivered to load PSUP = Power drawn from power supply VLRMS = RMS voltage on BTL load RL = Load resistance VP 2 PL RL BTL

2 PL RL

Where: Therefore, VP = Peak voltage on BTL load IDDavg = Average current drawn from the power supply VDD = Power supply voltage ηBTL = Efficiency of a BTL amplifier (8) TPA6021A4 SLOS465 JUNE 2005 Figure 28. Voltage and Current Waveforms for BTL Amplifiers Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different. Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform. The following equations are the basis for calculating amplifier efficiency. substituting PL and PSUP into Equation Table employs Equation to calculate efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1-W audio system with Ω loads and a 5-V supply, we get an efficiency of 0.628. Total output power is 2-W. Thus the maximum draw on the power supply is almost 3.25

www.ti.com CREST FACTOR AND THERMAL CONSIDERATIONS P = 10LogdB = 10Log PW Pref 3 W 1 W = 5 dB (9) P = 10 x PW ref PdB/10 (10) TPA6021A4 SLOS465 JUNE 2005 Table Efficiency vs Output Power in 5-V, Ω BTL Systems OUTPUT POWER EFFICIENCY PEAK VOLTAGE INTERNAL DISSIPATION (W) (%) (V) (W) 0.25 31.4 2.00 0.55 0.50 44.4 2.83 0.62 1.00 62.8 4.00 0.59 1.25 70.2 4.47 (1) 0.53 (1) High peak voltages cause the THD to increase. A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation V DD is in the denominator. This indicates that as V DD goes down, efficiency goes up. Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. A typical music CD requires dB to dB of dynamic range, or headroom above the average power output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest factor between dB and dB. When determining the optimal ambient operating temperature, the internal dissipated power at the average output power level must be used. From the data sheet graph (Figure 5.), one can see that when the TPA6021A4 is operating from a 5-V supply into a Ω speaker at THD, that output power is 1.5-W so maximum instantaneous output power is 3-W. Use equation to convert watts to dB. Subtracting the headroom restriction to obtain the average listening level without distortion yields: dB dB dB (15-dB crest factor) dB dB dB (12-dB crest factor) dB dB dB (9-dB crest factor) dB dB dB (6-dB crest factor) dB dB dB (3-dB crest factor) To convert dB back into watts use equation 10. mW (18-dB crest factor) mW (15-dB crest factor) 190 mW (12-dB crest factor) 380 mW (9-dB crest factor) 750 mW (6-dB crest factor) 1500 mW (3-dB crest factor) This is valuable information to consider when attempting to estimate the heat dissipation requirements for the amplifier system. Comparing the worst case, which is 1.5 W of continuous power output with a 3-dB crest factor, against 12-dB and 15-dB system. Using the power dissipation curves for a 5-V, Ω system, the internal dissipation in the TPA6021A4 and maximum ambient temperatures is shown in Table

www.ti.com PD(max) 2V2 DD 2RL (11) qJA = = = 45 C/W o1 1 Derating Factor 0.0222 (12) TA Max = T PJ JA DMax - q = 150 - 45 (0.6 x 2) = 96 C(15-dB crest factor) o (13) TPA6021A4 SLOS465 JUNE 2005 Table TPA6021A4 Power Rating, 5-V, Ω Stereo PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT AVERAGE OUTPUT POWER (W) (W/Channel) TEMPERATURE 1500 mW dB) 1.26 C 750 mW dB) 1.20 C 380 mW dB) 1.00 C 190 mW (12 dB) 0.79 C mW (15 dB) 0.60 C (1) mW (18 dB) 0.44 110 C (1) (1) Package limited to C ambient. Table TPA6021A4 Power Rating, 5-V, Ω Stereo PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT AVERAGE OUTPUT POWER (W) (W/Channel) TEMPERATURE 2.2 1100 mW (3-dB crest factor) 0.57 C (1) 2.2 876 mW (4-dB crest factor) 0.61 C (1) 2.2 440 mW (7-dB crest factor) 0.62 C (1) 2.2 220 mW (10-dB crest factor) 0.53 103 C (1) (1) Package limited to C ambient. The maximum dissipated power D(max) is reached at a much lower output power level for an Ω load than for a Ω load. As a result, this simple formula for calculating P D(max) may be used for an Ω application. However, in the case of a Ω load, the P D(max) occurs at a point well above the normal operating power level. The amplifier may therefore be operated at a higher ambient temperature than required by the P D(max) formula for a Ω load. The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the N package with an external heatsink is shown in the dissipation rating table Use Equation to convert this to θ JA. To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are per channel, so the dissipated power needs to be doubled for two channel operation. Given θ JA the maximum allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be calculated using Equation The maximum recommended junction temperature for the TPA6021A4 is 150 The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs. NOTE: Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per channel. Table and Table show that some range. The TPA6021A4 is designed with thermal protection that turns the device off when the junction temperature surpasses 150 C to prevent damage to the IC. Table and Table were calculated for maximum listening volume without distortion. When the output level is reduced the numbers in the table change significantly. Also, using Ω speakers increases the thermal performance by increasing amplifier efficiency.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPA6021A4N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 12-Aug-2005 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPA6021A4N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TPA6021A4NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2005 Addendum-Page 1

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