TPA5051RSARG4

TPA5051_07 TI | Alldatasheet

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DATA1 DATA_OUT1 3.3□V BCLK1 LRCLK1 DATA1 TPA5051 Digital Amplfiier SCLK Audio□Processor SCLK BCLK1 LRCLK1 DATA1 SDA SCLADDx(2:0) I C□Delay Control VDDGND DATA2DATA2 BCLK2BCLK2 LRCLK2LRCLK2 DATA2 BCLK2 LRCLK2 DATA_OUT2 TAS5504A +□TAS5122 TAS3108 or ATSC Processor TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I C CONTROL High Definition Lip-Sync Delay Digital Audio Format: 16-24-bit I Right-Justified, Left-Justified Flat Panel TV Lip-Sync Delay Home Theater Rear Channel Effects I C Bus Controlled Wireless Speaker Front-Channel Dual Serial Input Ports Synchronization Delay Time: ms/ch at fs kHz Delay Resolution: One Sample Delay Memory Cleared on Power-Up or After The TPA5051 accepts two serial audio inputs, Delay Changes buffers the data for a selectable period of time, and Eliminates Erroneous Data on Output outputs the delayed audio data on two serial outputs. One device allows delay of up to ms/ch (fs 3.3 V Operation With V Tolerant I/O and I C kHz) to synchronize the audio stream to the video Control stream in systems with complex video processing Supports Audio Bit Clock Rates of to fs algorithms. If more delay is needed, the devices can with fs kHz 192 kHz be connected in series. Independent clocks can be No External Crystal or Oscillator Required used for each audio input. All Internal Clocks Generated From the Audio Clock Independent Clocks for Each Audio Input Surface Mount 4mm 4mm, 16-pin QFN Package Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com PIN DESCRIPTIONS BCLK1DA T A_OUT1GND VDD ADD1 LRCLK1 SCL DA T A_OUT2 ADD0 ADD2 GND DA T A1 75 6 1 1 16 15 14 13 4SDA DA T A2 LRCLK2BCLK2 RSA (QFN)□PACKAGE (TOP VIEW) TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 TERMINAL FUNCTIONS TERMINAL I/O NO. ADD0 I I C address select pin LSB. tolerant input. ADD1 I I C address select pin. tolerant input. ADD2 I I C address select pin MSB. tolerant input. BCLK1 (1) I Audio data bit clock input for serial input tolerant input. BCLK2 (1) I Audio data bit clock input for serial input tolerant input. DATA1 I Audio serial data input for serial input tolerant input. DATA2 I Audio serial data input for serial input tolerant input. DATA_OUT1 O Delayed audio serial data output for channel DATA_OUT2 O Delayed audio serial data output for channel GND P Ground All ground terminals must be tied to GND for proper operation LRCLK1 (1) I Channel left and right serial audio sampling rate clock (fs). tolerant input. LRCLK2 (1) I Channel left and right serial audio sampling rate clock (fs). tolerant input. SCL I I C communication bus clock input. tolerant input. SDA I/O I C communication bus data input. tolerant input. VDD P Power supply interface. Connect to ground. Must be soldered down in all PCB. (1) Left and right channels may use different BCLK frequencies as well as different LRCLK (fs) frequencies. Submit Documentation Feedback

www.ti.com FUNCTIONAL BLOCK DIAGRAM DATA1 BCLK1 LRCLK1 INPUT BUFFER OUTPUT BUFFER DATA_OUT1 CONTROL2 I C ADDx□(2:0) DELAY MEMORY DELAY MEMORY DATA2 BCLK2 LRCLK2 DATA_OUT2 ABSOLUTE MAXIMUM RATINGS DISSIPATION RATINGS (1) RECOMMENDED OPERATING CONDITIONS TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 over operating free-air temperature (unless otherwise noted) (1) VALUE UNIT V DD Supply voltage 0.3 to 3.6 V V I Input voltage DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0] 0.3 to 5.5 V Continuous total power dissipation See Dissipation Rating Table T A Operating free-air temperature range to C T J Operating junction temperature range to 125 C T stg Storage temperature range to 125 C Lead temperature 1,6 mm (1/16 inch) from case for seconds 260 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PACKAGE T A C DERATING T A C T A C POWER RATING FACTOR POWER RATING POWER RATING RSA 2.5 W mW/ C 1.375 W 1.0 W (1) This data was taken using oz trace copper and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI technical briefs SCBA01 D and SLUA271 for more information about using the QFN thermal pad. MIN MAX UNIT V DD Supply voltage VDD 3.6 V V IH High-level input voltage DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL, SDA, V ADD[2:0] V IL Low-level input voltage DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL, SDA, 0.8 V ADD[2:0] T A Operating free-air temperature C Submit Documentation Feedback

www.ti.com DC CHARACTERISTICS TIMING CHARACTERISTICS (1) (2) SCL SDA tw(H) tw(L) t su1 th1 SCL SDA th2 t(buf) tsu2 tsu3 Start□Condition Stop□Condition TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 T A V DD V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I DD Supply current V DD 3.3 fs kHz, BCLK fs 1.8 mA I OH High-level output current DATA_OUT1 DATA_OUT2 2.6 V mA I OL Low-level output current DATA_OUT1 DATA_OUT2 0.4 V mA DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL, µ A SDA, Vi 5.5V, VDD I IH High-level input current ADD[2:0], Vi 3.6V, VDD 3.6V µ A DATA1, DATA2, LRCLK1, LRCLK2, BCLK1, BCLK2, SCL, µ A I IL Low-level input current SDA, ADD[2:0], Vi 0V, VDD 3.6V For I C Interface Signals Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f SCL Frequency, SCL No wait states 400 kHz t w(H) Pulse duration, SCL high 0.6 µ s t w(L) Pulse duration, SCL low 1.3 µ s t su1 Setup time, SDA to SCL 100 ns t Hold time, SCL to SDA ns t (buf) Bus free time between stop and start condition 1.3 µ s t su2 Setup time, SCL to start condition 0.6 µ s t Hold time, start condition to SCL 0.6 µ s t su3 Setup time, SCL to stop condition 0.6 µ s (1) V Pull-up V DD (2) A pull-up resistor k Ω is required for a V I C bus voltage. Figure SCL and SDA Timing Figure Start and Stop Conditions Timing Submit Documentation Feedback

www.ti.com Serial Audio Input Ports th1 tsu1 tsu2 th2 DA T A BCLK (Input) LRCLK (Input) APPLICATION INFORMATION AUDIO SERIAL INTERFACE AUDIO DATA FORMATS AND TIMING TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f SCLKIN Frequency, BCLK fs, fs, fs 1.024 12.288 MHz t su1 Setup time, LRCLK to BCLK rising edge ns t Hold time, LRCLK from BCLK rising edge ns t su2 Setup time, DATA to BCLK rising edge ns t Hold time, DATA from BCLK rising edge ns LRCLK frequency 192 kHz BCLK duty cycle 50% LRCLK duty cycle 50% BCLK rising edges between LRCLK rising edges LRCLK duty cycle 50% BCLK edges Figure Serial Data Interface Timing The audio serial interface for the TPA5051 consists of two 3-wire synchronous serial ports. Each includes an LRCLK, BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on the DATA line into the serial shift register of the audio interface. Serial data is clocked into the TPA5051 on the rising edge of BCLK. LRCLK is the serial audio left/right word clock, operated at the sampling frequency, fs. It is used to latch serial data into the internal registers of the serial audio interface. BCLK can be operated at to times the sampling frequency for right-justified, left-justified, and I S formats. Generally, both LRCLK and BCLK should be synchronous to the system clock. However, the TPA5051 does not have a system clock, so the only synchonization necessary is between BCLK and LRCLK. The TPA5051 supports industry-standard audio data formats, including right-justified, I and left-justified. The data formats are shown in Figure Data formats are selected using the I C interface and register map (see Table Submit Documentation Feedback

www.ti.com LRCK (2)□I2S□Data□Format;□L-Channel□=□LOW ,□R-Channel□=□HIGH MSB LSB 1/fS (= 32□fS,□48□fS, or□64□fS) 18-Bit□Right-Justified,□BCK□=□48□f S or□64□fS 1/fS (1) Right-Justified□Data□Format;□L-Channel□=□HIGH,□R-Channel□=□LOW (3)□Left-Justified□Data□Format;□L-Channel□=□HIGH,□R-Channel□=□LOW MSB LSB 20-Bit Right-Justified,□BCK□=□48□f S or□64□fS MSB LSB 24-Bit□Right-Justified,□BCK□=□48□f S or□64□fS 1/fS MSB LSB 16-Bit□Right-Justified,□BCK□=□32□f S 16-Bit□Right-Justified,□BCK□=□48□f S or□64□fS MSB LSB L-Channel R-Channel BCK DATA 14 15 16 1 2 3 14 15 16 14 15 16 1 2 3 14 15 16 16 17 18 DATA DATA DATA DATA 1 2 3 16 17 18 18 19 20 1 2 3 18 19 20 22 23 24 1 2 3 MSB LSB MSB LSB MSB LSB MSB LSB 1 2 3 14 15 16 1 2 3 14 15 16 1 2 3 16 17 18 1 2 3 18 19 20 22 23 24 MSB LSB 1 2 3 22 23 24 L-Channel R-ChannelLRCK BCK DATA 1 2 3 1 2 MSB N–2 NN–1 LSB 1 2 3 MSB N–2 NN–1 LSB L-Channel R-ChannelLRCK BCK DATA 1 2 3 N–2 NN–1 1 2 3 N–2 NN–1 1 2 MSB LSB LSBMSB TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 APPLICATION INFORMATION (continued) Figure Audio Data Formats Submit Documentation Feedback

www.ti.com GENERAL I C OPERATION Register□(N) 8-□Bit□Data□for 8-□Bit□Data□for Register□(N+1) SINGLE-AND MULTIPLE-BYTE TRANSFERS TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 APPLICATION INFORMATION (continued) The I C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The TPA5051 holds SDA low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. When the bus level is pull-up resistors between k Ω and k Ω in value must be used. For a bus level of 3.3 higher resistor values, such as k Ω may be used. Figure Typical I C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure The 7-bit address for the TPA5051 is selectable using the address pins (ADD0, ADD1, ADD2). Table lists the possible slave addresses. Table I C Slave Address SELECTABLE ADDRESS BITS FIXED ADDRESS MSB bits) ADD2 ADD1 ADD0 1101 1101 1101 1101 1101 1101 1101 1101 The serial control interface supports both single-byte and multi-byte read/write operations for all registers. During multiple-byte read operations, the TPA5051 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges. Submit Documentation Feedback

www.ti.com SINGLE-BYTE WRITE A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I2C□Device□Address□and Read/Write□Bit Register Data□□Byte MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE Register SINGLE-BYTE READ TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 The TPA5051 supports sequential I C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I C write transaction has taken place. For I C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written. As shown is Figure a single-byte data write transfer begins with the master device transmitting a start condition followed by the I C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit must be set to After receiving the correct I C device address and the read/write bit, the TPA5051 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the TPA5051 internal memory address being accessed. After receiving the register byte, the TPA5051 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TPA5051 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer. Figure Single-Byte Write Transfer A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TPA5051 as shown in Figure After receiving each data byte, the TPA5051 responds with an acknowledge bit. Figure Multiple-Byte Write Transfer As shown in Figure a single-byte data read transfer begins with the master device transmitting a start condition followed by the I C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a After receiving the TPA5051 address and the read/write bit, the TPA5051 responds with an acknowledge bit. The master then sends the internal memory address byte, after which the TPA5051 issues an acknowledge bit. The master device transmits another start condition followed by the TPA5051 address and the read/write bit again. This time the read/write bit is set to indicating a read transfer. Next, the TPA5051 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer. Submit Documentation Feedback

www.ti.com A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I2C□Device□Address□and Read/Write□Bit Register Data□Byte D7 D6 D1 D0 ACK I2C□Device□Address□and Read/Write□Bit Not Acknowledge R/WA1 A1 Repeat□Start Condition MULTIPLE-BYTE READ A6 A0 ACK Acknowledge I2C□Device□Address□and Read/Write□Bit R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge Last□Data□Byte ACK First□Data□Byte Repeat□Start Condition Not Acknowledge I2C□Device□Address□and Read/Write□Bit Register Other□Data□Bytes A7 A6 A5 D7 D0 ACK Acknowledge D7 D0 TPA5051 Operation VDD DATA1 LRCLK1 BCLK1 GND DATA_OUT1 SDA SCL ADD0 ADD1 ADD2 GND 3.3□V

0.1 F/c109

Word□Clock1 Bit□Clock1 Delayed Audio1 I C□Clock I C□Data I C Address Select Digital Audio2 Word□Clock2 Bit□Clock2 DATA2 LRCLK2 BCLK2 DATA_OUT2 Delayed Audio2 TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 Figure Single-Byte Read Transfer A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TPA5051 to the master device as shown in Figure With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Figure Multiple-Byte Read Transfer The following sections describe the registers configurable via I C commands for the TPA5051. Only a single decoupling capacitor (0.1 µ F µ is required across VDD and GND. The ADDx terminals can be directly connected to VDD or GND. Table describes the I C addresses selectable via the ADDx terminals. A schematic implementation of the TPA5051 is shown in Figure Figure 10. TPA5051 Schematic Submit Documentation Feedback

www.ti.com SERIAL CONTROL INTERFACE REGISTER SUMMARY CONTROL REGISTER (0x01, 0x09) AUDIO DELAY REGISTERS (0x02 0x05, 0x0A 0x0D) TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 Table Serial Control Register Summary REGISTER REGISTER NAME NO. OF

(1) Control Register (1) Right Delay Upper bits) (1) Right Delay Lower bits) (1) Left Delay Upper bits) (1) Left Delay Lower bits) (1) Frame Delay (1) RJ Packet Length (1) Complete Update (2) Control Register (2) Right Delay Upper bits) (2) Right Delay Lower bits) (2) Left Delay Upper bits) (2) Left Delay Lower bits) (2) Frame Delay (2) RJ Packet Length (2) Complete Update (1) I C registers for serial data channel (2) I C registers for serial data channel The control register allows the user to mute a specific audio channel. It is also used to specify the data type Right-Justified, or Left-Justified). Table Control Registers (0x01, 0x09) (1) FUNCTION X X X X Left and Right channel are active. X X X X Left channel is MUTED. X X X X Right channel is MUTED. X X X X Left and Right channel are MUTED. X X X X I S data format X X X X Right-justified data format (see PACKET LENGTH register 0x07) X X X X Left-justified data format X X X X Bypass mode data is passed straight through without delay. (1) Default values are in bold The audio delay for the left and right channels is fixed by writing a total of bits byte transfer) to upper and lower registers as specified in Table A multiple byte transfer should be performed starting with the control register and following with bytes to fill the upper and lower registers associated with right/left channel delay. The decimal value of D13 equals the number of samples to delay. The maximum number of delayed samples per channel is 4095 for the TPA5051. This equates to 85.3 ms ([4095 (1/Fs)] at kHz) of delay per channel. Submit Documentation Feedback

www.ti.com FRAME DELAY REGISTERS (0x06, 0x0E) RJ PACKET LENGTH REGISTERS (0x07, 0x0F) TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 Table Audio Delay Registers (0x02 0x05, 0x0A 0x0D) (1) D13 D12 D11 FUNCTION Left and Right audio is passed to output with no delay. Left and Right audio is delayed by sample (1/Fs delay time) Left and Right audio is delayed by 4095 samples (4095/Fs delay time) (1) Default values are in bold This register can be used to specify delay in video frames instead of audio samples. When the MSB is set to the audio delay registers (0x01 0x04) are bypassed and the Frame Delay Register is used to set the delay based on the frame rate (D6), audio sample rate (D5 D3), and number of frames to delay (D2 D0). The total audio delay time is calculated by the following formula: Audio Delay (in samples) int Delay Frames (1/Frame Rate) Audio Sample Rate] If the result of the formula above is greater than the maximum number of delay samples (4095 for TPA5051), then the value is limited to this maximum before passing to the delay block. Table Frame Delay Registers (0x06, 0x0E) (1) FUNCTION Settings in this register are masked and audio delay is determined by settings in the right/left audio delay registers. Right/left audio delay registers are masked and delay is determined by settings in this register. Frame rate Hz Frame rate 59.94 Hz Audio sample rate kHz Audio sample rate 44.1 kHz Audio sample rate kHz Audio sample rate 88.2 kHz Audio sample rate kHz Audio sample rate 176.4 kHz Audio sample rate 192 kHz Audio sample rate 192 kHz Delay frames Delay frames Delay frames (1) Default values are in bold This register is only used in right justified mode. The decimal value of bits [5:0] represents the width of the useable data in a right justified audio stream. The number of BCLK transitions between LRCLK transitions must be greater than or equal to the packet length selected in this register. The maximum packet length value is bits. Any setting greater whose numerical value is greater than bits is limited to the maximum bits. Table RJ Package Length (0x07, 0x0F) (1) FUNCTION Packet length bits Packet length bits X X X Packet length bits (1) Default values are in bold Submit Documentation Feedback

www.ti.com COMPLETE UPDATE REGISTER (0x08, 0x10) APPLICATION EXAMPLES Connecting Two Devices in Series to Increase the Delay BCLK1 LRCLK1 DATA1 DATA2 BCLK2 LRCLK2 2□k/c87 2□k/c87 BCLK1 LRCLK1 DATA1 DATA2 BCLK2 LRCLK2 BCLK1 LRCLK1 DATA1 DATA2 BCLK2 LRCLK2 BCLK1 LRCLK1 DATA1 DATA2 BCLK2 LRCLK2 DATA_OUT1 DATA_OUT2 DATA_OUT1 DATA_OUT2 VDD GND registers, it is likely that multiple writes would be necessary to configure the device. This may cause interruptions in the audio stream and unwanted pops and clicks might occur as register data is passed to delay functional block. To avoid this from happening, the Complete Update register is used to transfer the user settings from the register file to the delay functional block when a is written to the LSB. For example, if the right delay is set to samples, and the left delay is set to 300 samples, the device holds the right channel in MUTE until samples of audio data have passed, and holds the left channel in MUTE until 300 samples of audio data have passed. The Complete Update register must also be used when either the stream type is changed or the RJ packet length is changed. If a complete update command is not issued, the changes will not take effect. Note that the individual channels can be muted using the upper bits of the Control Registers without writing to the Complete Update registers. Table Complete Update Registers (0x08, 0x10) (1) FUNCTION X No data from the register settings is passed to the delay block. X Stream type, right/left delay or frame delay, and packet length is passed to the delay functional block. (1) Default values are in bold It is sometimes desirable to increase the delay time beyond which one device can provide. In such cases, several TPA5051 devices can be placed in series to increase the delay. A maximum of eight devices can be placed in series. This is because each device has eight I address settings. Under no circumstances should two TPA5051 devices share the same I S address. See Figure Figure 11. Two Devices Connected in Series Submit Documentation Feedback

www.ti.com I C Examples Single Byte Write D2Start ACK 01 ACK C0 ACK Stop TPA5051 Address□and Write Register Address Data Multiple Byte Write D2Start ACK01 00 04ACK TPA5051 Address□and Write Register Address (Control□Register )DATA1 Data (Right□Delay□Upper□Bits )DATA1 ACK ACK 00 ACK Data (Control□Register )DATA1 Data (Right□Delay□Lower□Bits )DATA1

08 ACK00 00 00ACK

(Left□Delay□Upper□Bits )DATA1 Data (RJ□Packet□=□0□Bits )DATA1 ACK ACK 01 ACK Data (Frame□Delay )DATA1 Data (Complete□Update )DATA1 Data (Left□Delay□Lower□Bits )DATA1 Stop

10 ACK00 00 00ACK

(Control□Register )DATA2 Data (Left□Delay□Upper□Bits )DATA2 ACK ACK 00 ACK Data (Right□Delay□Lower□Bits )DATA2 Data (Left□Delay□Lower□Bits )DATA2 Data (Right□Delay□Upper□Bits )DATA2

91 ACK10 01 ACK

(Frame□Delay )DATA2 ACK Data (Complete□Update )DATA2 Data (RJ□Packet□=□16□Bits )DATA2 TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 The following are some examples of I C commands used to read or write to the TPA5051. For all conditions, assume the address of the TPA5051 is set to 001. In this example, the TPA5051 is set to mute both left and right channels of DATA1, and to operate in I S mode. NOTE: Because no complete update command was issued in this example, the stream type change will not take effect until a is written to the Complete Update register. In this example, the TPA5051 is set to make both the left and right channels of both DATA1 and DATA2 active. DATA1 is set to operate in I S mode, delay the right channel by 1024 samples, and delay the left channel by 2048 samples. DATA2 is set to operate in the Right-Justified mode with a packet length of bits. It is to delay the audio signal by ms using the Frame Delay function. Assume the audio sample rate (fs) kHz, and the Frame rate Hz. This is a sequential write, so all registers must have data written to them. Submit Documentation Feedback

www.ti.com Combination of Single Byte Writes D2Start ACK 01 ACK 00 ACK Stop TPA5051 Address□and Write Register Address (Control□Register )DATA1 Data (Control□Register )DATA1 D2Start ACK 09 ACK C0 ACK TPA5051 Address□and Write Register Address (Control□Register )DATA2 Data (Control□Register )DATA2 Stop Single Byte Read D2Start ACK 01 ACK Start D3 XX TPA5051 Address□and Write Register Address (Control□Register )DATA1 StopACK Data□Read (Control□Register )DATA1 No ACK TPA5051 Address□and Read TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 In this example, DATA1 set to operate in the I S mode, and DATA2 is set to mute. Note that in every circumstance where a delay or stream type is written into the memory of the TPA5051, a must be written to the Complete Update registers for the change to take effect. In this example, the stream type change made to DATA1 would not take effect. This does not apply to muting, which occurs in the Control registers. In this example, one byte of data is read from the Control Register (0x01). After the data (represented xx by is read by the master device, the master device issues a Not Acknowledge, before stopping the communication. Submit Documentation Feedback

www.ti.com Multiple Byte Read D2Start ACK01 TPA5051 Address□and Write Register Address (Control□Register )DATA1 ACK ACK XX ACK Data□Read (Control□Register )DATA2 Data□Read (Control□Register )DATA1 XX ACKXX XX XXACK Data□Read (Right□Delay□Upper□Bits )DATA1 Data□Read (RJ□Packet□Length )DATA1 ACK ACK XX ACK Data□Read (Frame□Delay )DATA1 Data□Read (Complete□Update )DATA1 Data□Read (Right□Delay□Lower□Bits )DATA1 Stop XX ACKXX XX XXACK Data□Read (Left□Delay□Upper□Bits )DATA2 ACK ACK XX ACK Data□Read (Right□Delay□Lower□Bits )DATA2 Data□Read (Left□Delay□Lower□Bits )DATA2 Data□Read (Right□Delay□Upper□Bits )DATA2 XX ACKXX XX NO ACK Data□Read (Frame□Delay )DATA2 ACK Start D3 TPA5051 Address□and Read Data□Read (Left□Delay□Upper□Bits )DATA1 Data□Read (Left□Delay□Lower□Bits )DATA1 TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 Often, when it is necessary to read what is contained in one register, it is necessary to determine what information is contained in all registers. In such a case, a sequential read should be used. In situations where data must be read from a register at the beginning (0x01), and a register towards the end (0x0E), a sequential read is likely to be faster to implement than multiple single byte reads. In this example, a sequential read is initiated with the Control Register (0x01), and ends with the Frame Delay Register (0x0E). Submit Documentation Feedback

www.ti.com DEVICE CURRENT CONSUMPTION 0.5 1.5 2.5 3.5 4.5 32 52 72 92 112 132 152 172 192 fs□-□Sampling□Frequency□-□kHz I -□Supply□Current□-□mA DD V =□3.6□VDD V =□3.3□VDD V =□3□VDD BCLK□=□64□fs Data□=□24□bit SUPPLY CURRENT vs SAMPLING□FREQUENCY TPA5051 SLOS497A JUNE 2006 REVISED JULY 2006 The TPA5051 draws different amounts of supply current depending upon the conditions under which it is operated. As V DD increases, so too does I DD Likewise, as V DD decreases, I DD decreases. The same is true of the sampling frequency, fs. An increase in fs causes an increase in I DD Figure illustrates the relationship between operating condition and typical supply current. Figure 12. Typical Supply Current Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPA5051RSAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA5051RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA5051RSAT ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA5051RSATG4 ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

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Summary

FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL

Description

FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL

Source title TPA5051RSARG4 Datasheet(PDF) - Texas Instruments

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