TPA4861DR.A

TPA4861 TI | Alldatasheet

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a shutdown function for power-sensitive

applications

protection. The TPA4861 works seamlessly with TI's TPA4860 in stereo applications. The amplifier is available in an 8-pin SOIC surface-mount package that reduces board space and facilitates automated assembly. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 1996 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS DISSIPATION RATING TABLE RECOMMENDED OPERATING CONDITIONS TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGED DEVICE T A SMALL OUTLINE (1) (D) C to C TPA4861D (1) The D package is available tape and reeled. To order a tape and reeled part, add the suffix R to the part number (e.g., TPA4861DR). Terminal Functions TERMINAL I/O

DESCRIPTION

NO. BYPASS is the tap to the voltage divider for internal mid-supply bias. This terminal should be connected to a BYPASS I 0.1- µ F 1.0- µ F capacitor when used as an audio power amplifier. GND GND is the ground connection. IN- I IN- is the inverting input. IN- is typically used as the audio input terminal. IN+ I IN+ is the noninverting input. IN+ is typically tied to the BYPASS terminal. SHUTDOWN I SHUTDOWN places the entire device in shutdown mode when held high DD 0.6 µ A). V O O V O is the positive BTL output. V O O V O is the negative BTL output. V DD V DD is the supply voltage terminal. over operating free-air temperature range (unless otherwise noted) (1) UNIT V DD Supply voltage V V I Input voltage 0.3 V to V DD +0.3 V Continuous total power dissipation Internally Limited (see Dissipation Rating Table) T A Operating free-air temperature range C to C T J Operating junction temperature range C to 150 C T stg Storage temperature range C to 150 C Lead temperature 1,6 mm (1/16 inch) from case for seconds 260 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PACKAGE T A C DERATING FACTOR T A C T A C D 725 mW 5.8 mW/ C 464 mW 377 mW MIN MAX UNIT V DD Supply voltage 2.7 5.5 V V DD V 1.25 2.7 V V IC Common-mode input voltage V DD V 1.25 4.5 V T A Operating free-air temperature C

www.ti.com ELECTRICAL CHARACTERISTICS OPERATING CHARACTERISTICS ELECTRICAL CHARACTERISTICS OPERATING CHARACTERISTICS TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 at specified free-air temperature, V DD 3.3 V (unless otherwise noted) TPA4861 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX V OO Output offset voltage See (1) mV PSRR Power supply rejection ratio Δ V DD Δ V OO V DD 3.2 V to 3.4 V dB I DD Supply current 2.5 mA I DD(SD) Supply current, shutdown 0.6 µ A (1) At V V DD V the dc output voltage is approximately V DD /2. V DD 3.3 T A R L Ω TPA4861 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX THD 0.2%, f kHz, A V V/V 400 mW P O Output power (1) THD 2%, f kHz, A V V/V 500 mW B OM Maximum output power bandwidth Gain V/V, THD kHz B Unity-gain bandwidth Open Loop 1.5 MHz BTL f kHz, C B 0.1 µ F dB Supply ripple rejection ratio SE f kHz, C B 0.1 µ F dB V n Noise output voltage (2) Gain V/V µ V (1) Output power is measured at the output terminals of the device. (2) Noise voltage is measured in a bandwidth of Hz to kHz. at specified free-air temperature range, V DD V (unless otherwise noted) TPA4861 PARAMETER TEST CONDITION UNIT MIN TYP MAX V OO Output offset voltage See (1) mV PSRR Power supply rejection ratio Δ V DD Δ V OO V DD 4.9 V to 5.1 V dB I DD Supply current 3.5 mA I DD(SD) Supply current, shutdown 0.6 µ A (1) At V V DD V the dc output voltage is approximately V DD /2. V DD T A R L Ω TPA4861 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX THD 0.2%, f kHz, A V V/V 1000 mW P O Output power (1) THD 2%, f kHz, A V V/V 1100 mW B OM Maximum output power bandwidth Gain -10 V/V, THD kHz B Unity-gain bandwidth Open Loop 1.5 MHz BTL f kHz, C B 0.1 µ F dB Supply ripple rejection ratio SE f kHz, C B 0.1 µ F dB V n Noise output voltage (2) Gain V/V µ V (1) Output power is measured at the output terminals of the device. (2) Noise voltage is measured in a bandwidth of Hz to kHz.

www.ti.com TYPICAL CHARACTERISTICS Number of Amplifiers VOO − Output Offset Voltage − mV −4 −3 −2 −1 0 1 2 3 4 5 6 VDD = 3.3 V Number of Amplifiers VOO − Output Offset Voltage − mV VDD = 5 V −4 −3 −2 −1 0 1 2 3 4 5 6 TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 Table of Graphs FIGURE V OO Output offset voltage Distribution I DD Supply current distribution vs Free-air temperature vs Frequency 10,11,15, 16,17,18 THD+N Total harmonic distortion plus noise vs Output power 12, 13, 14, 19,20,21 I DD Supply current vs Supply voltage V n Output noise voltage vs Frequency 23, Maximum package power dissipation vs Free-air temperature Power dissipation vs Output power 26, Maximum output power vs Free-air temperature vs Load resistance Output power vs Supply voltage Open-loop gain vs Frequency k SVR Supply ripple rejection ratio vs Frequency 32, DISTRIBUTION OF TPS4861 DISTRIBUTION OF TPS4861 OUTPUT OFFSET VOLTAGE OUTPUT OFFSET VOLTAGE Figure Figure

www.ti.com − Supply Current − mA 2.5 1.5 0.5 −40 25 VDD = 5 V I DD 3.5 4.5 Typical − Supply Current − mA 3.5 −40 25 2.5 1.5 0.5 VDD = 3.3 V I DD Typical 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz VDD = 5 V PO = 1 W AV = −2 V/V RL = 8 Ω CB = 0.1 µF CB = 1 µF THD+N − Total Harmonic Distortion Plus Noise − % 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz VDD = 5 V PO = 1 W AV = −10 V/V RL = 8 Ω CB = 0.1 µF CB = 1 µF THD+N − Total Harmonic Distortion Plus Noise − % TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 SUPPLY CURRENT DISTRIBUTION SUPPLY CURRENT DISTRIBUTION vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Figure Figure TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY Figure Figure

www.ti.com 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz VDD = 5 V PO = 1 W AV = −20 V/V RL = 8 ΩCB = 0.1 µF CB = 1 µF THD+N − Total Harmonic Distortion Plus Noise − % 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz VDD = 5 V PO = 0.5 W AV = −2 V/V RL = 8 Ω CB = 0.1 µF CB = 1 µF THD+N − Total Harmonic Distortion Plus Noise − % 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz VDD = 5 V PO = 0.5 W AV = −10 V/V RL = 8 Ω CB = 0.1 µF CB = 1 µF THD+N − Total Harmonic Distortion Plus Noise − % 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz THD+N − Total Harmonic Distortion Plus Noise − % VDD = 5 V PO = 0.5 W AV = −20 V/V RL = 8 ΩCB = 0.1 µF CB = 1 µF TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY Figure Figure TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY Figure Figure 10.

www.ti.com 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz THD+N − Total Harmonic Distortion Plus Noise − % VDD = 5 V AV = −10 V/V Single Ended RL = 8 Ω PO = 250 mW RL = 32 Ω PO = 60 mW 0.02 0.1 0.01 0.1 1 PO − Output Power − W THD+N − Total Harmonic Distortion Plus Noise − % VDD = 5 V AV = −2 V/V RL = 8 Ω f = 20 Hz CB = 0.1 µF CB = 1 µF 0.02 0.1 0.01 0.1 1 PO − Output Power − W THD+N − Total Harmonic Distortion Plus Noise − % VDD = 5 V AV = −2 V/V RL = 8 Ω f = 1 kHz CB = 0.1 µF CB = 1 µF 0.02 0.1 0.01 0.1 1 PO − Output Power − W THD+N − Total Harmonic Distortion Plus Noise − % VDD = 5 V AV = −2 V/V RL = 8 Ω f = 20 kHz CB = 0.1 µF CB = 1 µF TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY OUTPUT POWER Figure 11. Figure 12. TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER Figure 13. Figure 14.

www.ti.com 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V PO = 350 mW RL = 8 Ω AV = −2 V/V CB = 0.1 µF CB = 1 µF 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V PO = 350 mW RL = 8 Ω AV = −10 V/V CB = 1 µF CB = 0.1 µF 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V PO = 350 mW RL = 8 Ω AV = −20 V/V CB = 1 µF CB = 0.1 µF 0.1 0.01 100 1 k 10 k 20 k f − Frequency − Hz THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V AV = −10 V/V Single Ended RL = 32 Ω PO = 60 mW RL = 8 Ω PO = 250 mW TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY Figure 15. Figure 16. TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY Figure 17. Figure 18.

www.ti.com 0.02 0.1 0.01 0.1 1 PO − Output Power − W THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V AV = −2 V/V RL = 8 Ω f = 20 Hz CB = 0.1 µF CB = 1.0 µF 0.02 0.1 0.01 0.1 1 PO − Output Power − W THD+N − Total Harmonic Distortion Plus Noise − % VDD = 3.3 V AV = −2 V/V RL = 8 Ω f = 1 kHz CB = 0.1 µF CB = 1 µF 20 m 0.1 0.01 0.1 1 PO − Output Power − W THD+N − Total Harmonic Distortion Plus Noise − %VDD = 3.3 V AV = −2 V/V RL = 8 Ω f = 20 kHz CB = 1 µF CB = 0.1 µF − Supply Current − mAIDD 2.5 3 3.5 VDD − Supply Voltage − V 4 4.5 5 5.5 TA = 0° C TA = 85° C TA = 25° C TA = −40° C TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER Figure 19. Figure 20. TOTAL HARMONIC DISTORTION NOISE SUPPLY CURRENT vs vs OUTPUT POWER SUPPLY VOLTAGE Figure 21. Figure 22.

www.ti.com 103 102 101 100 1 k 10 k 20 k f − Frequency − Hz VDD = 5 V V01 +V02 V01 V02 − Output Noise Voltage − Vn Vµ 103 102 101 100 1 k 10 k 20 k f − Frequency − Hz VDD = 3.3 V V02 V01 V01 +V02 − Output Noise Voltage − Vn Vµ 0.4 0.2 −25 0 25 50 75 0.6 0.8 100 TA − Free-Air Temperature − ° C Maximum Package Power Dissipation − W −50 0.75 0.5 0 0.75 PO − Output Power − W 0.25 0.5 1 1.25 VDD = 5 V 0.25 RL = 8 Ω RL = 16 Ω PD − Power Dissipation − W TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 OUTPUT NOISE VOLTAGE OUTPUT NOISE VOLTAGE vs vs FREQUENCY FREQUENCY Figure 23. Figure 24. MAXIMUM PACKAGE POWER DISSIPATION POWER DISSIPATION vs vs FREE-AIR TEMPERATURE OUTPUT POWER Figure 25. Figure 26.

www.ti.com 0.5 0.3 0.2 0 0.5 PO − Output Power − W 0.1 0.4 VDD = 3.3 V 0.4 RL = 8 Ω RL = 16 Ω 0.1 0.2 0.3 PD − Power Dissipation − W 160 0 0.25 1.50.5 0.75 1 − Free-Air Temperature − PO − Maximum Output Power − W 1.25 C°TA 120 100 140 RL = 16 Ω RL = 8 Ω − Power Output − W 1.4 0.8 0.4 8 20 36 Load Resistance − Ω 12 16 24 28 32 0.6 0.2 VDD = 5 V VDD = 3.3 V PO AV = −2 V/V f = 1 kHz CB = 0.1 µF THD+N ≤ 1% 1.2 4840 44 − Power Output − W 1.75 0.5 3.5 5 Supply Voltage − V 4 4.5 5.5 1.25 0.75 0.25 PO 1.5 AV = −2 V/V f = 1 kHz CB = 0.1 µF THD+N ≤ 1% 2.5 RL = 8 Ω RL = 4 Ω RL = 16 Ω TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 POWER DISSIPATION MAXIMUM OUTPUT POWER vs vs OUTPUT POWER FREE-AIR TEMPERATURE Figure 27. Figure 28. OUTPUT POWER OUTPUT POWER vs vs LOAD RESISTANCE SUPPLY VOLTAGE Figure 29. Figure 30.

www.ti.com Open-Loop Gain − dB 100 −20 100 100 k f − Frequency − Hz VDD = 5 V RL = 8 Ω CB = 0.1 µF 1 k 10 k 1 M 10 M 45° −45° −135° −225° −90° −180° Phase Gain Phase 100 −90 −100 1 k 10 k 20 k f − Frequency − Hz CB = 0.1 µF CB = 1 µF −80 −70 −60 −50 −40 −30 −20 −10 VDD = 5 V RL = 8 Ω Bridge-Tied Load k SVR − Supply Ripple Rejection Ratio − dB 100 −90 −100 1 k 10 k 20 k f − Frequency − Hz CB = 0.1 µF CB = 1 µF −80 −70 −60 −50 −40 −30 −20 −10 VDD = 5 V RL = 8 Ω Single Ended k SVR − Supply Ripple Rejection Ratio − dB TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 OPEN-LOOP GAIN SUPPLY RIPPLE REJECTION RATIO vs vs FREQUENCY FREQUENCY Figure 31. Figure 32. SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY Figure 33.

www.ti.com APPLICATION INFORMATION BRIDGED-TIED LOAD VERSUS SINGLE-ENDED MODE Power V(rms) RL V(rms) VO(PP) 2 2 (1) RL 2x VO(PP) VO(PP) ±VO(PP) VDD VDD f(corner) 1 2RLCC (2) TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 Figure shows a linear audio power amplifier (APA) in a bridge-tied load (BTL) configuration. A BTL amplifier actually consists of two linear amplifiers driving both ends of the load. There are several potential benefits to this differential drive configuration, but initially, let us consider power to the load. The differential drive to the speaker means that as one side is slewing up the other side is slewing down and vice versa. This, in effect, doubles the voltage swing on the load as compared to a ground-referenced load. Plugging twice the voltage into the power equation, where voltage is squared, yields times the output power from the same supply rail and load impedance (see Equation Figure 34. Bridge-Tied Load Configuration In a typical computer sound channel operating at bridging raises the power into an Ω speaker from a singled-ended (SE) limit of 250 mW to In sound power that is a 6-dB improvement, which is loudness that can be heard. In addition to increased power, frequency response is a concern; consider the single-supply SE configuration shown in Figure A coupling capacitor is required to block the dc offset voltage from reaching the load. These capacitors can be quite large (approximately µ F to 1000 µ so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system. This frequency-limiting effect is due to the high-pass filter network created with the speaker impedance and the coupling capacitance and is calculated with Equation For example, a 68- µ F capacitor with an Ω speaker would attenuate low frequencies below 293 Hz. The BTL configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency performance is then limited only by the input network and speaker response. Cost and PCB space are also minimized by eliminating the bulky coupling capacitor.

www.ti.com RL CC VO(PP) VO(PP) VDD BTL AMPLIFIER EFFICIENCY VL(RMS) VO IDD IDD(RMS) TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 APPLICATION INFORMATION (continued) Figure 35. Single-Ended Configuration Increasing power to the load does carry a penalty of increased internal power dissipation. The increased dissipation is understandable considering that the BTL configuration produces times the output power of the SE configuration. Internal dissipation versus output power is discussed further in the thermal considerations section. Linear amplifiers are notoriously inefficient. The primary cause of these inefficiencies is voltage drop across the output stage transistors. The internal voltage drop has two components. One is the headroom or dc voltage drop that varies inversely to output power. The second component is due to the sine-wave nature of the output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from V DD The internal voltage drop multiplied by the RMS value of the supply current, I DD(RMS) determines the internal power dissipation of the amplifier. An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. To accurately calculate the RMS values of power in the load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure Figure 36. Voltage and Current Waveforms for BTL Amplifiers Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are different between SE and BTL configurations. In an SE application, the current waveform is a half-wave rectified shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different. Keep in mind that for most of the waveform, both the push and pull transistor are not on at the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform. The following equations are the basis for calculating amplifier efficiency.

www.ti.com IDDRMS 2VP RL PSUP VDD IDDRMS VDD 2VP RL Efficiency PL PSUP Where: PL VLRMS RL Vp 2RL VLRMS VP (3) Efficiency of a BTL configuration VP 2VDD PLRL 2VDD (4) TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 APPLICATION INFORMATION (continued) Table employs Equation to calculate efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased, resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1-W audio system with Ω loads and a 5-V supply, the maximum draw on the power supply is almost 3.25 Table Efficiency Vs Output Power in 5-V Ω BTL Systems PEAK-TO-PEAK INTERNAL OUTPUT POWER EFFICIENCY VOLTAGE DISSIPATION (W) (%) (V) (W) 0.25 31.4 2.00 0.55 0.50 44.4 2.83 0.62 1.00 62.8 4.00 0.59 1.25 70.2 4.47 (1) 0.53 (1) High peak voltages cause the THD to increase. A final point to remember about linear amplifiers, whether they are SE or BTL configured, is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in Equation V DD is in the denominator. This indicates that as V DD goes down, efficiency goes up. For example, if the 5-V supply is replaced with a 10-V supply (TPA4861 has a maximum recommended V DD of 5.5 in the calculations of Table then efficiency at W would fall to 31% and internal power dissipation would rise to 2.18 W from 0.59 W at Then for a stereo 1-W system from a 10-V supply, the maximum draw would be almost 6.5 Choose the correct supply voltage and speaker impedance for the application.

www.ti.com SELECTION OF COMPONENTS Audio Input Bias Control VDD = 5 V 1-W Internal Speaker VO1 VO2 VDD IN+ IN− BYPASS SHUTDOWN (see Note A) VDD/2 CI RI RFCF 50 kΩ 50 kΩ 46 kΩ 46 kΩCB CS NOTE A: SHUTDOWN must be held low for normal operation and asserted high for shutdown mode. Gain Setting Resistors, R F and R I Gain 2 RF RI (5) Effective Impedance RFRI RF RI (6) TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 Figure is a schematic diagram of a typical notebook computer application circuit. Figure 37. TPA4861 Typical Notebook Computer Application Circuit The gain for the TPA4861 is set by resistors R F and R I according to Equation BTL mode operation brings about the factor of in the gain equation due to the inverting amplifier mirroring the voltage swing across the load. Given that the TPA4861 is a MOS amplifier, the input impedance is high; consequently, input leakage currents are not generally a concern, although noise in the circuit increases as the value of R F increases. In addition, a certain range of R F values are required for proper start-up operation of the amplifier. Taken together, it is recommended that the effective impedance seen by the inverting node of the amplifier be set between k Ω and k Ω The effective impedance is calculated in Equation As an example, consider an input resistance of k Ω and a feedback resistor of k Ω The gain of the amplifier would be V/V, and the effective impedance at the inverting terminal would be 8.3 k Ω which is well within the recommended range. For high-performance applications, metal film resistors are recommended because they tend to have lower noise levels than carbon resistors. For values of R F above k Ω the amplifier tends to become unstable due to a pole formed from R F and the inherent input capacitance of the MOS input structure. For this reason, a small compensation capacitor of approximately pF should be placed in parallel with R F This, in effect, creates a low-pass filter network with the cutoff frequency defined in Equation

www.ti.com fco(lowpass) 1 2RFCF (7) Input Capacitor, C I fco(highpass) 1 2RICI (8) CI 1 2RIfco (9) Power Supply Decoupling, C S Midrail Bypass Capacitor, C B CB 25 kΩ CIRI (10) TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 For example if R F is 100 k Ω and C F is pF, then f co is 318 kHz, which is well outside of the audio range. In the typical application, an input capacitor, C I is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, C I and R I form a high-pass filter with the corner frequency determined in Equation The value of C I is important to consider, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where R I is k Ω and the specification calls for a flat bass response down to Hz. Equation is reconfigured as Equation In this example, C I is 0.40 µ so, one would likely choose a value in the range of 0.47 µ F to µ A further consideration for this capacitor is the leakage path from the input source through the input network I C I and the feedback resistor F to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high-gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most V DD /2, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. The TPA4861 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µ F placed as close as possible to the device V DD lead, works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of µ F or greater placed near the power amplifier is recommended. The midrail bypass capacitor, C B serves several important functions. During start-up or recovery from shutdown mode, C B determines the rate at which the amplifier starts up. This helps to push the start-up pop noise into the subaudible range (so slow it cannot be heard). The second function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier. The capacitor is fed from a 25-k Ω source inside the amplifier. To keep the start-up pop as low as possible, the relationship shown in Equation should be maintained. As an example, consider a circuit where C B is 0.1 µ C I is 0.22 µ F and R I is k Ω Inserting these values into the Equation we get 400 454 which satisfies the rule. Bypass capacitor, C B values of 0.1- µ F to µ F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance.

www.ti.com SINGLE-ENDED OPERATION Audio Input VDD VO1 VO2 VDD IN+ IN− BYPASS VDD/2 CI RI RF CS CB 250-mW External Speaker CSE = 0.1 µF RSE = 50 Ω CC Gain RF RI (11) CB 25 kΩ CIRI RLCC (12) OUTPUT COUPLING CAPACITOR, C C fout high 1 2RLCC (13) TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 Figure is a schematic diagram of the recommended SE configuration. In SE mode configurations, the load should be driven from the primary amplifier output O terminal 5). Figure 38. Singled-Ended Mode Gain is set by the R F and R I resistors and is shown in Equation Because the inverting amplifier is not used to mirror the voltage swing on the load, the factor of is not included. The phase margin of the inverting amplifier into an open circuit is not adequate to ensure stability, so a termination load should be connected to V O This consists of a 50- Ω resistor in series with a 0.1- µ F capacitor to ground. It is important to avoid oscillation of the inverting output to minimize noise and power dissipation. The output coupling capacitor required in single-supply SE mode also places additional constraints on the selection of other components in the amplifier circuit. The rules described earlier still hold with the addition of the following relationship: In the typical single-supply SE configuration, an output coupling capacitor C is required to block the dc bias at the output of the amplifier thus preventing dc currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by Equation The main disadvantage, from a performance standpoint, is that the load impedances are typically small, which drives the low-frequency corner higher. Large values of C C are required to pass low frequencies into the load. Consider the example where a C C of µ F is chosen and loads vary from Ω Ω and k Ω Table summarizes the frequency response characteristics of each configuration.

www.ti.com SHUTDOWN MODE USING LOW-ESR CAPACITORS THERMAL CONSIDERATIONS 160 0 0.25 1.50.5 0.75 1 ± Free-Air Temperature ± PO ± Maximum Output Power ± W 1.25 C°TA 120 100 140 RL = 16 Ω RL = 8 Ω VDD = 5 V TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 Table Common Load Impedances vs Low-Frequency Output Characteristics in SE Mode R L C C LOWEST FREQUENCY Ω µ F 293 Hz Ω µ F Hz 47,000 Ω µ F 0.05 Hz As Table indicates, most of the bass response is attenuated into Ω loads, while headphone response is adequate and drive into line level inputs home stereo for example) is good. The TPA4861 employs a shutdown mode of operation designed to reduce supply current, I DD(q) to the absolute minimum level during periods of nonuse for battery-power conservation. For example, during device sleep modes or when other audio-drive currents are used (i.e., headphone mode), the speaker drive is not required. The SHUTDOWN input terminal should be held low during normal operation when the amplifier is in use. Pulling SHUTDOWN high causes the outputs to mute and the amplifier to enter a low-current state, I DD(SD) 0.6 µ SHUTDOWN should never be left unconnected because amplifier operation would be unpredictable. Low-ESR capacitors are recommended throughout this section. A real capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. A prime consideration when designing an audio amplifier circuit is internal power dissipation in the device. The curve in Figure provides an easy way to determine what output power can be expected out of the TPA4861 for a given system ambient temperature in designs using 5-V supplies. This curve assumes no forced airflow or additional heat sinking. Figure 39. Free-Air Temperature vs Maximum Continuous Output Power

www.ti.com 5-V VERSUS 3.3-V OPERATION TPA4861 SLOS163C SEPTEMBER 1996 REVISED JUNE 2004 The TPA4861 was designed for operation over a supply range of 2.7 V to 5.5 This data sheet provides full specifications for 5-V and 3.3-V operation, as these are considered to be the two most common standard voltages. There are no special considerations for 3.3-V versus 5-V operation as far as supply bypassing, gain setting, or stability. Supply current is slightly reduced from 3.5 mA (typical) to 2.5 mA (typical). The most important consideration is that of output power. Each amplifier in TPA4861 can produce a maximum voltage swing of V DD This means, for 3.3-V operation, clipping starts to occur when V O(PP) 2.3 V as opposed to when V O(PP) V while operating at The reduced voltage swing subsequently reduces maximum output power into an Ω load to less than 0.33 W before distortion begins to become significant. Operation at 3.3-V supplies, as can be shown from the efficiency formula in Equation consumes approximately two-thirds of the supply power for a given output-power level than operation from 5-V supplies. When the application demands less than 500 mW, 3.3-V operation should be strongly considered, especially in battery-powered applications.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPA4861D Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 4861 TPA4861D.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 4861 TPA4861DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 4861 TPA4861DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 4861 TPA4861DRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 4861 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA4861DR SOIC D 8 2500 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPA4861D D SOIC 8 75 505.46 6.76 3810 4 TPA4861D.A D SOIC 8 75 505.46 6.76 3810 4 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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