TPA3101D2RGZTG4

TPA3101D2_07 TI | Alldatasheet

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Simplified Application Circuit TV Audio Processor RINP BSRN BSRP VCLAMPR VCLAMPL PGNDR PGNDL VREG VBYP ROSC BSLN ROUTN LOUTN LOUTP BSLP ROUTP TPA3101D2 LINN RINN LINP MUTE GAIN0 GAIN1 SYNC FAULT PVCCR PVCCL AVCC AGND MSTR/SLV SHUTDOWNShutdown Control Mute Control Sync Control Fault Flag

10 V to 26 V

0.22 Fm 0.22 Fm 0.22 Fm 0.22 Fm 1 Fm 1 Fm 1 Fm TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 10-W STEREO CLASS-D AUDIO POWER AMPLIFIER Televisions 10-W/ch into an Ω Load From a 13-V Supply 9.2-W/ch into an Ω Load From a 12-V Supply Operates from V to V The TPA3101D2 is a 10-W (per channel) efficient, 87% Efficient Class-D Operation Eliminates Class-D audio power amplifier for driving bridged-tied Need for Heat Sinks stereo speakers. The TPA3101D2 can drive stereo Four Selectable, Fixed Gain Settings speakers as low as Ω The high efficiency of the Differential Inputs TPA3101D2, 87%, eliminates the need for an external heat sink when playing music. Thermal and Short-Circuit Protection With Auto Recovery Feature The gain of the amplifier is controlled by two gain select pins. The gain selections are 20, 26, 32, Clock Output for Synchronization With dB. Multiple Class-D Devices The outputs are fully protected against shorts to Surface Mount mm mm, 48-pin QFN GND, V CC and output-to-output shorts with an auto Package recovery feature and monitor output. Surface Mount mm mm, 48-pin HTQFP Package Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2005 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS TYPICAL DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. over operating free-air temperature range (unless otherwise noted) (1) UNIT V CC Supply voltage AVCC, PVCC 0.3 V to V SHUTDOWN MUTE 0.3 V to V CC 0.3 V V I Input voltage GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/ SLV 0.3 V to VREG 0.5 V SYNC Continuous total power dissipation See Dissipation Rating Table T A Operating free-air temperature range C to C T J Operating junction temperature range (2) C to 150 C T stg Storage temperature range C to 150 C Lead temperature 1,6 mm (1/16 inch) from case for seconds 260 C R (Load) Load Resistance 3.2 Ω Minimum Human body model (3) (all pins) kV Electrostatic discharge Machine model (4) (all pins) 200 V Charged-device model (5) (all pins) 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The TPA3101D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad. (3) In accordance with JEDEC Standard 22, Test Method A114-B. (4) In accordance with JEDEC Standard 22, Test Method A115-A (5) In accordance with JEDEC Standard 22, Test Method C101-A PACKAGE T A C DERATING FACTOR T A C T A C 48-pin RGZ (QFN) 4.39 W 35.1 mW/ C (1) 2.81 W 2.28 W 48-pin PHP (HTQFP) 4.82 W 38.6 mW/ C (2) 3.09 W 2.51 W (1) This data was taken using oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. (2) This data was taken using oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT V CC Supply voltage PVCC, AVCC V SHUTDOWN MUTE, GAIN0, GAIN1, MSTR/ SLV V IH High-level input voltage V SYNC SHUTDOWN MUTE, GAIN0, GAIN1, MSTR/ SLV V IL Low-level input voltage 0.8 V SYNC SHUTDOWN V I V CC V CC V 125 MUTE, V I V CC V CC V I IH High-level input current µ A GAIN0, GAIN1, MSTR/ SLV SYNC, V I VREG, V CC V Submit Documentation Feedback

www.ti.com DC CHARACTERISTICS DC CHARACTERISTICS TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT SHUTDOWN V I V CC V I IL Low-level input current µ A SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, V I V CC V V OH High-level output voltage FAULT, I OH mA VREG 0.6 V V OL Low-level output voltage FAULT, I OL mA AGND 0.4 V f OSC Oscillator frequency R osc Resistor 100 k Ω 200 300 kHz T A Operating free-air temperature C T A V CC R L Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Class-D output offset voltage (measured V OS V I Gain dB mV differentially) Bypass reference for input amplifier VBYP, no load 1.1 1.25 1.45 V 4-V internal supply voltage VREG, no load, V CC V to V 3.75 4.25 V V CC V to inputs ac coupled to AGND, PSRR DC Power supply rejection ratio -70 dB Gain dB I CC Quiescent supply current SHUTDOWN MUTE no load 26.5 mA I CC(SD) Quiescent supply current in shutdown mode SHUTDOWN 0.8 no load 300 400 µ A I CC(MUTE) Quiescent supply current in mute mode MUTE no load mA High Side 370 V CC I O 500 mA, r DS(on) Drain-source on-state resistance Low side 370 m Ω T J C Total 780 950 GAIN0 0.8 V GAIN1 0.8 V dB GAIN0 V G Gain GAIN0 0.8 V GAIN1 V dB GAIN0 V Gain matching Between channels t ON Turn-on time C (VBYP) µ SHUTDOWN V ms t OFF Turn-off time C (VBYP) µ SHUTDOWN 0.8 V 0.1 ms T A V CC R L Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Class-D output offset voltage (measured V OS V I Gain dB mV differentially) Bypass reference for input amplifier VBYP, no load 1.1 1.25 1.45 V 4-V internal supply voltage VREG, no load 3.75 4.25 V V CC V to Inputs ac coupled to AGND, PSRR DC Power supply rejection ratio -70 dB Gain dB I CC Quiescent supply current SHUTDOWN MUTE no load 22.5 mA I CC(SD) Quiescent supply current in shutdown mode SHUTDOWN 0.8 no load 180 300 µ A I CC(MUTE) Quiescent supply current in mute mode MUTE no load mA High Side 370 V CC I O 500 mA, r DS(on) Drain-source on-state resistance Low side 370 m Ω T J C Total 780 950 Submit Documentation Feedback

www.ti.com AC CHARACTERISTICS AC CHARACTERISTICS TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 DC CHARACTERISTICS (continued) T A V CC R L Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GAIN0 0.8 V GAIN1 0.8 V dB GAIN0 V G Gain GAIN0 0.8 V GAIN1 V dB GAIN0 V t ON Turn-on time C (VBYP) µ SHUTDOWN V ms t OFF Turn-off time C (VBYP) µ SHUTDOWN 0.8 V 0.1 ms T A V CC R L Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 mV PP ripple from Hz kHz, K SVR Supply ripple rejection dB Gain dB, Inputs ac-coupled to AGND P O Continuous output power THD+N 0.09%, f kHz (thermally limited) W THD+N Total harmonic distortion noise f kHz, P O W (half-power) 0.09% 100 µ V V n Output integrated noise Hz to kHz, A-weighted filter, Gain dB dBV Crosstalk V O Vrms, Gain dB, f kHz dB Maximum output at THD+N 1%, f kHz, SNR Signal-to-noise ratio 102 dB Gain dB, A-weighted Thermal trip point 150 C Thermal hysteresis C T A V CC R L Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 mV PP ripple from Hz kHz, K SVR Supply ripple rejection dB Gain dB, Inputs ac-coupled to AGND THD+N 7%, f kHz 8.7 THD+N 10%, f kHz 9.2 P O Continuous output power W THD+N 10%, f kHz, V CC V THD+N 0.26%, f kHz, R L Ω (thermally limited) THD+N Total harmonic distortion noise R L Ω f kHz, P O 4.5 W (half-power) 0.08% R L Ω f kHz, P O W (half-power) 0.11% 100 µ V V n Output integrated noise Hz to kHz, A-weighted filter, Gain dB dBV Crosstalk P o Gain dB, f kHz dB Maximum output at THD+N 1%, f kHz, SNR Signal-to-noise ratio dB Gain dB, A-weighted Thermal trip point 150 C Thermal hysteresis C Submit Documentation Feedback

www.ti.com 325 2710 2512 PVCCRRINP PGNDRAGND AVCC NC MUTE VBYP ROUTP LOUTP NC NC BSRN BSLNLOUTN ROUTNFAUL T VREG SHUTDOWN AGND NC ROSC BSRP BSLP ROUTP ROUTN LOUTNLOUTP PVCCR Exposed Thermal Pad RINN NCNC NCNC PGNDRLINP VCLAMPRLINN VCLAMPLNC PGNDLGAIN0 PGNDLGAIN1 PVCCLMSTR/SLV PVCCLSYNC 334 289 2611 343 298 352 307 361 316 AVCCAVCCFAUL T MUTESHUTDOWNBSRP ROUTP ROUTP ROUTN ROUTN BSRN GND GND PVCCR PVCCR PGNDR VCLAMPR VCLAMPL PGNDL PVCCL PVCCL GND GND RINN RINP AGND LINP LINN GAIN0 GAIN1 MSTR/SLV SYNC GND GNDROSCVREGVBYPAGNDBSLPLOUTP LOUTPLOUTN LOUTNBSLNGND PGNDR PGNDL GAIN0 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 Exposed Thermal Pad TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 PIN, QFN PACKAGE PIN, HTQFP PACKAGE (TOP VIEW) (TOP VIEW) TERMINAL FUNCTIONS TERMINAL I/O NO. NO. Shutdown signal for IC (LOW disabled, HIGH operational). TTL logic SHUTDOWN I levels with compliance to AVCC. RINN I Negative audio input for right channel. Biased at VREG/2. RINP I Positive audio input for right channel. Biased at VREG/2. LINN I Negative audio input for left channel. Biased at VREG/2. LINP I Positive audio input for left channel. Biased at VREG/2. GAIN0 I Gain select least significant bit. TTL logic levels with compliance to VREG. GAIN1 I Gain select most significant bit. TTL logic levels with compliance to VREG. 12, 13, GND 24, 25, 36, Connect to the thermal pad. Mute signal for quick disable/enable of outputs (HIGH outputs high-Z, MUTE I LOW outputs enabled). TTL logic levels with compliance to AVCC. TTL compatible output. HIGH short-circuit fault. LOW no fault. Only FAULT O reports short-circuit faults. Thermal faults are not reported on this terminal. BSLP I/O Bootstrap I/O for left channel, positive high-side FET. Power supply for left channel H-bridge, not internally connected to PVCCR PVCCL 26, 26, or AVCC. LOUTP 19, 19, O Class-D 1/2-H-bridge positive output for left channel. PGNDL 28, 28, Power ground for left channel H-bridge. LOUTN 21, 21, O Class-D 1/2-H-bridge negative output for left channel. BSLN I/O Bootstrap I/O for left channel, negative high-side FET. VCLAMPL Internally generated voltage supply for left channel bootstrap capacitor. VCLAMPR Internally generated voltage supply for right channel bootstrap capacitor. BSRN I/O Bootstrap I/O for right channel, negative high-side FET. ROUTN 39, 39, O Class-D 1/2-H-bridge negative output for right channel. PGNDR 32, 32, Power ground for right channel H-bridge. Submit Documentation Feedback

www.ti.com TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 TERMINAL FUNCTIONS (continued) TERMINAL I/O NO. NO. ROUTP 41, 41, O Class-D 1/2-H-bridge positive output for right channel. PVCCR 34, 34, Power supply for right channel H-bridge, not connected to PVCCL or AVCC. BSRP I/O Bootstrap I/O for right channel, positive high-side FET. AGND Analog ground for digital/analog cells in core. ROSC I/O I/O for current setting resistor of ramp generator. Master/Slave select for determining direction of SYNC terminal. HIGH=Master mode, SYNC terminal is an output; LOW slave mode, MSTR/ SLV I SYNC terminal accepts a clock input. TTL logic levels with compliance to VREG. Clock input/output for synchronizing multiple class-D devices. Direction SYNC I/O determined by MSTR/ SLV terminal. Input signal not to exceed VREG. Reference for preamplifier. Nominally equal to 1.25 Also controls start-up VBYP O time via external capacitor sizing. 4-V regulated output for use by internal cells, GAINx, MUTE, and VREG O MSTR/ SLV pins only. Not specified for driving other external circuitry. High-voltage analog power supply. Not internally connected to PVCCR or AVCC 47, PVCCL. 12, NC 13, 24, 25, Not internally connected. 36, 37, Connect to AGND and PGND should be star point for both grounds. Internal resistive connection to AGND and PGND. Thermal vias on the PCB Thermal Pad should connect this pad to a large copper area on an internal or bottom layer for the best thermal performance. The Thermal Pad must be soldered to the PCB for mechanical reliability. Submit Documentation Feedback

www.ti.com Biases and References Startup Protection Logic VREGok RINP RINN Ramp Generator ROSC VCCok 4V Reg AVCC VREG PWM Logic Gain Control Gain Control LINP LINN SHUTDOWN VBYP VBYP MSTR/SLV PWM Logic SYNC AVCC AVCC AVCC Gain Control GAIN0 GAIN1 8 To Gain Adj. Blocks and Startup Logic MUTE FAULT VREG AGND VBYP VBYP VREG VBYP VClamp Gen PVCCR Gate Drive Gate Drive VClamp Gen Gate Drive Thermal SC Detect PVCCR Gate Drive BSLN VCLAMPL PVCCL PVCCL BSLP LOUTN BSRN VCLAMPR PVCCR PVCCR ROUTN BSRP ROUTP PGNDR PVCCL PVCCL PGNDL LOUTP Gain Gain Gain Gain TLL Input Buffer (VCC Compliant) TLL Input Buffer (VCC Compliant) TYPICAL CHARACTERISTICS TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 FUNCTIONAL BLOCK DIAGRAM TABLE OF GRAPHS (1) FIGURE THD+N Total harmonic distortion noise vs Frequency THD+N Total harmonic distortion noise vs Output power Closed-loop response vs Frequency Output power vs Supply voltage 11. Efficiency vs Output power 13, V CC Supply current vs Total output power 15, Crosstalk vs Frequency 17, k SVR Supply ripple rejection ratio vs Frequency 19, (1) All graphs were measured using the TPA3101D2 EVM. Submit Documentation Feedback

www.ti.com f ! Frequency ! Hz VCC = 12 V RL = 8 " Gain = 20 dB 100 1k 10k THD+N Total Harmonic Distortion + Noise 0.005 0.1 20k 0.01 PO = 2.5 W PO = 1 W PO = 5 W f ! Frequency ! Hz VCC = 18 V RL = 8 " Gain = 20 dB 100 1k 10k THD+N Total Harmonic Distortion + Noise 0.005 0.1 20k 0.01 PO = 2.5 W PO = 1 W PO = 5 W f ! Frequency ! Hz VCC = 24 V RL = 8 " Gain = 20 dB 100 1k 10k THD+N Total Harmonic Distortion + Noise 0.005 0.1 20k 0.01 PO = 10 W PO = 1 W PO = 5 W f ! Frequency ! Hz VCC = 12 V RL = 4 " Gain = 20 dB 100 1k 10k THD+N Total Harmonic Distortion + Noise 0.005 0.1 20k 0.01 PO = 2.5 W PO = 1 W TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY Figure Figure TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREQUENCY FREQUENCY Figure Figure Submit Documentation Feedback

www.ti.com 0.1 0.01 PO ! Output Power ! W 10 m 100 m 1 10 20 THD+N Total Harmonic Distortion + Noise VCC = 12 V RL = 8 " Gain = 32 dB 1 kHz 20 Hz 10 kHz Power Beyond 10 W May Require More Heatsinking. 0.1 0.01 PO ! Output Power ! W 10 m 100 m 1 10 20 THD+N Total Harmonic Distortion + Noise 1 kHz 10 kHz 20 Hz VCC = 18 V RL = 8 " Gain = 32 dB Power Beyond 10 W May Require More Heatsinking. 0.1 0.01 PO ! Output Power ! W 10 m 100 m 1 10 20 THD+N Total Harmonic Distortion + Noise VCC = 24 V RL = 8 " Gain = 32 dB 1 kHz 20 Hz Power Beyond 10 W May Require More Heatsinking. 10 kHz 0.1 0.01 PO ! Output Power ! W 10 m 100 m 1 10 20 THD+N Total Harmonic Distortion + Noise VCC = 12 V RL = 4 " Gain = 32 dB Power Beyond 10 W May Require More Heatsinking. 1 kHz 20 Hz 10 kHz TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER Figure Figure TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs OUTPUT POWER OUTPUT POWER Figure Figure Submit Documentation Feedback

www.ti.com -200 200 -150 -100 -50 100 150 f - Frequency - Hz 10 100 1 k 10 k 100 k Gain dB Phase o Gain Phase V = 12 V R = 8 V = 0.1 V C = 10 F Gain = 32 dB RC filter = 100 , 10 nF CC L I rms I W m W -200 200 -150 -100 -50 100 150 f - Frequency - Hz 10 100 1 k 10 k 100 k Gain dB Phase o Gain Phase V = 24 V R = 8 V = 0.1 V C = 10 F Gain = 32 dB RC filter = 100 , 10 nF CC L I rms I W m W V - Supply Voltage - VCC 7.5 12.5 17.5 22.5 27.5 32.5 37.5 10 12 14 16 18 20 22 24 26 P O Output Power W THD+N = 10% THD+N = 1% R = 8 Gain = 20 dB L W Power Beyond 10 W May Require More Heatsinking. V - Supply Voltage - VCC 10 11 12 13 P O Output Power W THD+N = 10% THD+N = 1% R = 4 Gain = 20 dB L W Power Beyond 10 W May Require More Heatsinking. TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE vs vs FREQUENCY FREQUENCY Figure Figure 10. OUTPUT POWER OUTPUT POWER vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Figure 11. Figure 12. Submit Documentation Feedback

www.ti.com PO ! Output Power (Per Channel) ! W 100 0 2 4 6 8 10 12 14 16 18 20 RL = 8 W Gain = 20 dB Efficiency VCC = 24 V V = 18 VCC VCC = 12 V PO ! Output Power (Per Channel) ! W 100 0 2 4 6 8 10 12 14 15 RL = 4 " Gain = 32 dB Efficiency VCC = 12 V PO ! Total Output Power ! W 0.5 1.5 2.5 0 10 20 30 40 RL = 8 " Gain = 32 dB ICC Supply Current A VCC = 24 V VCC = 12 V VCC = 18 V Power Beyond 10 W May Require More Heatsinking. PO ! Total Output Power ! W 0.5 1.5 2.5 0 10 20 30 40 RL = 4 " Gain = 32 dB ICC Supply Current A VCC = 12 V Power Beyond 10 W May Require More Heatsinking. TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 EFFICIENCY EFFICIENCY vs vs OUTPUT POWER OUTPUT POWER Figure 13. Figure 14. SUPPLY CURRENT SUPPLY CURRENT vs vs TOTAL OUTPUT POWER TOTAL OUTPUT POWER Figure 15. Figure 16. Submit Documentation Feedback

www.ti.com !140 !120 !100 !80 !60 -40 f ! Frequency ! Hz Crosstalk dB 20 100 1k 10k 20k VCC = 12 V RL = 8 " Gain = 20 dB V = 1 VrmsO L to R R to L !140 !120 !100 !80 !60 -40 f ! Frequency ! Hz Crosstalk dB 20 100 1k 10k 20k VCC = 24 V RL = 8 " Gain = 20 dB V = 1 VrmsO L to R R to L !100 !90 !80 !70 !60 !50 !40 !30 !20 !10 f ! Frequency ! Hz kSVR Supply Ripple Rejection Ratio dB 20 100 1k 10k 20k V = 12 VCC R = 8 Gain = 20 dB V = 200 mV L (RIPPLE) PP W !100 !90 !80 !70 !60 !50 !40 !30 !20 !10 f ! Frequency ! Hz kSVR Supply Ripple Rejection Ratio dB 20 100 1k 10k 20k V = 18 VCC R = 8 Gain = 20 dB V = 200 mV L (RIPPLE) PP W TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 CROSSTALK CROSSTALK vs vs FREQUENCY FREQUENCY Figure 17. Figure 18. SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO vs vs FREQUENCY FREQUENCY Figure 19. Figure 20. Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION TPA3101D2 GAIN1 LINP RINN RINP AGND LINN GAIN0 SYNC MSTR/SLV NC NC NC AVCC NC FAUL T MUTE SHUTDOWN BSRPROUTP ROUTP ROUTN ROUTNBSRN NC

10 V - 26 V

NC VREG VBYP AGND BSLP LOUTP LOUTP LOUTN LOUTN BSLN NCROSC 220nF 220nF 220nF 220nF PVCCR NC NC PGNDR PVCCR PGNDR VCLAMPR VCLAMPL PVCCL PGNDL PGNDL PVCCL 0.47 Fm 1 Fm 1 Fm 1 Fm 1 Fm 1 Fm 220 Fm 1 Fm 1 Fm 1 Fm 220 Fm 1 Fm 1 Fm 10 nF 100 kW 0.1 Fm 0.1 Fm Differential Analog Inputs 4-Step Gain Control Synchronize Multiple Class-D Devices 33 Hm 33 Hm 0.47 Fm 0.1 Fm 8 W 8 W 0.1 Fm TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 Figure 21. Stereo Class-D With Differential Inputs (QFN) Submit Documentation Feedback

www.ti.com TPA3101D2 GAIN1 LINP RINN RINP AGND LINN GAIN0 SYNC MSTR/SLV NC NC NC AVCC NC FAUL T MUTE SHUTDOWN BSRPROUTP ROUTP ROUTN ROUTNBSRN NC NC VREG VBYP AGND BSLP LOUTP LOUTP LOUTN LOUTN BSLN NCROSC 220nF 220nF 220nF 220nF PVCCR NC NC PGNDR PVCCR PGNDR VCLAMPR VCLAMPL PVCCL PGNDL PGNDL PVCCL 0.47 Fm 1 Fm 1 Fm 1 Fm 1 Fm 1 Fm 220 Fm 1 Fm 1 Fm 1 Fm 220 Fm 1 Fm 1 Fm 10 nF 100 kW 0.1 Fm 0.1 Fm Single-Ended Analog Inputs 4-Step Gain Control Synchronize Multiple Class-D Devices 33 Hm 33 Hm 0.47 Fm 0.1 Fm 8 W 8 W 0.1 Fm TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) Figure 22. Stereo Class-D With Single-Ended Inputs (QFN) Submit Documentation Feedback

www.ti.com TPA3101D2 GAIN1 LINP RINN RINP AGND LINN GAIN0 SYNC MSTR/SLV GND GAIN0 GND AVCC AVCC FAUL T MUTE SHUTDOWN BSRPROUTP ROUTP ROUTN ROUTNBSRNGND GND VREG VBYP AGND BSLP LOUTP LOUTP LOUTN LOUTN BSLN GNDROSC 220nF 220nF 220nF 220nF PVCCR GND GND PGNDR PVCCR PGNDR VCLAMPR VCLAMPL PVCCL PGNDL PGNDL PVCCL 0.47 Fm 1 Fm 1 Fm 1 Fm 1 Fm 1 Fm 220 Fm 1 Fm 1 Fm 1 Fm 220 Fm 1 Fm 1 Fm 10 nF 100 kW 0.1 Fm 0.1 Fm Differential Analog Inputs 4-Step Gain Control Synchronize Multiple Class-D Devices 33 Hm 33 Hm 0.47 Fm 0.1 Fm 8 W 8 W 0.1 Fm TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) Figure 23. Stereo Class-D With Differential Inputs (HTQFP) Submit Documentation Feedback

www.ti.com TPA3101D2 GAIN1 LINP RINN RINP AGND LINN GAIN0 SYNC MSTR/SLV GND GAIN0 GND AVCC AVCC FAUL T MUTE SHUTDOWN BSRPROUTP ROUTP ROUTN ROUTNBSRNGND GND VREG VBYP AGND BSLP LOUTP LOUTP LOUTN LOUTN BSLN GNDROSC 220nF 220nF 220nF 220nF PVCCR GND GND PGNDR PVCCR PGNDR VCLAMPR VCLAMPL PVCCL PGNDL PGNDL PVCCL 0.47 Fm 1 Fm 1 Fm 1 Fm 1 Fm 1 Fm 220 Fm 1 Fm 1 Fm 1 Fm 220 Fm 1 Fm 1 Fm 10 nF 100 kW 0.1 Fm 0.1 Fm Single-Ended Analog Inputs 4-Step Gain Control Synchronize Multiple Class-D Devices 33 Hm 33 Hm 0.47 Fm 0.1 Fm 8 W 8 W 0.1 Fm TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) Figure 24. Stereo Class-D With Single-Ended Inputs (HTQFP) Submit Documentation Feedback

www.ti.com CLASS-D OPERATION Traditional Class-D Modulation Scheme 0 V -12 V +12 V Current OUTP Differential Voltage Across Load OUTN TPA3101D2 Modulation Scheme TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) This section focuses on the class-D operation of the TPA3101D2. The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, V CC Therefore, the differential prefiltered output varies between positive and negative V CC where filtered 50% duty cycle yields V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure Note that even at an average of V across the load (50% duty cycle), the current to the load is high, causing high loss and thus causing a high supply current. Figure 25. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an Inductive Load With No Input The TPA3101D2 uses a modulation scheme that still has each output switching from to the supply voltage. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at V throughout most of the switching period, greatly reducing the switching current, which reduces any I R losses in the load. Submit Documentation Feedback

www.ti.com 0 V -12 V +12 V Current OUTP OUTN Differential Voltage Across Load 0 V -12 V +12 V Current OUTP OUTN Differential Voltage Across Load Output = 0 V Output > 0 V Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme When to Use an Output Filter for EMI Suppression TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) Figure 26. The TPA3101D2 Output Voltage and Current Waveforms Into an Inductive Load The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is x V CC and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3101D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is V CC instead of x V CC As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency. Design the TPA3101D2 without the filter if the traces from amplifier to speaker are short cm). Powered speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter. Submit Documentation Feedback

www.ti.com 0.1 mF 0.1 mF 0.47 mF 33 Hm 33 mH OUTP OUTN 0.22 mF 0.22 mF 1 mF 15 Hm 15 mH OUTP OUTN 1 nF Ferrite Chip Bead OUTP OUTN Ferrite Chip Bead 1 nF TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) Most a ferrite bead filter. The ferrite filter reduces EMI around MHz and higher (FCC and CE only test radiated emissions greater than MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies. Use an LC output filter if there are low frequency MHz) EMI-sensitive circuits and/or there are long wires from the amplifier to the speaker. When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to the IC followed by the ferrite bead filter. Figure 27. Typical LC Output Filter, Cutoff Frequency of kHz, Speaker Impedance Ω Figure 28. Typical LC Output Filter, Cutoff Frequency of kHz, Speaker Impedance Ω Figure 29. Typical Ferrite Chip Bead Filter (Chip Bead Example: Fair-Rite 2512067007Y3) Submit Documentation Feedback

www.ti.com f ! Frequency ! Hz

30 M 230 M 430 M 630 M 830 M

dB( Vin) m National Technical Systems, Plano Tx Radiated Emissions 30 MHz - 1000 MHz FCC B FCC B Limit Peak dB TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) Using the LC filter in Figure the TPA3101D2 EMI EVM passed the FCC Part Class B radiated emissions with inch speaker wires. Quasi-peak measurements were taken for configurations, and the TPA3101D2 EMI EVM passed with at least a 5.6-dB margin. A plot of the peak measurement for the horizontal rear configuration is shown in Figure Figure 30. Radiated Emissions Prescan MHz 1000 MHz Submit Documentation Feedback

www.ti.com Adaptive Dynamic Range Control TPA3101D2 Closest Competitor t - Time = 100 s/divm V - V oltage = 10 V/div TPA3101D2 Closest Competitor t - Time = 20 s/divm V - V oltage = 1 V/div Gain setting via GAIN0 and GAIN1 inputs INPUT RESISTANCE TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) Figure 31. 1-kHz Sine Output at 10% THD+N Figure 32. 8-kHz Sine Output at 10% THD+N The Texas Instruments patent-pending adaptive dynamic range control (ADRC) technology removes the notch inherent in class-D audio power amplifiers when they come out of clipping. This effect is more severe at higher frequencies as shown in Figure The gain of the TPA3101D2 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance I to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by 20% due to shifts in the actual resistance of the input resistors. For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 12.8 k Ω which is the absolute minimum input impedance of the TPA3101D2. At the lower gain settings, the input impedance could increase as high as 38.4 k Ω Table Gain Setting INPUT IMPEDANCE AMPLIFIER GAIN (dB) Ω GAIN1 GAIN0 TYP TYP Changing the gain setting can vary the input resistance of the amplifier from its smallest value, k Ω 20%, to the largest value, k Ω 20%. As a result, if a single capacitor is used in the input high-pass filter, the dB or cutoff frequency may change when changing gain steps. Submit Documentation Feedback

www.ti.com Ci IN Zi Zf Input Signal f = 1

2 Z Cp i i (1)

CAPACITOR, C I f =c

2 Z Cp i i

-3 dB fc (2) C =i

2 Z fp i c

(3) Power Supply Decoupling, C S TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 The -3-dB frequency can be calculated using Equation Use the Z I values given in Table In the typical application, an input capacitor I is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, C I and the input impedance of the amplifier I form a high-pass filter with the corner frequency determined in Equation The value of C I is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where Z I is k Ω and the specification calls for a flat bass response down to Hz. Equation is reconfigured as Equation In this example, C I is 0.4 µ so, one would likely choose a value of 0.47 µ F as this value is commonly used. If the gain is known and is constant, use Z I from Table to calculate C I A further consideration for this capacitor is the leakage path from the input source through the input network I and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly. The TPA3101D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µ F to µ F placed as close as possible to the device V CC lead works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µ F or greater placed near the audio power amplifier is recommended. The 220 µ F capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220 µ F or larger capacitor should be placed on each PVCC terminal. A µ F capacitor on the AVCC terminal is adequate. Submit Documentation Feedback

www.ti.com BSN and BSP Capacitors VCLAMP Capacitors Internal Regulated 4-V Supply (VREG) VBYP Capacitor Selection ROSC Resistor Selection F =OSC 2 x ROSC x COSC (4) TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least must be connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be connected from xOUTP to BSxx, and one 220-nF capacitor must be connected from xOUTN to BSxx. (See the application circuit diagram in Figure The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two internal regulators clamp the gate voltage. Two µ F capacitors must be connected from VCLAMPL (pin 30) and VCLAMPR (pin 31) to ground and must be rated for at least The voltages at the VCLAMP terminals may vary with V CC and may not be used for powering any other circuitry. The VREG terminal (pin 15) is the output of an internally generated 4-V supply, used for the oscillator, preamplifier, and gain control circuitry. It requires a 10-nF capacitor, placed close to the pin, to keep the regulator stable. This regulated voltage can be used to control GAIN0, GAIN1, MSTR/ SLV and MUTE terminals, but should not be used to drive external circuitry. The internal bias generator (VBYP) nominally provides a 1.25-V internal bias for the preamplifier stages. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of the input preamplifiers. The selection of the capacitor value on the VBYP terminal is critical for achieving the best device performance. During power up or recovery from the shutdown state, the VBYP capacitor determines the rate at which the amplifier starts up. When the voltage on the VBYP capacitor equals VBYP, the device starts a 16.4-ms timer. When this timer completes, the outputs start switching. The charge rate of the capacitor is calculated using the standard charging formula for a capacitor, I C x dV/dT. The charge current is nominally equal to 250 µ A and dV is equal to VBYP. For example, a µ F capacitor on VBYP would take ms to reach the value of VBYP and begin a 16.4-ms count before the outputs turn on. This equates to a turn-on time of <30 ms for a µ F capacitor on the VBYP terminal. A secondary function of the VBYP capacitor is to filter high-frequency noise on the internal 1.25-V bias generator. A value of at least 0.47 µ F is recommended for the VBYP capacitor. For the best power-up and shutdown pop performance, the VBYP capacitor should be greater than or equal to the input capacitors. The resistor connected to the ROSC terminal controls the class-D output switching frequency using Equation COSC is an internal capacitor that is nominally equal to pF. Variation over process and temperature can result in a 15% change in this capacitor value. For example, if ROSC is fixed at 100 k Ω the frequency from device to device with this fixed resistance could vary from 217 kHz to 294 kHz with a 15% variation in the internal COSC capacitor. The tolerance of the ROSC resistor should also be considered to determine the range of expected switching frequencies from device to device. It is recommended that tolerance resistors be used. Submit Documentation Feedback

www.ti.com Differential Input SHUTDOWN OPERATION MUTE Operation MUTE FAULT External GPIO Control TPA3101D2 TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3101D2 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3101D2 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. The TPA3101D2 employs a shutdown mode of operation designed to reduce supply current CC to the absolute minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SHUTDOWN unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the power supply voltage. The MUTE pin is an input for controlling the output state of the TPA3101D2. A logic high on this terminal disables the outputs. A logic low on this pin enables the outputs. This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources. The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level. The MUTE terminal can also be used with the FAULT output to automatically recover from a short-circuit event. When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see Figure Figure 33. External MUTE Control Submit Documentation Feedback

www.ti.com MSTR/ SLV and SYNC operation USING LOW-ESR CAPACITORS TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 The MSTR/ SLV and SYNC terminals can be used to synchronize the frequency of the class-D output switching. When the MSTR/ SLV terminal is high, the output switching frequency is determined by the selection of the resistor connected to the ROSC terminal (see ROSC Resistor Selection). The SYNC terminal becomes an output in this mode, and the frequency of this output is also determined by the selection of the ROSC resistor. This TTL compatible, push-pull output can be connected to another TPA3101D2, configured in the slave mode. The output switching is synchronized to avoid any beat frequencies that could occur in the audio band when two class-D amplifiers in the same system are switching at slightly different frequencies. When the MSTR/ SLV terminal is low, the output switching frequency is determined by the incoming square wave on the SYNC input. The SYNC terminal becomes an input in this mode and accepts a TTL compatible square wave from another TPA3101D2 configured in the master mode or from an external GPIO. If connecting to an external GPIO, recommended frequencies are 200 kHz to 300 kHz for proper device operation, and the maximum amplitude is Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. Submit Documentation Feedback

www.ti.com SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE THERMAL PROTECTION PRINTED-CIRCUIT BOARD (PCB) LAYOUT TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 The TPA3101D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-V CC shorts. When a short circuit is detected on the outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the voltage on the SHUTDOWN pin or MUTE pin. This clears the short-circuit flag and allows for normal operation if the short was removed. If the short was not removed, the protection circuitry again activates. The FAULT terminal can be used for automatic recovery from a short-circuit event, or used to monitor the status with an external GPIO. For automatic recovery from a short-circuit event, connect the FAULT terminal directly to the MUTE terminal. When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see Figure Thermal protection on the TPA3101D2 prevents damage to the device when the internal die temperature exceeds 150 There is a C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by The device begins normal operation at this point with no external system interaction. Because the TPA3101D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance. Decoupling capacitors The high-frequency µ F decoupling capacitors should be placed as close to the PVCC (pins 26, 27, 34, and 35) and AVCC (pin 48) terminals as possible. The VBYP (pin 16) capacitor, VREG (pin 15) capacitor, and VCLAMP (pins and 31) capacitor should also be placed as close to the device as possible. Large (220 µ F or greater) bulk power supply decoupling capacitors should be placed near the TPA3101D2 on the PVCCL, PVCCR, and AVCC terminals. Grounding The AVCC (pin 48) decoupling capacitor, VREG (pin 15) capacitor, VBYP (pin 16) capacitor, and ROSC (pin 14) resistor should each be grounded to analog ground (AGND, pin 17). The PVCC decoupling capacitors and VCLAMP capacitors should each be grounded to power ground (PGND, pins 28, 29, 32, and 33). Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3101D2. Output filter The ferrite EMI filter Figure should be placed as close to the output terminals as possible for the best EMI performance. The LC filter Figure and Figure should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to power ground. If both filters are used, the LC filter should be placed first, following the outputs. Thermal Pad The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 5,1 mm by 5,1 mm. Five rows of solid vias (five vias per row, 0,3302 mm or mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad. For recommended PCB footprints, see figures at the end of this data sheet. For an example layout, see the TPA3101D2 Evaluation Module (TPA3101D2EVM) User Manual, (SLOU179). Both the EVM user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com. Submit Documentation Feedback

www.ti.com BASIC MEASUREMENT SYSTEM TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 This application note focuses on methods that use the basic equipment listed below: Audio analyzer or spectrum analyzer Digital multimeter (DMM) Oscilloscope Twisted-pair wires Signal generator Power resistor(s) Linear regulated power supply Filter components EVM or other complete audio circuit Figure shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine wave is normally used as the input signal because it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II) (Reference by Audio Precision includes the signal generator and analyzer in one package. The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, IN so no additional coupling is required. The generator output impedance should be low to avoid attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the analyzer-input impedance should be high. The output resistance, R OUT of the APA is normally in the hundreds of milliohms and can be ignored for all but the power-related calculations. Figure (a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal output. This amplifier circuit can be directly connected to the AP-II or other analyzer input. This is not true of the class-D amplifier system shown in Figure (b), which requires low-pass filters in most cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers. Submit Documentation Feedback

www.ti.com Analyzer

20 Hz - 20 kHz

(a) Basic Class-AB APASignal Generator Power Supply Analyzer

20 Hz - 20 kHzRL

(b) Filter-Free and Traditional Class-D Class-D APASignal Generator Power Supply RL Low-Pass RC Filter Low-Pass RC Filter (See note A) DIFFERENTIAL INPUT AND BTL OUTPUT TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 For efficiency measurements with filter-free Class-D, R L should be an inductive load like a speaker. Figure 34. Audio Measurement Systems The TPA3101D2 uses a modulation scheme that does not require an output filter for operation, but they do sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer can measure the output sine wave. All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor. A block diagram of the measurement circuit is shown in Figure The differential input is a balanced input, meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the BTL output equates to a balanced output. Submit Documentation Feedback

www.ti.com CIN Audio Power AmplifierGenerator Low-Pass RC Filter CIN RGEN RGEN RIN RIN VGEN ROUT ROUT Analyzer RANA RANA CANA Low-Pass RC Filter RL CANA Twisted-Pair Wire Evaluation Module Twisted-Pair Wire CLASS-D RC LOW-PASS FILTER TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 Figure 35. Differential Input, BTL Output Measurement Circuit The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in the circuit and providing the most accurate measurement. The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs: Use a balanced source to supply the input signal. Use an analyzer with balanced inputs. Use twisted-pair wire for all connections. Use shielding when the system environment is noisy. Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table Table shows the recommended wire size for the power supply and load cables of the APA system. The real concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch long wire with a 20-kHz sine-wave signal at Table Recommended Minimum Wire Size for Power Cables DC POWER LOSS AC POWER LOSS P OUT (W) R L Ω AWG Size (MW) (MW) 3.2 3.7 8.5 2.1 8.1 0.75 1.5 6.1 1.6 6.2 An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff frequency is set above the audio band. The high frequency of the square wave has negligible impact on measurement accuracy because it is well above the audible frequency range, and the speaker cone cannot respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx). The component values of the RC filter are selected using the equivalent output circuit as shown in Figure R L is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be available and substituted for R ANA and C ANA The filter components, R FILT and C FILT can then be derived for the system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin to minimize ground loops. Submit Documentation Feedback

www.ti.com RFILT RL RFILT CFILT VL= VIN VOUT RANACANA RANACANA CFILT To APA GND AP Analyzer InputRC Low-Pass FiltersLoad VOUT wVIN wO RANA + RFILT RANA 1 + j ( ( () ) = (5) f =c Ö2 x fmax (6) C =FILT 2 x f x Rp c FILT (7) TPA3101D2 SLOS473A DECEMBER 2005 REVISED FEBRUARY 2006 Figure 36. Measurement Low-Pass Filter Derivation Circuit-Class-D APAs The transfer function for this circuit is shown in Equation where ω O R EQ C EQ R EQ R FILT R ANA and C EQ FILT C ANA The filter frequency should be set above f MAX the highest frequency of the measurement bandwidth, to avoid attenuating the audio signal. Equation provides this cutoff frequency, f C The value of R FILT must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the attenuation of the analyzer-input voltage through the voltage divider formed by R FILT and R ANA A general rule is that R FILT should be small (~100 Ω for most measurements. This reduces the measurement error to less than for R ANA k Ω An exception occurs with the efficiency measurements, where R FILT must be increased by a factor of ten to reduce the current shunted through the filter. C FILT must be decreased by a factor of ten to maintain the same cutoff frequency. See Table for the recommended filter component values. Once f C is determined and R FILT is selected, the filter capacitance is calculated using When the calculated value is not available, it is better to choose a smaller capacitance value to keep f C above the minimum desired value calculated in Equation Table shows recommended values of R FILT and C FILT based on common component values. The value of f C was originally calculated to be kHz for an f MAX of kHz. C FILT however, was calculated to be 57,000 pF, but the nearest values of 56,000 pF and 51,000 pF were not available. A 47,000-pF capacitor was used instead, and f C is kHz, which is above the desired value of kHz. Table Typical RC Measurement Filter Values MEASUREMENT R FILT C FILT Efficiency 1000 Ω 5,600 pF All other measurements 100 Ω 56,000 pF Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPA3101D2PHP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3101D2PHPG4 ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3101D2PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3101D2PHPRG4 ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3101D2RGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3101D2RGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3101D2RGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3101D2RGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1

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