TPA3002D2PHPR

TPA3002D2_07 TI | Alldatasheet

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/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 /C0057/C0262/C0087 /C0083/C0084/C0069/C0082/C0069/C0079 /C0067/C0076/C0065/C0083/C0083/C0262/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0079/C0087/C0069/C0082 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0087/C0073/C0084/C0072 /C0068/C0067 /C0086/C0079/C0076/C0085/C0077/C0069 /C0067/C0079/C0078/C0084/C0082/C0079/C0076

FEATURES

/C00689-W/Ch Into an 8-Ω Load From 12-V Supply /C0068Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements /C006832-Step DC Volume Control From −40 dB to 36 dB /C0068Line Outputs For External Headphone Amplifier With Volume Control /C0068Regulated 5-V Supply Output for Powering TPA6110A2 /C0068Space-Saving, Thermally-Enhanced PowerPAD  Packaging /C0068Thermal and Short-Circuit Protection

APPLICATIONS

/C0068LCD Monitors and TVs /C0068Powered Speakers

DESCRIPTION

The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 Ω. The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music. Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from –40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also dc voltage controlled with a range of gain from –56 dB to 20 dB. An integrated 5-V regulated supply is provided for powering an external headphone amplifier. Cs Cs10 nF Cbs Cs Cs 10 nF Cbs PVCC PVCC Cs Cs10 nF Cbs Cs Cs 10 nF Cbs PVCC PVCC 220 pF Cosc Rosc Ccpl 100 nF Cvdd Ccpr Crinp Crinn Clinn Clinp LINP LINN RINN RINP SDZ VREF VOL REFGND VARDIFF VARMAX BSLP PVCCL PVCCL LOUTP LOUTP PGNDL PGNDL LOUTN LOUTN PVCCL PVCCL BSLN TPA3002D2 VCLAMPRSD V2P5 RINP LINN LINP AVDDREF VREF VARDIFF VARMAX VOLUME REFGND MODE MODE_OUT VAROUTR VAROUTL AVDD AGND COSC ROSC AVCC VCLAMPL BSRP PVCCR PVCCR ROUTP ROUTP PGNDR PGNDR ROUTN ROUTN PVCCR PVCCR BSRN RINN AVDD AVCCC2p5 AGND 10 µF10 µF 0.1 µF 0.1 µF 1 µF 1 µF 1 µF 1 µF 1 µF 0.1 µF 0.1 µF 10 µF 10 µF 1 µF 120 kΩ 1 µF kΩ 10 kΩ Cs 0.1 µF Cvcc 10 µF MODE_OUT MODE RLINE_OUT LLINE_OUT /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. www.ti.com Copyright  2002−2004, Texas Instruments Incorporated PowerPAD is a trademark of Texas Instruments.

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS TA PACKAGED DEVICE TA 48-PIN HTQFP (PHP)(1) −40°C to 85°C TPA3002D2PHP (1)The PHP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA3002D2PHPR). PIN ASSIGNMENTS PHP PACKAGE (TOP VIEW) 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 BSRN PVCCR PVCCR ROUTN ROUTN PGNDR PGNDR ROUTP ROUTP PVCCR PVCCR BSRP VCLAMPR MODE_OUT MODE VAROUTR VAROUTL AGND COSC ROSC AGND VCLAMPL SD RINN RINP V2P5 LINP LINN VREF VARDIFF VARMAX VOLUME REFGND BSLN PVCCL PVCCL LOUTN LOUTN PGNDL PGNDL LOUTP LOUTP PVCCL PVCCL BSLP TPA3002D2 AV CC AV DD AV DD REF

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com FUNCTIONAL BLOCK DIAGRAM Biases References TTL Input Buffer Startup Protection Logic OC Detect Thermal VDDok RINP RINN VAROUTR Ramp Generator COSC ROSC VCCok 5V LDO AVCC AVDD AVDD VDD Deglitch & Modulation Logic Gain Adj. Rfdbk2 Rfdbk2 Cint2 Cint2 Gain Control Deglitch & Modulation Logic Gain Adj. Rfdbk2 Rfdbk2 Cint2 Cint2 LINP LINN VAROUTL Gate Drive VClamp Gen Gate Drive PVCC BSRP PVCCR( 2) ROUTP( 2) PGNDR PGNDR ROUTN( 2) PVCCR( 2) BSRN Gate Drive VClamp Gen Gate Drive PVCC BSLP PVCCL( 2) LOUTP( 2) PGNDL PGNDL LOUTN( 2) PVCCL( 2) BSLN VCLAMP L VCLAMPR VOLUME VARDIFF VARMAX To Gain Adj. Blocks SD VREF REFGND V2P5 V2P5 V2P5 Mode Control MODE MODE_OUT AVCC AGND AVDDREF Gain Adj. Gain Adj. V2P5 V2P5 V2P5 V2P5

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONNO. NAME I/O DESCRIPTION AGND 26, 30 − Analog ground for digital/analog cells in core AV CC 33 − High-voltage analog power supply (8.5 V to 14 V) AV DD 29 O 5-V Regulated output capable of 100-mA output AV DD REF 7 O 5-V Reference output—provided for connection to adjacent VREF terminal. BSLN 13 I/O Bootstrap I/O for left channel, negative high-side FET BSLP 24 I/O Bootstrap I/O for left channel, positive high-side FET BSRN 48 I/O Bootstrap I/O for right channel, negative high-side FET BSRP 37 I/O Bootstrap I/O for right channel, positive high-side FET COSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5 LINN 6 I Negative differential audio input for left channel LINP 5 I Positive differential audio input for left channel LOUTN 16, 17 O Class-D 1/2-H-bridge negative output for left channel LOUTP 20, 21 O Class-D 1/2-H-bridge positive output for left channel MODE 34 I Input for MODE control. A logic high on this pin places the amplifier in the variable output mode and the Class-D outputs are disabled. A logic low on this pin places the amplifier in the Class-D mode and Class-D stereo outputs are enabled. Variable outputs (VAROUTL and VAROUTR) are still enabled in Class-D mode to be used as line-level outputs for external amplifiers. MODE_OUT 35 O Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the MODE_OUT pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is intended for MUTE control of an external headphone amplifier. Leave unconnected when not used for headphone amplifier control. PGNDL 18, 19 − Power ground for left channel H-bridge PGNDR 42, 43 − Power ground for right channel H-bridge PVCCL 14, 15 − Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or AVCC . PVCCL 22, 23 − Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or AVCC . PVCCR 38,39 − Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or AVCC . PVCCR 46, 47 − Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or AVCC . REFGND 12 − Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC ground to this terminal. RINP 3 I Positive differential audio input for right channel RINN 2 I Negative differential audio input for right channel ROSC 27 I/O Current setting resistor for ramp generator. Nominally equal to 1/8*VCC ROUTN 44, 45 O Class-D 1/2-H-bridge negative output for right channel ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channel SD 1 I Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC . VARDIFF 9 I DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to GND or AV DD REF if VAROUT outputs are unconnected. VARMAX 10 I DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AVDD REF if VAROUT outputs are unconnected. VAROUTL 31 O Variable output for left channel audio. Line level output for driving external HP amplifier. VAROUTR 32 O Variable output for right channel audio. Line level output for driving external HP amplifier. VCLAMPL 25 − Internally generated voltage supply for left channel bootstrap capacitors. VCLAMPR 36 − Internally generated voltage supply for right channel bootstrap capacitors. VOLUME 11 I DC voltage that sets the gain of the Class-D and VAROUT outputs. VREF 8 I Analog reference for gain control section. V2P5 4 O 2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended inputs. — Thermal Pad − Connect to AGND and PGND—should be center point for both grounds.

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Supply voltage range: AV CC, PVCC −0.3 V to 15 V MODE, VREF, VARDIFF , VARMAX, VOLUME 0 V to 5.5 V Input voltage range, VI SD −0.3 V to VCC + 0.3 VInput voltage range, VI RINN, RINP, LINN, LINP −0.3 V to 7 V Supply current AV DD 120 mA Supply current AVDDREF 10 mA Output current, VAROUTL, VAROUTR 20 mA Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, TA −40°C to 85°C Operating junction temperature range, T −40°C to 150°C Storage temperature range, Tstg −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PACKAGE DISSIPATION RATINGS PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C PHP 4.3 W 34.7 mW/°C (1) 2.7 W 2.2 W (1)The PowerPAD must be soldered to a thermal land on the printed circuit board. Please refer to the PowerPAD Thermally Enhanced Package application note (SLMA002). RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Supply voltage, VCC PV CC , AVCC 8.5 14 V Volume reference voltage VREF 3.0 5.5 V Volume control pins, input voltage VARDIFF , VARMAX, VOLUME 5.5 V High-level input voltage, VIH SD 2 VHigh-level input voltage, VIH MODE 3.5 V Low-level input voltage, VIL SD 0.8 VLow-level input voltage, VIL MODE 2 V High-level output voltage, VOH MODE_OUT , IOH = 1 mA AV DD −100mV V Low-level output voltage, VOL MODE_OUT , IOL = −1 mA AGND+100mV V High-level input current, IIH MODE, V I= 5 V, VCC = 14 V 1 uA High-level input current, IIH SD , VI= 14 V, VCC = 14 V 30 uA Low-level input current, IIL MODE, V I= 0 V, VCC = 14 V 1 uA Low-level input current, IIL SD , VI= 0 V, VCC = 14 V 1 uA Oscillator frequency, fOSC 225 275 kHz Operating free-air temperature, TA −40 85 °C

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com DC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT | VOS | Class-D Output offset voltage (measured differentially) INN and INP connected together, Gain = 36 dB 10 65 mV V2P5 (terminal 4) 2.5-V Bias voltage No load 0.45x AV DD 0.5x AV DD 0.55x AV DD V AV DD 5-V Regulated output IO = 0 to 100 mA, SD = 2 V, VCC = 8 V to 14 V 4.5 5.0 5.5 V PSRR Class-D power supply rejection ratioVCC = 11.5 V to 12.5 V −80 dB ICC(class-D) Class-D mode quiescent current MODE = 2 V, SD = 2 V 16 28.5 mA ICC(varout) Variable output mode quiescent currentMODE = 3.5 V, SD = 2 V 7 9 mA ICC(class-D – max power) Class-D mode RMS current at max power R L = 8 Ω, PO = 9 W 2 A ICC(SD) Supply current in shutdown mode SD = 0.8 V 1 10 uA ÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑ ÑÑÑÑÑ VCC = 12 V, ÑÑÑÑÑ ÑÑÑÑÑ High side ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ 300 ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑ rds(on) ÑÑÑÑÑÑÑÑÑÑÑ ÑÑÑÑÑÑÑÑÑÑÑ Drain-source on-state resistance ÑÑÑÑÑ ÑÑÑÑÑ VCC = 12 V, IO = 1 A, T = 25C ÑÑÑÑÑ ÑÑÑÑÑ Low side ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ 250 ÑÑÑ ÑÑÑ ÑÑÑ ÑÑÑ m Ω ÑÑÑÑÑÑÑÑ rds(on) ÑÑÑÑÑÑÑÑÑÑÑ Drain-source on-state resistance ÑÑÑÑÑ IO = 1 A, TJ = 25°C ÑÑÑÑÑ Total ÑÑÑ ÑÑÑ 550 ÑÑÑ 590 ÑÑÑ m Ω AC ELECTRICAL CHARACTERISTICS FOR CLASS-D OUTPUTS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS kSVR Supply ripple rejection ratio VCC = 11.5 V to 12.5 V from 10 Hz to 1 kHz, Gain = 36 dB −67 dB PO Continuous output power THD+N = 1%, f = 1 kHz, RL = 8 Ω 7.5 W PO Continuous output power THD+N = 10%, f = 1 kHz, RL = 8 Ω 9 W 20 Hz to 22 kHz, No filter, Gain = 0.5 dB 79 µV Vn Output integrated noise floor 20 Hz to 22 kHz, No filter, Gain = 0.5 dB −82 dBV Vn Output integrated noise floor

20 Hz to 22 kHz, A-weighted filter, 100 µV20 Hz to 22 kHz, A-weighted filter,

Gain = 13.2 dB −80 dBV Crosstalk, Class-D−Left → Class-D−Right Gain = 13.2 dB, PO = 1 W, RL = 8 Ω −77 dB Crosstalk, Class-D → VAROUT Maximum output at THD < 0.5%, Gain = 36 dB −63 dB SNR Signal-to-noise ratio Maximum output at THD+N < 0.5%, f= 1 kHz, Gain = 36 dB 96 dB Thermal trip point 150 °C Thermal hystersis 20 °C CHARACTERISTICS FOR VAROUT OUTPUTS PARAMETER TEST CONDITIONS MIN TYP MAX UNITS |VOS | Output offset voltage Measured between V2P5 and VAROUT , Gain = 20 dB, RL = 10 kΩ 10 mV THD+N Total harmonic distortion + noise AV = 7.3 dB, f = 1 kHz, PO = 6 mW, RL = 32 Ω 0.025% THD+N Total harmonic distortion + noiseAV = 7.3 dB, f = 1 kHz, RL = 2 kΩ, VO = 1 Vrms 0.002% PSRR DC power supply rejection ratio Gain = 20 dB −74 dB kSVR Supply ripple rejection ratio Gain = 20 dB, f = 1 kHz −95 dB Crosstalk, VAROUTL → VAROUTR Maximum output at THD < 0.5%, Gain = 20 dB −60 dB Crosstalk, VAROUT → Class-D Maximum output at THD < 0.5%, Gain = 20 dB −74 dB Vn Output integrated noise floor

20 Hz to 22 kHz, Gain = 20 dB 75

VVn Output integrated noise floor 20 Hz to 22 kHz, Gain = −0.3 dB 15 µV

Table 1. DC Volume Control for Class-D Outputs (1)Tested in production. Remaining steps are specified by design.

Table 2. DC Volume Control for VAROUT Outputs (1)Tested in production. Remaining steps are specified by design.

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Class-D Efficiency vs Output power 1 PO Class-D Output power vs Load resistance 2PO Class-D Output power vs Supply voltage 3 ICC Class-D Supply current vs Supply voltage 4ICC Class-D Supply current vs Output Power 5 IO(sd) Shutdown supply current vs Supply voltage 6 Class-D Input resistance vs Gain 7 THD+N Class-D Total harmonic distortion + noise vs Frequency 8, 9 THD+N Class-D Total harmonic distortion + noise vs Output power 10, 11 kSVR Class-D Supply ripple rejection ratio vs Frequency 12 Class-D Closed loop response 13 Class-D Intermodulation performance 14 Class-D Input offset voltage vs Common-mode input voltage 15 Class-D Crosstalk vs Frequency 16 Class-D Mute attenuation vs Frequency Class-D Shutdown attenuation vs Frequency 18 Class-D Common-mode rejection ratio vs Frequency 19 VAROUT Input resistance vs Gain 20 VAROUT Noise vs Frequency 21 VAROUT Closed Loop Response 22 VAROUT Common-mode rejection ratio vs Frequency 23 VAROUT Crosstalk vs Frequency 24 vs Output power 25 THD+N VAROUT Total harmonic distortion + noise vs Output voltage 26THD+N VAROUT Total harmonic distortion + noise vs Frequency 27 kSVR VAROUT Supply ripple rejection ratio vs Frequency 28

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com

APPLICATION INFORMATION

LIN− RIN− SHUTDOWN BSLP PVCCL PVCCL LOUTP LOUTP PGNDL PGNDL LOUTN LOUTN PVCCL PVCCL BSLN TPA3002D2 VCLAMPRSD V2P5 RINP LINN LINP AVDDREF VREF VARDIFF VARMAX VOLUME REFGND MODE MODE_OUT VAROUTR VAROUTL AGND AVDD AGND COSC ROSC AVCC VCLAMPL BSRP PVCCR PVCCR ROUTP ROUTP PGNDR PGNDR ROUTN ROUTN PVCCR PVCCR BSRN RINN C16C5 50k LOUT− VCC VCC LOUT+ C1510 nF C18 C10 10 nF C19 ROUT− VCC VCC (Bead) C24 1nF (Bead) C25 1nF GND GND GND VAROUTR VAROUTL AVDD C13 GND MODEB MODE AGND AGND AGND PGND PGND PGND PGND GND ROUT+ (Bead) C22 1 nF (Bead) C23 1 nF VCC 10 µF 0.1uF 0.1uF 1 µF 0.1 µF 10 µF 120 kΩ 1 µF 0.1 µF0.1 µF 10 µF 50 kΩ 50 kΩ 1 µF 1 µF 1 µF 1 µF 1 µF 10 µF Figure 29. Stereo Class-D With Single-Ended Inputs

Figure 30. Stereo Class-D With Single-Ended Inputs and Stereo Headphone Amplifier Interface

This section focuses on the class-D operation of the TPA3002D2. high, causing high loss, thus causing a high supply current. Figure 31. Traditional Class-D Modulation Scheme’s Output Voltage and The TPA3002D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage. most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.

Figure 32. The TPA3002D2 Output Voltage and Current Waveforms Into an Inductive Load resistive and reactive, whereas an LC filter is almost purely reactive. for most applications the filter is not needed. power dissipation, therefore increasing efficiency. for frequencies beyond the audio band.

power generated from a clipping waveform. impedance at high frequencies, but very low impedance at low frequencies. the amplifier to the speaker. Figure 33. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω

Figure 34. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3) the VAROUT volume. All of these pins are controlled with a dc voltage, which should not exceed VREF. the gain in class-D mode as determined by the voltage on the VOLUME pin in reference to the voltage on VREF. × VREF will be present at the VOLUME pin and result in a class-D gain of 10.7 dB. If using an analog potentiometer to control the gain, it should be connected between VREF and REFGND. second column should be referenced. gain is 16 dB. As the voltage on the VARDIFF terminal is increased, the VAROUT channel gain decreases. VOLUME terminal and this value is used to determine the VAROUT gain.

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com MODE OPERATION The MODE pin is an input for controlling the output mode of the TPA3002D2. A logic HIGH on this pin disables the Class-D outputs. A logic LOW on this pin enables the class-D outputs. The VAROUT outputs are active in both modes and can be used as line level inputs to an external powered subwoofer while driving internal stereo speakers with the class-D outputs. The trip levels are defined in the specifications table. For interfacing with an external headphone amplifier like the TPA6110A2, the MODE pin can be connected to the switch on a headphone jack. When configured like Figure 30, the class-D outputs will be disabled when a headphone plug is inserted into the headphone jack. MODE_OUT OPERATION for controlling the SHUTDOWN pin on an external headphone amplifier like the TPA6110A2 or for interfacing with other logic. The output voltages for a given load condition are given in the specifications table. This output is controlled by the MODE pin logic. When the MODE input is driven to a logic low, the MODE_OUT output drives to a logic high. Conversely, when the MODE pin is driven to a logic high, the MODE_OUT output drives LOW. The MODE_OUT output is simply the inverted state of the MODE input. It is designed in this manner because the TPA6110A2 SHUTDOWN input is active high. This allows the TPA3002D2 to place the TPA6110A2 into the shutdown state when driving internal speakers in the Class-D mode. Conversely, the MODE_OUT pin drives low to enable the TPA6110A2 headphone amplifier when headphones are plugged into the headphone jack and the MODE input is driven high. SELECTION OF COSC AND ROSC The switching frequency is determined using the values of the components connected to ROSC (pin 27) and COSC (pin 28) and may be calculated with the following equation: fOSC = 6.6 / (ROSC * COSC ) INTERNAL 2.5-V BIAS GENERATOR CAPACITOR SELECTION The internal 2.5-V bias generator (V2P5) provides the internal bias for the preamplifier stages on both the class-D amplifiers and the variable amplifiers. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of the input preamplifiers. The selection of the capacitor value on the V2P5 terminal is critical for achieving the best device performance. During startup or recovery from the shutdown state, the V2P5 capacitor determines the rate at which the amplifier starts up. When the voltage on the V2P5 capacitor equals 0.75xV2P5, or 75% of its final value, the device turns on and the class-D outputs start switching. The startup time is not critical for the best depop performance since any pop sound that is heard is the result of the class-D outputs switching on and not the startup time. However, at least a 0.47-µF capacitor is recommended for the V2P5 capacitor. A secondary function of the V2P5 capacitor is to filter high frequency noise on the internal 2.5-V bias generator. INPUT RESISTANCE Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the −3 dB or cutoff frequency also changes by over six times. C i IN Zi Zf Input Signal The −3-dB frequency can be calculated using equation 5. Input impedance (Zi) vs Gain can be found in Figure 7.

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com f/C00423dB /C00431 2/C0112ZiC i INPUT CAPACITOR, C I In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper dc level (V2P5)for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a high-pass filter with the corner frequency determined in equation 6. fc /C00431 2/C0112ZiC i −3 dB fc (6) The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider the example where Zi is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6 is reconfigured as equation 7. C i /C00431 2/C0112Zifc In this example, Ci is 0.4 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. If the gain is known and will be constant, use Zi from Figure 7 (Input Impedance vs Gain) to calculate Ci. Calculations for C i should be based off the impedance at the lowest gain step intended for use in the system. A further consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Power Supply Decoupling, C S The TPA3002D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device V CC lead works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio power amplifier is recommended. The 10-µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. BSN and BSP Capacitors The full H-bridge output stages use only NMOS transistors. They therefore require bootstrap capacitors for the high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be connected from xOUTP to xBSP, and one 10-nF capacitor must be connected from xOUTN to xBSN. (See the application circuit diagram in Figure 29.) (5) (7)

decrease while the high-side is conducting. CC and may not be used for powering any other circuitry. Figure 37. Power-Up Response The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. audio source instead of at the device input for best noise performance.

/C0084/C0080/C0065/C0051/C0048/C0048/C0050/C0068/C0050 SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004 www.ti.com SD OPERATION The TPA3002D2 employs a shutdown mode of operation designed to reduce supply current (ICC ) to the absolute minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see specification table for trip point)during normal operation when the amplifier is in use. Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state, ICC(SD) = 10 µA. SD should never be left unconnected, because amplifier operation would be unpredictable. POWER-OFF POP REDUCTION For the best power-off pop performance, the amplifier should be placed in the shutdown mode prior to removing the power supply voltage. Another method to reduce power-off pop can be implemented in the hardware. A 100-µF − 150-µF capacitor can be added to the AVDD terminal in parallel with the 100-nF capacitor shown in Figure 29. The additional capacitance holds up the regulator voltage for a longer period of time and results in smaller power-off pop. USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor. SHORT-CIRCUIT PROTECTION The TPA3002D2 has short circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-V CC shorts. When a short-circuit is detected on the outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the voltage on the SD pin to a logic low and back to the logic high state for normal operation. This will clear the short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the protection circuitry will again activate. The trip-point for the short-circuit protection is nominally set at 8 A. However, this trip point can vary with PCB layout and the separation of AV CC and PVCC . It is important to connect the AVCC pin as close as possible to all of the PVCC pins with a wide (>20 mils) trace. This minimizes the inductance between the two pins and allows the short-circuit protection to trip at the nominal current. If the inductance between these two pins is large, the short-circuit protection may inadvertently trip when drive low impedance loads into heavy clipping. THERMAL PROTECTION Thermal protection on the TPA3002D2 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15 degree tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 20°C. The device begins normal operation at this point with no external system interaction. THERMAL CONSIDERATIONS: OUTPUT POWER AND MAXIMUM AMBIENT TEMPERATURE To calculate the maximum ambient temperature, the following equation may be used: ΘJA = 19°C/W (2-Layer PCB, 5 sq. in. copper, see Figure 38) where: TJmax = 150°C TAmax = TJmax – ΘJAPDissipated To estimate the power dissipation, the following equation may be used: PDissipated = PO(average) x ((1 / Efficiency) – 1) Efficiency = ~85% for an 8-Ω load = ~75% for a 4-Ω load (8) (9)

board (PCB) should be optimized according to the following guidelines for the best possible performance. PowerPAD, which should be used as a central ground connection or star ground for the TPA3002D2. Basically, an island should be created with a single connection to PGND at the PowerPAD. capacitors used in both the ferrite and LC filters should be grounded to power ground. reliability. The dimensions of the PowerPAD thermal land should be 5 mm by 5 mm (197 mils by 197 mils). Enhanced Package application note (SLMA002). Figure 38. Thermal Resistance

20 Hz − 20 kHz

20 Hz − 20 kHzRL

Figure 40. Audio Measurement Systems analyzer can measure the output sine wave. All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. the output power to the load and eliminating a dc blocking capacitor. equates to a balanced output.

Figure 41. Differential Input—BTL output Measurement Circuit noise in the circuit and providing the most accurate measurement. /C0068Use a balanced source to supply the input signal. /C0068Use an analyzer with balanced inputs. /C0068Use twisted-pair wire for all connections. /C0068Use shielding when the system environment is noisy. are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C. Table 3. Recommended Minimum Wire Size for Power Cables class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx). The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 42. ground pin to minimize ground loops.

Figure 42. Measurement Low-Pass Filter Derivation Circuit—Class-D APAs minimize the attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA . error to less than 1% for RANA ≥ 10 kΩ. cutoff frequency. See Table 4 for the recommended filter component values. desired value calculated in equation (11). and fC is 34 kHz, which is above the desired value of 28 kHz. Table 4. Typical RC Measurement Filter Values

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPA3002D2PHP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TPA3002D2PHPG4 ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TPA3002D2PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TPA3002D2PHPRG4 ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Apr-2006 Addendum-Page 1

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Summary

9-W STEREO CLASS-D AUDIO POWER AMPLFIER WITH DC VOLUME CONTROL

Description