TPA0142PWPR

TPA0142_16 TI1 | Alldatasheet

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FEATURES

LOUT± LIN BYPASS GND GND RLINEIN SHUTDOWN ROUT+ RHPIN V DD PVDD CLK ROUT± SE/BTL PC-BEEP GND PWP PACKAGE (TOP VIEW) TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 2.8-W STEREO AUDIO POWER AMPLIFIER WITH DC VOLUME CONTROL Compatible With PC Desktop Line-Out Into 10-k Ω Load Compatible With PC Portable Into Ω Load Internal Gain Control, Which Eliminates External Gain-Setting Resistors DC Volume Control From dB to -40 dB 2.8-W/Ch Output Power Into a Ω Load PC-Beep Input Depop Circuitry Stereo Input MUX Fully Differential Input Low Supply Current and Shutdown Current Surface-Mount Power Packaging 24-Pin TSSOP PowerPAD

DESCRIPTION

a stereo audio power amplifier in a 24-pin TSSOP thermally enhanced package capable of delivering 2.8 W of continuous RMS power per channel into Ω loads. This device minimizes the number of external components needed, which simplifies the design and frees up board space for other features. When driving W into Ω speakers, the TPA0142 has less than 0.22% THD+N across its specified frequency range. Included within this device is integrated depop circuitry that virtually eliminates transients that cause noise in the speakers. Amplifier gain is controlled by a dc voltage input on the VOLUME terminal. There are discrete steps covering the range of dB (maximum volume setting) to -40 dB (minimum volume setting) in 2-dB steps. When the VOLUME terminal exceeds 3.54 the device is muted. An internal input MUX allows two sets of stereo inputs to the amplifier. In notebook applications, where internal speakers are driven as bridge-tied load (BTL) and the line outputs (often headphone drive) are required to be single-ended (SE), the TPA0142 automatically switches into SE mode when the SE/ BTL input is activated, and this effectively reduces the gain by dB. The TPA0142 consumes only mA of supply current during normal operation. A shutdown mode reduces the supply current to 150 µ The PowerPAD package (PWP) delivers a level of thermal performance that was previously achievable only in TO-220-type packages. Thermal impedances of approximately C/W are truly realized in multilayer PCB applications. This allows the TPA0142 to operate at full power into Ω loads at ambient temperatures of Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 1999 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ROUT+ R MUX 32-Step Volume Control PC Beep MUX Control Depop Circuitry Power Management L MUX 32-Step Volume Control RHPIN RLINEIN VOLUME RIN PC-BEEP SE/BTL LHPIN LLINEIN LIN ROUT- PVDD VDD BYPASS SHUTDOWN GND LOUT+ LOUT- 32-Step Volume Control 32-Step Volume Control TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGED DEVICE T A TSSOP (1) (PWP) -40 C to C TPA0142PWP (1) The PWP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA0142PWPR). FUNCTIONAL BLOCK DIAGRAM

www.ti.com ABSOLUTE MAXIMUM RATINGS TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 Terminal Functions TERMINAL I/O NO. BYPASS Tap to voltage divider for internal mid-supply bias generator If a 47-nF capacitor is attached, the TPA0142 generates an internal clock. An external clock can override the CLK I internal clock input to this terminal. GND I Ground connection for circuitry. Connected to thermal pad 13, LHPIN I Left channel headphone input, selected when SE/ BTL is held high LIN I Common left input for fully differential input. AC ground for single-ended inputs LLINEIN I Left channel line negative input, selected when SE/ BTL is held low LOUT+ O Left channel positive output in BTL mode and positive output in SE mode LOUT- O Left channel negative output in BTL mode and high-impedance in SE mode If this terminal is high, the detection circuitry for PC-BEEP is overridden and passes PC-BEEP through the PCB EN- I amplifier, regardless of its amplitude. If PCB ENABLE is floating or low, the amplifier continues to operate ABLE normally. The input for PC-Beep mode. PC-BEEP is enabled when a 1.5-V PP (peak-to-peak) square wave is input to PC-BEEP I PC-BEEP or PCB ENABLE is high. PV DD I Power supply for output stage RHPIN I Right channel headphone input, selected when SE/ BTL is held high RIN I Common right input for fully differential input. AC ground for single-ended inputs RLINEIN I Right channel line input, selected when SE/ BTL is held low ROUT+ O Right channel positive output in BTL mode and positive output in SE mode ROUT- O Right channel negative output in BTL mode and high-impedance in SE mode Input and output MUX control. When this terminal is held high, the LHPIN or RHPIN and SE output is SE/ BTL I selected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected. SHUTDOWN I When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdown mode. V DD I Analog V DD input supply. This terminal needs to be isolated from PV DD to achieve highest performance. VOLUME detects the dc level at the terminal and sets the gain for discrete steps covering a range of VOLUME I dB to -40 dB for dc levels of 0.15 V to 3.54 When the dc level is over 3.54 the device is muted. Thermal Pad Connect to ground. Must be soldered down in all board. over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage, V DD V Input voltage, V I -0.3 V to V DD 0.3 V Continuous total power dissipation Internally limited (see Dissipation Rating Table) Operating free-air temperature range, T A -40 C to C Operating junction temperature range, T J -40 C to 150 C Storage temperature range, T stg -65 C to C Lead temperature 1,6 mm (1/16 inch) from case for seconds 260 C (1) Stresses beyond those listed under "absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

www.ti.com RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS OPERATING CHARACTERISTICS TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 DISSIPATION RATING TABLE PACKAGE T A C DERATING FACTOR T A C T A C PWP 2.7 W (1) 21.8 mW/ C 1.7 W 1.4 W (1) See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report (literature number SLMA002), for more information on the PowerPAD package. The thermal data was measured on a PCB layout based on the information in the section entitled Texas Instruments Recommended Board for PowerPAD on page of the before mentioned document. MIN MAX UNIT Supply voltage, V DD 4.5 5.5 V PCB ENABLE 0.6 V DD High-level input voltage, V IH SE/ BTL 0.8 V DD V SHUTDOWN PCB ENABLE 0.4 V DD Low-level input voltage, V IL SE/ BTL 0.6 V DD V SHUTDOWN 0.8 Operating free-air temperature, T A -40 C at specified free-air temperature, V DD T A C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OS Output offset voltage (measured differentially) V I A V dB mV PSRR Supply ripple rejection ratio V DD 4.9 V to 5.1 V dB High-level input current SHUTDOWN SE/ BTL V DD 5.5 V I V DD 900 nA VOLUME IH High-level input current PCB ENABLE V DD 5.5 V I V DD 125 µ A Low-level input current SHUTDOWN SE/ BTL IL V DD 5.5 V I V 900 nA VOLUME, PCB ENABLE BTL mode SHUTDOWN SE/ BTL 0.6 V DD I DD Supply current mA SE mode SHUTDOWN 12.5 SE/ BTL 0.8 V DD SHUTDOWN I DD(SD) Supply current, shutdown mode 150 300 µ A SE/ BTL V V DD T A R L Ω Gain V/V, BTL mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THD 10% 2.8 P O Output power R L Ω f kHz W THD 2.2 THD N Total harmonic distortion plus noise P O f Hz to kHz 0.22% B OM Maximum output power bandwidth THD >15 kHz BTL mode -78 C (BYP) 0.47 µ Supply ripple rejection ratio dB f kHz SE mode -60 BTL mode C (BYP) 0.47 µ V n Noise output voltage µ V RMS f Hz to kHz SE mode

www.ti.com TYPICAL CHARACTERISTICS 0.01% −40 −30 −20 −10 0 THD+N −Total Harmonic Distortion + Noise A - Voltage Gain - dB 0.1% 10 20 V RL = 8 Ω BTL 0.1% 0.01% 10% 2.25 2.5 2.75 3 PO − Output Power − W AV = 20 to 4 dB f = 1 kHz BTL THD+N −Total Harmonic Distortion + Noise RL = 8 Ω RL = 3 Ω RL = 4 Ω TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 Table of Graphs FIGURE vs Output power vs Voltage gain THD+N Total harmonic distortion plus noise vs Frequency vs Output voltage V n Output noise voltage vs Bandwidth Supply ripple rejection ratio vs Frequency 14, Crosstalk vs Frequency 16, 17, Shutdown attenuation vs Frequency SNR Signal-to-noise ratio vs Bandwidth Closed loop response 21, P O Output power vs Load resistance 23, vs Output power 25, P D Power dissipation vs Ambient temperature Z i Input impedance vs Gain TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs vs OUTPUT POWER VOLTAGE GAIN Figure Figure

www.ti.com 0.1% 0.01% 0.01 0.1 10% 1 10 f = 20 Hz f = 1 kHz PO − Output Power − W RL = 3 Ω AV = 20 to 4 dB BTL THD+N −Total Harmonic Distortion + Noise f = 20 kHz 0.01% 10% 20 100 1k 10k 20k THD+N −Total Harmonic Distortion + Noise f − Frequency − Hz 0.1% RL = 3 Ω AV = 20 to 0 dB BTL PO = 1.75 W PO = 0.5 W PO = 1 W 0.1% 0.01% 20 100 10% 1k 10k f − Frequency − Hz RL = 4 Ω AV = 20 to 4 dB BTL THD+N −Total Harmonic Distortion + Noise PO = 0.25 W 20k PO = 1 W PO = 1.5 W 0.1% 0.01% 0.01 0.1 10% 1 10 f = 20 Hz f = 1 kHz PO − Output Power − W THD+N −Total Harmonic Distortion + Noise f = 20 kHz RL = 4 Ω AV = 20 to 4 dB BTL TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs vs FREQUENCY OUTPUT POWER Figure Figure TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs vs FREQUENCY OUTPUT POWER Figure Figure

www.ti.com 0.1% 0.01% 0.01 0.1 10% 1 10 f = 20 Hz f = 1 kHz PO − Output Power − W THD+N −Total Harmonic Distortion + Noise f = 20 kHz RL = 8 Ω AV = 20 to 4 dB BTL 0.01% 10% 20 100 1k 10k 20k THD+N −Total Harmonic Distortion + Noise f − Frequency − Hz 0.1% PO = 0.25 W PO = 0.5 W PO = 1 W RL = 8 Ω AV = 20 to 4 dB BTL 0.1% 0.01% 10% 10k f − Frequency − Hz THD+N −Total Harmonic Distortion + Noise PO = 25 mW 20k RL = 32 Ω AV = 14 to 4 dB SE PO = 50 mW PO = 75 mW 100 1k 0.001% 0.1% 0.01% 0.01 0.1 10% f = 20 Hz f = 1 kHz PO − Output Power − W THD+N −Total Harmonic Distortion + Noise f = 20 kHz RL = 32 Ω AV = 14 to 4 dB SE TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs vs FREQUENCY OUTPUT POWER Figure Figure TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs vs FREQUENCY OUTPUT POWER Figure Figure 10.

www.ti.com THD+N −Total Harmonic Distortion + Noise f = 20 kHz VO − Output Voltage − VRMS 0.001% 0.01% 0.1% 10% RL = 10 kΩ AV = 14 to 4 dB SE f = 1 kHz f = 20 Hz 0.001% 10% 20 100 1k 10k 20k THD+N −Total Harmonic Distortion + Noise f − Frequency − Hz 0.1% VO = 1 VRMS 0.01% RL = 10 kΩ AV = 14 to 0 dB SE 120 20 100 140 160 1k 10k BW − Bandwidth − Hz VDD = 5 V RL = 4 Ω AV = 20 dB 20k AV = 6 dB − Output Noise Voltage − VµVn RMS 100 −100 −120 20 100 −80 1k 10k RL = 8 Ω C(BYP) = 0.47 µF BTL AV = 6 dB −60 −40 −20 f − Frequency − Hz 20k AV = 20 dB Supply Ripple Rejection Ratio − dB TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs vs FREQUENCY OUTPUT VOLTAGE Figure 11. Figure 12. OUTPUT NOISE VOLTAGE SUPPLY RIPPLE REJECTION RATIO vs vs BANDWIDTH FREQUENCY Figure 13. Figure 14.

www.ti.com −100 −120 20 100 −80 1k 10k RL = 32 Ω C(BYP) = 0.47 µF SE AV = 0 dB −60 −40 −20 f − Frequency − Hz 20k AV = 14 dB Supply Ripple Rejection Ratio − dB −120 −80 20 100 1k 10k 20k Crosstalk − dB f − Frequency − Hz −90 −100 −110 PO = 1 W RL = 8 Ω AV = 20 dB BTL −70 −60 Left to Right Right to Left −50 −40 −120 −40 20 100 1k 10k 20k Crosstalk − dB f − Frequency − Hz −60 −80 −100 VO = 1 VRMS RL = 10 kΩ AV = 6 dB SE Left to Right Right to Left −110 −90 −70 −50 −120 −80 20 100 1k 10k 20k Crosstalk − dB f − Frequency − Hz −90 −100 −110 PO = 1 W RL = 8 Ω AV = 6 dB BTL −70 −60 Left to Right Right to Left −50 −40 TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 SUPPLY RIPPLE REJECTION RATIO CROSSTALK vs vs FREQUENCY FREQUENCY Figure 15. Figure 16. CROSSTALK CROSSTALK vs vs FREQUENCY FREQUENCY Figure 17. Figure 18.

www.ti.com 110 20 100 1k 10k 20k SNR − Signal-To-Noise Ratio − dB BW − Bandwidth − Hz 105 100 115 120 PO = 1 W RL = 8 Ω BTL AV = 20 dB AV = 6 dB −120 −40 20 100 1k 10k 20k Shutdown Attenuation − dB f − Frequency − Hz −60 −80 −100 −20 VI = 1 VRMS RL = 8 Ω , BTL RL = 32 Ω , SE RL = 10 kΩ , SE −10 10 100 1k 10k 100k Gain − dB f − Frequency − Hz 180° 90° −90° −180° RL = 8 Ω AV = 20 dB BTL Gain Phase Phase −10 10 100 1k 10k 100k Gain − dB f − Frequency − Hz 180° 90° −90° −180° RL = 8 Ω AV = 6 dB BTL Gain Phase Phase TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 SHUTDOWN ATTENUATION SIGNAL-TO-NOISE RATIO vs vs FREQUENCY BANDWIDTH Figure 19. Figure 20. CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE Figure 21. Figure 22.

www.ti.com 1.5 0 8 16 24 32 40 2.5 3.5 48 56 64 RL − Load Resistance − Ω AV = 20 to 0 dB BTL − Output Power − WPO 1% THD+N 10% THD+N 0.5 750 0 8 16 1000 1250 1500 24 32 RL − Load Resistance − Ω AV = 14 to 0 dB SE − Output Power − mWPO 1% THD+N 10% THD+N 500 250 40 48 56 64 0.6 0.4 0.2 0 1 − Power Dissipation − W 1.2 1.4 1.5 2.5 0.8 PO − Output Power − W PD 4 Ω 8 Ω f = 1 kHz BTL Each Channel 3 Ω1.6 1.8 0.5 2 0.1 0.05 0 0.2 − Power Dissipation − W 0.2 0.25 0.3 0.3 0.8 0.15 PO − Output Power − W PD 8 Ω 32 Ω f = 1 kHz SE Each Channel 4 Ω 0.35 0.4 TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 OUTPUT POWER OUTPUT POWER vs vs LOAD RESISTANCE LOAD RESISTANCE Figure 23. Figure 24. POWER DISSIPATION POWER DISSIPATION vs vs OUTPUT POWER OUTPUT POWER Figure 25. Figure 26.

www.ti.com −40 −20 −10 10 AV − Gain − dB −30 0 − Input Impedance −ZI Ωk −40 0 − Power Dissipation − W 20 160 TA − Ambient Temperature − ° C PD −20 10040 60 80 120 140 Θ JA3 Θ JA1,2 Θ JA4 Θ JA1 = 45.9° C/W Θ JA2 = 45.2° C/W Θ JA3 = 31.2° C/W Θ JA4 = 18.6° C/W TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 POWER DISSIPATION INPUT IMPEDANCE vs vs AMBIENT TEMPERATURE GAIN Figure 27. Figure 28.

www.ti.com Volume Control Characteristics TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 Table Typical DC Volume Control (1) VOLUME (Terminal TYPICAL VOLTAGE INCREASING VOLTAGE GAIN of AMPLIFIER OR FIXED GAIN DECREASING (dB) (2) (V) (V) 0-0.27 0.16-0 0.28-0.37 0.28-0.17 0.38-0.48 0.39-0.29 0.49-0.58 0.50-0.40 0.59-0.69 0.61-0.51 0.70-0.80 0.72-0.62 0.81-0.91 0.84-0.73 0.92-1.02 0.95-0.85 1.03-1.13 1.06-0.96 1.14-1.24 1.17-1.07 1.25-1.35 1.29-1.18 1.36-1.46 1.40-1.30 1.47-1.58 1.51-1.41 1.59-1.68 1.62-1.52 1.69-1.79 1.73-1.63 1.80-1.90 1.84-1.74 -10 1.91-2.01 1.96-1.85 -12 2.02-2.12 2.06-1.97 -14 2.13-2.23 2.18-2.07 -16 2.24-2.34 2.29-2.19 -18 2.35-2.45 2.41-2.30 -20 2.46-2.56 2.52-2.42 -22 2.57-2.67 2.62-2.53 -24 2.68-2.78 2.74-2.63 -26 2.79-2.90 2.86-2.75 -28 2.91-3.01 2.97-2.87 -30 3.02-3.12 3.07-2.98 -32 3.13-3.23 3.19-3.08 -34 3.24-3.33 3.29-3.20 -36 3.34-3.44 3.40-3.30 -38 3.45-3.55 3.53-3.41 -40 3.56-5.00 5.00-3.54 -85 (1) Each step is tested at its midpoint and characterized within 4dB of the specified gain value for V DD For V DD 4.5 V to 5.5 multiply values by 90% and 110%, respectively. (2) 95% of the characterized values lie within 0.5dB of the specified gain value. Figure shows the typical behavior of most devices.

www.ti.com 100 Gain − dB Frequency of Occurance − % TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 GAIN HISTOGRAM AT dB Figure 29. Typical Gain Variance

www.ti.com APPLICATION INFORMATION GND PCBENABLE VOLUME LOUT+ LLINEIN LHPIN PVDD RIN LOUT− LIN BYPASS GND GND RLINEIN SHUTDOWN ROUT+ RHPIN VDD PVDD CLK ROUT− SE/BTL PC-BEEP GND VDD 50 kΩ 0.47 µF 0.47 µF 0.47 µF 0.47 µF 0.47 µF LOUT+ LHP RIN LOUT− 0.47 µF 0.1 µF 47 nF 0.1 µF 10 µF PC-BEEP 0.47 µF RLINE SHUTDOWN ROUT− RHP VDD GND ROUT− 0.47 µF LLINEIN SE/BTL TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 Figure 30. Typical TPA0142 Application Circuit

www.ti.com Component Selection ROUT+ 21 R MUX RHPIN RLINEIN23 CIRHP 0.47 µF Right Head− phone Input Signal CIRLINE 0.47 µFRight Line Input Signal CRIN 0.47 µF

8 RIN

ROUT− 16 1 kΩ COUTR 330 µF 100 kΩ L MUX LHPIN LLINEIN5 CILHP 0.47 µF Left Head− phone Input Signal CILLINE 0.47 µFLeft Line Input Signal CLIN 0.47 µF

10 LIN

1 kΩ COUTL 330 µF VDD 100 kΩ Depop Circuitry Power Management PVDD 18 VDD 19 BYPASS 11 SHUT− DOWN 22 GND LOUT+ 4 LOUT− 9 CBYP 0.47 µF 1, 12, 13, 24 To System Control CSR 0.1 µF VDD CSR 0.1 µF VDD See Note A PC- Beep PC-BEEP14 CPCB 0.47 µF PC-BEEP Input Signal Gain/ MUX Control VOLUME CLK SE/BTL15CCLK 47 nF VDD 50 kΩ 32-Step Volume Control 32-Step Volume Control 32-Step Volume Control 32-Step Volume Control TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) Figure and Figure are schematic diagrams of typical notebook computer application circuits. A 0.1- µ F ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise signals, a larger electrolytic capacitor of µ F or greater should be placed near the audio power amplifier. Figure 31. Typical TPA0142 Application Circuit Using Single-Ended Inputs and Input MUX

www.ti.com CCLK 47 nF SE/BTL ROUT+ 21 R MUX RHPIN RLINEIN CIRIN− 0.47 µF ROUT− 16 1 kΩ COUTR 330 µF 100 kΩ L MUX LHPIN LLINEIN5 CILIN− 0.47 µF 1 kΩ COUTL 330 µF VDD 100 kΩ Depop Circuitry Power Management PVDD 18 VDD 19 BYPASS 11 SHUT− DOWN 22 GND LOUT+ 4 LOUT− 9 CBYP 0.47 µF 1, 12, 13, 24 To System Control CSR 0.1 µF VDD CSR 0.1 µF VDD See Note A PC- Beep PC-BEEP14 CPCB 0.47 µF PC-BEEP Input Signal Gain/ MUX Control VOLUME CLK 1717 CIRIN+ 0.47 µF VDD 50 kΩ CILIN 0.47 µF 32-Step Volume Control 32-Step Volume Control 32-Step Volume Control CIRHP− 0.47 µF 32-Step Volume Control PCB ENABLE CILHP 0.47 µF Right Positive Differential Input Signal Right Negative Differential Input Signal Left Negative Differential Input Signal Left Positive Differential Input Signal TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) A 0.1- µ F ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise signals, a larger electrolytic capacitor of µ F or greater should be placed near the audio power amplifier. Figure 32. Typical TPA0142 Application Circuit Using Differential Inputs

www.ti.com VOLUME CONTROL OPERATION Decreasing Voltage on VOLUME Terminal Increasing Voltage on VOLUME Terminal 1.17 1.36 1.25 1.29 Gain - dB Voltage on VOLUME Pin - V INPUT RESISTANCE C R IN Ri Rf Input Signal TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) The VOLUME pin controls the volume of the TPA0142. It is controlled with a dc voltage, which must not exceed V DD The gain voltages on the VOLUME pin are given in the Typical Characteristics section. The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation of the volume control can be found in Figure 33. The graph focuses on three gain steps with the trip points defined in the first and second columns of the Typical DC Volume Control table. The dotted lines represent the hysteresis about each gain step. Figure 33. DC Volume Control Operation The gain is set by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high pass filter, the dB or cut-off frequency also changes by over six times. Connecting an additional resistor from the input pin of the amplifier to ground, as shown in Figure reduces the cutoff-frequency variation. Figure 34. Resistor on Input for Cut-Off Frequency The input resistance at each gain setting is given in the graph for Input Impedance vs Gain in the Typical Characteristics section. The 3-dB frequency can be calculated using Equation

www.ti.com ƒ ±3 dB 1

2 CR Ri (1)

CAPACITOR, C i fc(highpass) 1 2ZINCi −3 dB fc (2) Ci 1 2Zifc (3) POWER SUPPLY DECOUPLING, C (S) MIDRAIL BYPASS CAPACITOR, C (BYP) TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) To increase filter accuracy, increase the value of the capacitor and decrease the value of the resistor to ground. In addition, the order of the filter can be increased. In a typical application, an input capacitor i is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, C i and the input impedance of the amplifier i form a high-pass filter with the corner frequency determined by Equation The value of C i directly affects the bass (low frequency) performance of the circuit. Consider the example where Z i is k Ω and the specification calls for a flat bass response down to Hz. Equation is reconfigured as Equation In this example, C i is nF, so one would likely choose a value in the range of 0.1 µ F to µ A further consideration for this capacitor is the leakage path from the input source through the input network i and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high-gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, connect the positive lead of the capacitor to the amplifier input in most applications, as the dc level there is held at V DD /2, typically higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. This high-performance CMOS audio amplifier requires adequate power-supply decoupling to minimize output total harmonic distortion (THD). Power-supply decoupling also prevents oscillations with long lead lengths between the amplifier and the speaker. Optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power-supply leads. To filter high-frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µ placed as close as possible to the device V DD lead, works best. For filtering low-frequency noise signals, an aluminum electrolytic capacitor of µ F or greater placed near the audio power amplifier is recommended. The midrail bypass capacitor, C (BYP) is the most critical capacitor and serves several important functions. During startup or recovery from shutdown mode, C (BYP) determines the rate at which the amplifier starts up. The second function is to reduce power-supply noise coupling into the output drive signal. This noise is from the midrail generation circuit internal to the amplifier, and appears as degraded PSRR and THD+N. Bypass capacitor (BYP) values of 0.47- µ F to µ and ceramic or tantalum low-ESR capacitors are recommended for best THD and noise performance.

www.ti.com OUTPUT COUPLING CAPACITOR, C (C) fc(high) 1 2RLC(C) −3 dB fc (4) USING LOW-ESR CAPACITORS TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) In a typical single-supply SE configuration, an output coupling capacitor (C) is required to block the dc bias at the output of the amplifier to prevent dc currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by Equation The main disadvantage, from a performance standpoint, is that load impedances are typically small, driving the low-frequency corner higher, degrading the bass response. Large values of C (C) are required to pass low frequencies into the load. Consider the example where a C (C) of 330 µ F is chosen and loads include Ω Ω Ω Ω k Ω and k Ω Table summarizes the frequency response characteristics of each configuration. Table Common Load Impedances Vs Low Frequency Output Characteristics in SE Mode R L C (C) LOWEST FREQUENCY Ω 330 µ F 161 Hz Ω 330 µ F 120 Hz Ω 330 µ F Hz Ω 330 µ F Hz 10,000 Ω 330 µ F 0.05 Hz 47,000 Ω 330 µ F 0.01 Hz As Table indicates, most of the bass response is attenuated into a Ω load, an Ω load is adequate, headphone response is good, and drive into line level inputs home stereo for example) is exceptional. Low-ESR capacitors are recommended throughout this section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor.

www.ti.com BRIDGED-TIED LOAD VS SINGLE-ENDED MODE Power V(rms) RL V(rms) VO(PP) 2 2 (5) RL 2x VO(PP) VO(PP) −VO(PP) VDD VDD f(c) 1 2RLC(C) (6) TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 Figure shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA0142 amplifier consists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this differential drive configuration, but, initially consider power to the load. The differential drive to the speaker means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to a ground referenced load. Substituting V O(PP) into the power equation, where voltage is squared, yields the output power from the same supply rail and load impedance (see Equation Figure 35. Bridge-Tied Load Configuration In a typical computer sound channel operating at bridging raises the power into an Ω speaker from a singled-ended (SE, ground reference) limit of 250 mW to In sound power, this is a 6-dB improvement loudness that can be heard. In addition to increased power there are frequency-response concerns. Consider the single-supply SE configuration shown in Figure A coupling capacitor is required to block the dc offset voltage from reaching the load. These capacitors can be quite large (approximately µ F to 1000 µ F), so they tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting the low-frequency performance of the system. This frequency-limiting effect is due to the high-pass filter network created with the speaker impedance and the coupling capacitance, and is calculated with Equation For example, a 68- µ F capacitor with an Ω speaker would attenuate low frequencies below 293 Hz. The BTL configuration cancels the dc offsets, eliminating the need for blocking capacitors. Low-frequency performance is then limited only by the input network and speaker response. Cost and PCB space are also minimized by eliminating the bulky coupling capacitor.

www.ti.com RL C(C) VO(PP) VO(PP) VDD −3 dB fc Single-Ended Operation BTL AMPLIFIER EFFICIENCY V(LRMS) VO IDD IDD(avg) TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 Figure 36. Single-Ended Configuration and Frequency Response Increasing power to the load does carry a penalty of increased internal power dissipation. The increased dissipation is understandable, since the BTL configuration produces the output power of the SE configuration. Internal dissipation versus output power is discussed further in the Crest Factor and Thermal Considerations section. In SE mode (see Figure the load is driven from the primary amplifier output for each channel (LOUT+ and ROUT+). The amplifier switches to single-ended operation when the SE/ BTL terminal is held high. This puts the negative outputs in a high-impedance state, and reduces the amplifier's gain by dB. Class-AB amplifiers are inefficient, primarily because of voltage drop across the output-stage transistors. The two components of the internal voltage drop are the headroom or dc voltage drop that varies inversely to output power, and the sine wave nature of the output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from V DD The internal voltage drop multiplied by the RMS value of the supply current DD rms) determines the internal power dissipation of the amplifier. An easy-to-use equation to calculate efficiency begins as the ratio of power from the power supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the load and in the amplifier, the current and voltage waveforms must be understood (see Figure Figure 37. Voltage and Current Waveforms for BTL Amplifiers Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very different between SE and BTL configurations. In an SE application, the current waveform is a half-wave rectified shape, whereas in BTL it is a full-wave rectified waveform. Therefore, RMS conversion factors are different. Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform. Equation and Equation are the basis for calculating amplifier efficiency.

www.ti.com Efficiency of a BTL amplifier PL PSUP Where: PL VLrms2 RL , and VLRMS VP 2 , therefore, PL VP 2RL and PSUP VDD IDDavg and IDDavg 1 VP RL sin(t) dt 1 VP RL [cos(t)] 2VP RL Therefore, PSUP

2 VDD VP

substituting PL and PSUP into equation 7, Efficiency of a BTL amplifier VP 2 RL

4 VDD

Where: (7) PL = Power delivered to load PSUP = Power drawn from power supply VLRMS = RMS voltage on BTL load RL = Load resistance BTL

2 PL RL

Therefore, VP = Peak voltage on BTL load IDDavg = Average current drawn from the power supply VDD = Power supply voltage ηBTL = Efficiency of a BTL amplifier (8) TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 Table employs Equation to calculate efficiencies for four different output-power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half-power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1-W audio system with Ω loads and a 5-V supply, the maximum draw on the power supply is almost 3.25 Table Efficiency vs Output Power in 5-V, Ω BTL Systems EFFICIENCY OUTPUT POWER (W) PEAK VOLTAGE (V) INTERNAL DISSIPATION (W) (%) 0.25 31.4 2.00 0.55 0.50 44.4 2.83 0.62 1.00 62.8 4.00 0.59 1.25 70.2 4.47 (1) 0.53 (1) High peak voltages cause the THD to increase. A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in Equation V DD is in the denominator. This indicates that as V DD goes down, efficiency goes up.

www.ti.com CREST FACTOR AND THERMAL CONSIDERATIONS PdB 10Log PW Pref 10Log 4 W

1 W 6 dB

(9) TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. A typical music CD requires dB to dB of dynamic range, or headroom, above the average power output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest factor between dB and dB. When determining the optimal ambient operating temperature, the internal dissipated power at the average output power level must be used. From the data sheet, one can see that when the device is operating from a 5-V supply into a Ω speaker that 4-W peaks are available. Use Equation to convert watts to dB. Subtracting the headroom restriction to obtain the average listening level without distortion yields: dB dB dB (15-dB crest factor) dB dB dB (12-dB crest factor) dB dB dB (9-dB crest factor) dB dB dB (6-dB crest factor) dB dB dB (3-dB crest factor) Converting dB back into watts: P W PdB/10 P ref mW (18-dB crest factor) 125 mW (15-dB crest factor) 250 mW (9-dB crest factor) 500 mW (6-dB crest factor) 1000 mW (3-dB crest factor) 2000 mW (0-dB crest factor) This is valuable information to consider when estimating the heat-dissipation requirements for the amplifier system. Comparing the worst case, W of continuous power output with a 3-dB crest factor, against 12-dB and 15-dB applications, drastically affects maximum ambient temperature ratings for the system. Using the power dissipation curves for a 5-V, Ω system, the internal dissipation and maximum ambient temperatures are shown in the table below. Table TPA0142 Power Rating, 5-V, Ω Stereo PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT AVERAGE OUTPUT POWER (W) (W/Channel) TEMPERATURE (1) W dB) 1.7 C 1000 mW dB) 1.6 C 500 mW dB) 1.3 C 250 mW (12 dB) 1.0 C 125 mW (15 dB) 0.9 C mW (18 dB) 0.6 C (1) Package limited to C ambient

www.ti.com PDmax 2V2 DD 2RL (10) θJA 1 Derating Factor 1 0.022 45° CW (11) TA Max TJ Max θJA PD 150 45(0.6 2) 96° C (15-dB crest factor) (12) TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 Table TPA0142 Power Rating, 5-V, Ω Stereo PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT AVERAGE OUTPUT POWER (W) (W/Channel) TEMPERATURE (1) 2.5 1250 mW (3-dB crest factor) 0.53 C 2.5 1000 mW (4-dB crest factor) 0.59 C 2.5 500 mW (7-dB crest factor) 0.62 C 2.5 250 mW (10-dB crest factor) 0.55 C (1) Package limited to C ambient The maximum dissipated power Dmax is reached at a much lower output power level for a Ω load than for an Ω load. As a result, the formula in Equation for calculating P Dmax may be used for a Ω application: However, in the case of an Ω load, the P Dmax occurs at a point well above the normal operating power level. The amplifier may therefore be operated at a higher ambient temperature than required by the P Dmax formula for an Ω load, but do not exceed the maximum ambient temperature of The maximum ambient temperature depends on the heatsinking ability of the PCB system. The derating factor for the PWP package is shown in the dissipation rating table. Converting this to θ JA To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are per-channel, so the dissipated heat is doubled for two-channel operation. Given θ JA the maximum allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be calculated using Equation The maximum recommended junction temperature for the device is 150 The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs. NOTE: Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per channel. Due to package limitiations, the actual T AMAX is The power rating tables show that for some applications, no airflow is required to keep junction temperatures in the specified range. The internal thermal protection turns the device off at junction temperatures higher than 150 C to prevent damage to the IC. The power rating tables in this section were calculated for maximum listening volume without distortion. When the output level is reduced the numbers in the table change significantly. Also, using Ω speakers dramatically increases the thermal performance by increasing amplifier efficiency.

www.ti.com SE/ BTL OPERATION ROUT+ 21 R MUX RHPIN RLINEIN ROUT− 16 1 kΩ COUTR 330 µF 100 kΩSE/BTL 15 100 kΩ VDD 32-Step Volume Control 32-Step Volume Control TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 The ability of the TPA0142 to easily switch between BTL and SE modes is one of its most important cost-saving features. This feature eliminates the requirement for an additional headphone amplifier in accommodated. Two separate internal amplifiers drive OUT+ and OUT The SE/ BTL input controls the operation of the follower amplifier that drives LOUT and ROUT When SE/ BTL is held low, the amplifier is on and the device is in the BTL mode. When SE/ BTL is held high, the OUT amplifiers are in a high output-impedance state, which configures the device outputs as SE drivers from LOUT+ and ROUT+. I DD is reduced by approximately one-half in SE mode. Control of the SE/ BTL input can be from a logic-level CMOS source or, more typically, from a resistor-divider network as shown in Figure Figure 38. TPA0142 Resistor Divider Network Circuit Using a readily-available 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When closed, the 100-k Ω /1-k Ω divider pulls the SE/ BTL input low. When a plug is inserted, the 1-k Ω resistor is disconnected and the SE/ BTL input is pulled high. When the input goes high, the OUT amplifier is shut down, muting the speaker (virtually open-circuits the speaker). The OUT+ amplifier then drives through the output capacitor O into the headphone jack.

www.ti.com PC-BEEP OPERATION CPCB 1 2 ƒ PCB (100 k) (13) INPUT MUX OPERATION ROUT+ 21 R MUX RHPIN RLINEIN 0.47 µF CIRLINE 0.47 µF Right Headphone Input Signal Right Line Input Signal CRIN 0.47 µF TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 The PC-BEEP input allows a system beep to be sent directly from a computer through the amplifier to the speakers with few external components. The input is activated automatically. When the PC-BEEP input is active, both LINEIN and HPIN inputs are deselected, and both the left and right channels are driven in BTL mode with the signal from PC-BEEP. The gain from the PC-BEEP input to the speakers is fixed at 0.3 V/V and is independent of the volume setting. When the PC-BEEP input is deselected, the amplifier returns to the previous operating mode and volume setting. Furthermore, if the amplifier is in shutdown mode, activating PC-BEEP takes the device out of shutdown, outputs the PC-BEEP signal, then returns the amplifier to shutdown mode. When PCB ENABLE is held low, the amplifier automatically switches to PC-BEEP mode after detecting a valid signal at the PC-BEEP input. The preferred input signal is a square wave or pulse train. To be accurately detected, the signal must have a minimum of 1.5-V pp amplitude, rise and fall times of less than 0.1 µ s and a minimum of eight rising edges. When the signal is no longer detected, the amplifier returns to its previous operating mode and volume setting. To ac-couple the PC-BEEP input, choose a coupling-capacitor value to satisfy Equation The PC-BEEP input can also be dc-coupled to avoid using this coupling capacitor. The pin normally rests at midrail when no signal is present. Figure 39. TPA0142 Example Input MUX Circuit The input MUX provides the user with a means to select from two different audio sources. In BTL mode, the LINE inputs are selected. In SE mode, the HP inputs are selected. R IN and L IN must be grounded in SE mode.

www.ti.com SHUTDOWN MODES TPA0142 SLOS248E JUNE 1999 REVISED SEPTEMBER 2004 The TPA0142 employs a shutdown mode of operation designed to reduce supply current DD to the absolute minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state, I DD 150 µ SHUTDOWN should never be left unconnected because amplifier operation would be unpredictable. Table Shutdown and Mute Mode Functions INPUTS (1) AMPLIFIER STATE SE/ BTL SHUTDOWN INPUT OUTPUT Low High Line BTL X (2) Low X (2) Mute High High HP SE (1) Inputs should never be left unconnected. (2) X do not care

www.ti.com 30-Mar-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPA0142PWP ACTIVE HTSSOP PWP 24 60 TBD Call TI Call TI -40 to 85 TPA0142 TPA0142PWPR ACTIVE HTSSOP PWP 24 2000 TBD Call TI Call TI -40 to 85 TPA0142 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 30-Mar-2016 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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