TP65H480G4JSGB RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 12
Technical content
Datasheet sections
- 1.1 Pin Assignments
- 1.2 Pin Descriptions
- 2.1 Absolute Maximum Ratings
- 2.2 Thermal Specifications
- 2.3 Electrical Specifications – Forward Device
- 2.4 Electrical Specifications – Reverse Device
Features
■ Gen IV technology ■ JEDEC-qualified GaN technology ■ Dynamic RDS(on)eff production tested ■ Robust design, defined by
- Transient over-voltage capability
- Operation with E-mode gate drivers without need for Zener protection. ■ Negligible Qrr ■ Reduced crossover loss ■ RoHS compliant and Halogen-free packaging ■ 2kV HBM ESD rating
Applications
■ Consumer ■ Power adapters ■ Low power SMPS ■ Lighting Key Specifications VDS (V) 650 VDSS(TR)(V) 800 RDS(on) (mΩ) maximum [1] 560 QOSS (nC) typical 9.2 QG (nC) typical 5.2 1. Dynamic RDS(on); see Figure 17 and Figure 18.
1.1 Pin Assignments
Figure 1. Pin Assignments – Bottom View
1.2 Pin Descriptions
R08DS0327EU0102 Rev.1.02 Nov 21, 2025 Page 4 2. Specifications
2.1 Absolute Maximum Ratings
(Tc = 25°C unless otherwise stated.) Caution: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. Symbol Parameter Minimum Maximum Unit VDSS Drain to source voltage (TJ = -55°C to 150°C) - 650 V VDSS(TR) , non-repetitive Transient drain to source voltage, non-repetitive [1] - 800 VDSS(TR) , repetitive Transient drain to source voltage, repetitive [2] - 750 VGSS Gate to source voltage -20 +20 PD Maximum power dissipation at TC = 25°C - 25 W ID Continuous drain current at TC = 25°C - 5 A Continuous drain current at TC = 100°C - 3.1 A IDM Pulsed drain current (pulse width: 10µs) - 16 A TJ Junction operating temperature -55 +150 °C TS Storage temperature -55 +150 °C TSOLD Reflow soldering temperature [3] - 260 °C 1. In off-state, spike duration < 30µs, non-repetitive. 2. Off-state, spike duration < 5µs. 3. Reflow MSL3.
2.2 Thermal Specifications
Symbol Condition Typical Value Unit RΘJC Junction-to-case 5 °C/W RΘJA Junction-to-ambient [1] 50 1. Device on one layer epoxy PCB for source connection (vertical and without air stream cooling, with 6cm2 copper area and 70µm thickness).
R08DS0327EU0102 Rev.1.02 Nov 21, 2025 Page 5
2.3 Electrical Specifications – Forward Device
TJ = 25°C unless otherwise stated. Symbol Parameter Test Conditions Minimum Typical Maximum Unit VDSS(BL) Maximum drain-source voltage VGS = 0V 650 - - V VGS(th) Gate threshold voltage VDS = VGS, ID = 0.5mA 1.5 2.0 2.5 V ΔVGS(th)/TJ Gate threshold voltage temperature coefficient - -5.8 - mV/°C RDS(on)eff Drain-source on-resistance [1] VGS = 6V, ID = 3A - 480 560 mΩ VGS = 6V, ID = 3A, TJ = 150°C - 1000 - IDSS Drain-to-source leakage current VDS = 650V, VGS = 0V - 1 10 µA VDS = 650V, VGS = 0V, TJ = 150°C - 5 - IGSS Gate-to-source forward leakage current [2] VGS = 20V - - 10 µA Gate-to-source reverse leakage current [2] VGS = -20V - - -10 IGSS Gate-to-source forward leakage current [2] VGS = 6V - - 0.1 µA Gate-to-source reverse leakage current [2] VGS = -6V - - -0.1 CISS Input capacitance VGS = 0V, VDS = 400V, f = 1MHz - 465 - pF COSS Output capacitance - 8 - CRSS Reverse transfer capacitance - 1.2 - CO(er) Output capacitance, energy related [3] VGS = 0V, VDS = 0V to 400V - 11.6 - pF CO(tr) Output capacitance, time related [4] VGS = 0V, VDS = 0V to 400V - 23 - QG Total gate charge VDS = 400V, VGS = 0V to 10V, ID = 3A - 5.2 - nC QGS Gate-source charge - 1.3 - QGD Gate-drain charge - 2.1 - QOSS Output charge VGS = 0V, VDS = 0V to 400V - 9.2 - nC tD(on) Turn-on delay VDS = 400V, VGS = 0V to 6V, ID = 3A, RG = 20Ω, ZFB = 120Ω at 100MHz (see Figure 15) - 23.2 - ns tR Rise time - 4.1 - tD(off) Turn-off delay - 53.6 - tF Fall time - 10 - 1. Dynamic RDS(on), 100% tested; see Figure 17 and Figure 18 for conditions. 2. Including leakage current of the integrated ESD protection circuit. 3. Equivalent capacitance to give same stored energy from 0V to 400V. 4. Equivalent capacitance to give same charging time from 0V to 400V.
R08DS0327EU0102 Rev.1.02 Nov 21, 2025 Page 6
2.4 Electrical Specifications – Reverse Device
TJ = 25°C unless otherwise stated. Symbol Parameter Test Conditions Minimum Typical Maximum Unit IS Reverse current VGS = 0V, TC = 100°C, ≤ 25% duty cycle - - 2.3 A VSD Reverse voltage [1] VGS = 0V, IS = 1.3A - 1.3 - V VGS = 0V, IS = 2.6A - 1.8 - 1. Includes dynamic RDS(on) effect. Note: Reverse recovery charge is negligible, enabled by the LV Si FET technology
Figure 19. Package Outline Drawing – 5 × 6 PQFN
R08DS0327EU0102 Rev.1.02 Nov 21, 2025 Page 11 6. Related Information All technical documents for Renesas GaN Power devices are accessible from the GaN Power Solutions page. 7. Ordering Information Part Number Package Description Package Configuration TP65H480G4JSGB-TR [1] 5 × 6 PQFN IP Source 1. “-TR” suffix refers to tape and reel. 8. Revision History Revision Date Description 1.02 Nov 21, 2025 Updated the document's formatting; no technical changes were completed.
1.01 Aug, 04, 2025 Integrated ESD protection
1.00 Apr 1, 2025 Initial release.
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