TP65H300G4LSGBE RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 15
Technical content
Datasheet sections
- 1.1 Pin Assignments
- 1.2 Pin Descriptions
- 2.1 Absolute Maximum Ratings
- 2.2 Thermal Specifications
- 2.3 Circuit Implementation
- 2.4 Electrical Specifications – Forward Device
- 2.5 Electrical Specifications – Reverse Device
Features
■ Gen IV technology ■ JEDEC-qualified GaN technology ■ Dynamic RDS(on)eff production tested ■ Robust design, defined by
- Transient over-voltage capability
- Operation with E-mode Gate drivers without need for Zener protection ■ Very low QRR ■ Reduced crossover loss ■ RoHS compliant and Halogen-free packaging
Applications
■ Consumer ■ Power adapters ■ Low power SMPS ■ Lighting Specifications VDS (V) 650 VDSS(TR)(V) maximum 800 RDS(on) (mΩ) maximum [1] 312 QOSS (nC) typical 19 QG (nC) typical 12.7 1. Dynamic RDS(on); see Figure 21 and Figure 22. D G S KS
1.1 Pin Assignments
Figure 1. Pin Assignments – Bottom View
1.2 Pin Descriptions
R07DS1596EU0100 Rev.1.00 Apr 9, 2025 Page 4 2. Specifications
2.1 Absolute Maximum Ratings
Tc = 25°C unless otherwise stated. Caution: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. Symbol Parameter Minimum Maximum Unit VDSS Drain to source voltage (TJ = -55°C to 150°C) - 650 V VDSS(TR) , non-repetitive Transient drain to source voltage, non-repetitive [1] - 800 VDSS(TR) , repetitive Transient drain to source voltage, repetitive [2] - 750 VGSS Gate to source voltage -20 +20 PD Maximum power dissipation at TC = 25°C - 31.5 W ID Continuous drain current at TC = 25°C [3] - 8 A Continuous drain current at TC = 100°C [3] - 5 A IDM Pulsed drain current (pulse width: 10µs) - 30 A TC Operating temperature Case -55 +150 °C TJ Junction -55 +150 °C TS Storage temperature -55 +150 °C TSOLD Reflow soldering temperature [4] - 260 °C 1. In off-state, spike duration < 30µs, non-repetitive. 2. Off-state, spike duration < 5µs. 3. For increased stability at high current operation, see “Circuit Implementation”. 4. Reflow MSL3.
2.2 Thermal Specifications
Symbol Condition Typical Value Unit RΘJC Junction-to-case 4 °C/W RΘJA Junction-to-ambient [1] 50 1. Device on one layer epoxy PCB for source connection (vertical and without air stream cooling, with 6cm2 copper area and 70µm thickness).
2.3 Circuit Implementation
Figure 2. Simplified Half-Bridge Schematic Figure 3. Simplified Single-Ended Schematic
- For bridge topologies only. RG could be much smaller in single-ended topologies.
- RCDCL should be placed as close as possible to the drain pin.
R07DS1596EU0100 Rev.1.00 Apr 9, 2025 Page 6
2.4 Electrical Specifications – Forward Device
TJ = 25°C unless otherwise stated. Symbol Parameter Test Conditions Minimum Typical Maximum Unit VDSS(BL) Maximum drain-source voltage VGS = 0V 650 - - V VGS(th) Gate threshold voltage VDS = VGS, ID = 0.5mA 1.2 1.6 2 V ΔVGS(th)/TJ Gate threshold voltage temperature coefficient - -5.8 - mV/°C RDS(on)eff Drain-source on-resistance [1] VGS = 6V, ID = 5A, TJ = 25°C - 240 312 mΩ VGS = 6V, ID = 5A, TJ = 150°C - 492 - IDSS Drain-to-source leakage current VDS = 650V, VGS = 0V, TJ = 25°C - 1.2 12 µA VDS = 650V, VGS = 0V, TJ = 150°C - 8 - IGSS Gate-to-source forward leakage current VGS = 20V - - 100 nA Gate-to-source reverse leakage current VGS = -20V - - -100 CISS Input capacitance VGS = 0V, VDS = 400V, f = 1MHz - 1225 - pF COSS Output capacitance - 16.7 - CRSS Reverse transfer capacitance - 3.4 - CO(er) Output capacitance, energy related [2] VGS = 0V, VDS = 0V to 400V - 23.7 - pF CO(tr) Output capacitance, time related [3] - 48 - QG Total gate charge VDS = 400V, VGS = 0V to 6V, ID = 5A - 12.7 - nC QGS Gate-source charge - 3 - QGD Gate-drain charge - 4.6 - QOSS Output charge VGS = 0V, VDS = 0V to 400V - 19 - nC tD(on) Turn-on delay VDS = 400V, VGS = 0V to 6V, ID = 5A, RG_on = 15Ω, RG_off = 5Ω, ZFB = 120Ω at 100MHz (see Figure 17) - 33 - ns tR Rise time - 5.6 - tD(off) Turn-off delay - 68 - tF Fall time - 10 - 1. Dynamic RDS(on), 100% tested; see Figure 21 and Figure 22 for conditions. 2. Equivalent capacitance to give same stored energy from 0V to 400V. 3. Equivalent capacitance to give same charging time from 0V to 400V.
R07DS1596EU0100 Rev.1.00 Apr 9, 2025 Page 7
2.5 Electrical Specifications – Reverse Device
TJ = 25°C unless otherwise stated. Symbol Parameter Test Conditions Minimum Typical Maximum Unit IS Reverse current VGS = 0V, TC = 100°C, ≤25% duty cycle - - 5 A VSD Reverse voltage [1] VGS = 0V, IS = 10A - 3 - V VGS = 0V, IS = 5A - 1.9 - tRR Reverse recovery time IS = 5A, VDD = 400V, di/dt = 1000A/us - 29 - ns QRR Reverse recovery charge [2] - 0 - nC 1. Includes dynamic RDS(on) effect. 2. Excludes QOSS.
Figure 16. Safe Operating Area TC = 25°C
R07DS1596EU0100 Rev.1.00 Apr 9, 2025 Page 13 5. Package Outline Drawings
R07DS1596EU0100 Rev.1.00 Apr 9, 2025 Page 14 6. Design Considerations The fast switching of GaN devices reduces current-voltage crossover losses and enables high-frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switches requires adherence to specific PCB layout guidelines and probing techniques. Before evaluating Renesas GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power Switches. The following table provides some practical rules that should be followed during the evaluation. When Evaluating Renesas GaN Devices: DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop. Twist the pins of TO-220 or TO-247 to accommodate GDS board layout. Minimize lead length of TO-220 and TO-247 package when mounting to the PCB. Use long traces in drive circuit, long lead length of the devices. Use shortest sense loop for probing; attach the probe and its ground connection directly to the test points. Use differential mode probe or probe ground clip with long wire. 7. Related Information The complete technical library of GaN design tools can be found at Renesas: ■ Evaluation kits ■ Application notes ■ Design guides ■ Simulation models ■ Technical papers and presentations Specific resources include: ■ Printed Circuit Board Layout and Probing for Gan Power Switches ■ Recommendations for Vapor Phase Reflow ■ Recommended External Circuitry for GaN FETs ■ PQFN Tape and Reel Information 8. Ordering Information Part Number Package Description Package Configuration TP65H300G4LSGBE-TR [1] 8 × 8 PQFN Source 1. “-TR” suffix refers to tape and reel. 9. Revision History Revision Date Description 1.00 Apr 9, 2025 Initial release.
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