TP5510

TP5510 NSC | Alldatasheet

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Y Complete A/D and D/A with filter system including: Ð Serial Data Interface Ð Encode high-pass and low-pass filter Ð Decode low-pass filter with sin x/x correction Ð Active RC noise filters Ð m-law compatible A/D and D/A Ð Internal precision voltage reference Ð Internal auto-zero circuitry Y m-lawÐTP5510 Y g5V operation Y Low operating powerÐtypically 60 mW Y Power-down standby modeÐtypically 3 mW Y Automatic power-down Y TTL or CMOS compatible digital interfaces Y Maximizes PC card circuit density Y Plastic DIP and SOIC packages Y 8-bit digital I/O Y 13-bit dynamic range Y Use with DSP processor Y Applications: Tapeless Answering Machines, Cordless Phones, Cellular Radio Connection Diagram Dual-In-Line Package TL/H/11186–1 Top View Order Number TP5510WM See NS Package Number M16B Order Number TP5510N See NS Package Number N16A TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

TL/H/11186–2 FIGURE 1 Pin Description Symbol Function VBB Negative power supply pin. V BB eb 5V g5%. GNDA Analog ground. All signals are referenced to this pin. VFDO Analog output of the receive power ampli- fier. VCC Positive power supply pin. V CC ea 5V g5%. Symbol Function FSD Decode frame sync pulse which enables BCLKR to shift data into D D.F S D is an 8 kHz pulse train. See Figures 2 and 3 for timing details. DD Decode data input. Data is shifted into D D following the FS D leading edge. BCLKD/CLKSEL The bit clock which shifts data into D D af- ter the FS D leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLK D is used for both encode and de- code directions (see Table 1). http:/ /www.national.com 2

Pin Description (Continued) Symbol Function MCLKD/PDN Encode master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asyn- chronous with MCLK E, but should be syn- chronous with MCLK E for best perform- ance. When MCLK D is connected continu- ously low, MCLK E is selected for all inter- nal timing. When MCLK D is connected continuously high, the device is powered down. MCLK E Encode master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asyn- chronous with MCLK D. Best performance is realized from synchronous operation. FSE Encode frame sync pulse input which en- ables BCLK E to shift out the data on D E. FSE is an 8 kHz pulse train, see Figures 2 and 3 for timing details. BCLKE The bit clock which shifts out the data on DE. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLK E. DE The TRI-STATE É data output which is en- abled by FS E. TSE Open drain output which pulses low during the A/D time slot. GSE Analog output of the encode input amplifi- er. Used to externally set gain. VFEIb Inverting input of the encode input amplifi- er. VFEIa Non-inverting input of the encode input amplifier. Functional Description POWER-UP When power is first applied, power-on reset circuitry initializ- es the AFE and places it into a power-down state. All non- essential circuits are deactivated and the D E and VF DO out- puts are put in high impedance states. To power-up the de- vice, a logical low level or clock must be applied to the MCLK D/PDN pin and FSE and/or FS D pulses must be pres- ent. Thus, 2 power-down control modes are available. The first is to pull the MCLK D/PDN pin high; the alternative is to hold both FS E and FS D inputs continuously lowÐthe device will power-down approximately 2 ms after the last FS E or FSD pulse. Power-up will occur on the first FS E or FS D pulse. The TRI-STATE data output, D E, will remain in the high impedance state until the second FS E pulse. SYNCHRONOUS OPERATION For synchronous operation, the same master clock and bit clock should be used for both the encode and decode direc- tions. In this mode, a clock must be applied to MCLK E and the MCLK D/PDN pin can be used as a power-down control. A low level on MCLK D/PDN powers up the device and a high level powers down the device. In either case, MCLK E will be selected as the master clock for both the encode and decode circuits. A bit clock must also be applied to BCLK E and the BCLK D/CLKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device auto- matically compensates for the 193rd clock pulse each frame. With a fixed level on the BCLK D/CLKSEL pin, BCLK E will be selected as the bit clock for both the encode and decode directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLK CLKSEL. In this synchronous mode, the bit clock, BCLK E, may be from 64 kHz to 2.048 MHz, but must be synchro- nous with MCLK Each FS E pulse begins the encoding cycle and the data from the previous encode cycle is shifted out of the enabled D E output on the positive edge of BCLK E. After 8-bit clock periods, the TRI-STATE D E output is returned to a high im- pedance state. With an FS D pulse, data is latched via the DD input on the negative edge of BCLK E (or BCLK D if run- ning). FS E and FS D must be synchronous with MCLK E/D. TABLE I. Selection of Master Clock Frequencies BCLKD/CLKSEL Master Clock Frequency Selected TP5510 Clocked 1.536 MHz or 1.544 MHz 0 2.048 MHz 1 1.536 MHz or 1.544 MHz ASYNCHRONOUS OPERATION For asynchronous operation, separate encode and decode clocks may be applied. MCLK E and MCLK D must be 1.536 MHz or 1.544 MHz for the TP5510, and need not be synchronous. For best transmission performance, however, MCLK D should be synchronous with MCLK E, which is easily achieved by applying only static logic levels to the MCLK D/ PDN pin. This will automatically connect MCLK E to all inter- nal MCLK D functions (see Pin Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FS E starts each A/D conver- sion cycle and must be synchronous with MCLK E and BCLKE.F S D starts each D/A conversion cycle and must be synchronous with BCLK D. BCLK D must be a clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLK E and BCLK D may operate from 64 kHz to 2.048 MHz. SHORT FRAME SYNC OPERATION The AFE can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the device as- sumes a short frame mode. In this mode, both frame sync pulses, FS E and FS D, must be one bit clock period long, with timing relationships specified in Figure 2 . With FS E high during a falling edge of BCLK E, the next rising edge of BCLKE enables the D E TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge dis- ables the D E output. With FS D high during a falling edge of BCLKD (BCLKE in synchronous mode), the next falling edge of BCLK E latches in the sign bit. The following seven falling http:/ /www.national.com3

Functional Description (Continued) edges latch in the seven remaining bits. Both devices may utilize the short frame sync pulse in synchronous or asyn- chronous operating mode. LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FS E and FS D, must be three or more bit clock periods long, with timing relationships specified in Figure 3 . Based on the transmit frame sync, FS E, the AFE will sense whether short or long frame sync pulses are being used. For 64 kHz oper- ation, the frame sync pulse must be kept low for a minimum of 160 ns. The D E TRI-STATE output buffer is enabled with the rising edge of FS E or the rising edge of BCLK E, which- ever comes later, and the first bit clocked out is the sign bit. The following seven BCLK E rising edges clock out the re- maining seven bits. The D E output is disabled by the falling BCLKE edge following the eighth rising edge, or by FS E going low, whichever comes later. A rising edge on the de- code frame sync pulse, FS D, will cause the data at D D to be latched in on the next eight falling edges of BCLK D (BCLKE in synchronous mode). Both devices may utilize the long frame sync pulse in synchronous or asynchronous mode. ENCODE SECTION The encode section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4 . The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be real- ized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-ca- pacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the A/D sample-and-hold circuit. The A/D is of compressing type according to m-law coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (t MAX) of nomi- nally 2.5V peak (See Table of Transmission Characteris- tics). The FS E frame sync pulse controls the sampling of the filter output, and then the successive-approximation encod- ing cycle begins. The 8-bit code is then loaded into a buffer and shifted out through D E at the next FS E pulse. The total encoding delay will be approximately 165 ms (due to the encode filter) plus 125 ms (due to encoding delay), which totals 290 ms. Any offset voltage due to the filters or com- parator is cancelled by sign bit integration. DECODE SECTION The decode section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The DAC is m-law and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/power amplifier capable of driving a 600X load to a level of 7.2 dBm. The decode section is unity-gain. Upon the occurrence of FS D, the data at the D D input is clocked in on the falling edge of the next eight BCLK D (BCLKE) periods. At the end of the DAC time slot, the D/A conversion cycle begins, and 10 ms later the DAC output is updated. The total DAC delay is E10 ms (DAC update) plus 110 ms (filter delay) plus 62.5 ms( (/2 frame), which gives approximately 180 ms. http:/ /www.national.com 4

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. V CC to GNDA 7V VBB to GNDA b7V Voltage at any Analog Input or Output V CCa0.3V to V BBb0.3V Voltage at any Digital Input or Output V CCa0.3V to GNDA b0.3V Operating Temperature Range b25§Ct o a 125§C Storage Temperature Range b65§Ct o a150§C Lead Temperature (Soldering, 10 seconds) 300 §C ESD (Human Body Model) 2000V Latch-Up Immunity e 100 mA on any Pin Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V CC e 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACE VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.2 V VOL Output Low Voltage D E,I Le3.2 mA 0.4 V SIGD,I Le1.0 mA 0.4 V TSE,I Le3.2 mA, Open Drain 0.4 V VOH Output High Voltage D E,I Heb3.2 mA 2.4 V SIGD,I Heb1.0 mA 2.4 V IIL Input Low Current GNDA sVINsVIL, All Digital Inputs b10 10 mA IIH Input High Current V IHsVINsVCC b10 10 mA IOZ Output Current in High Impedance D E, GNDA sVOsVCC b10 10 mAState (TRI-STATE) ANALOG INTERFACE WITH ENCODE INPUT AMPLIFIER (ALL DEVICES) IIEA Input Leakage Current b2.5VsVsa2.5V, VF EIa or VF EIb b200 200 nA RIEA Input Resistance b2.5VsVsa2.5V, VF EIa or VF EIb 10 M X ROEA Output Resistance Closed Loop, Unity Gain 1 3 X RLEA Load Resistance GS E 10 k X CLEA Load Capacitance GS E 50 pF VOEA Output Dynamic Range GS E,R Lt10 k X b2.8 2.8 V AVEA Voltage Gain VF EIa to GS E 5000 V/V FUEA Unity Gain Bandwidth 1 2 MHz VOSEA Offset Voltage b20 20 mV VCMEA Common-Mode Voltage CMRREA l 60 dB b2.5 2.5 V CMRREA Common-Mode Rejection Ratio DC Test 60 dB PSRREA Power Supply Rejection Ratio DC Test 60 dB ANALOG INTERFACE WITH DECODE FILTER (ALL DEVICES) RODF Output Resistance Pin VF DO1 3 X RLDF Load Resistance VF DOeg2.5V 600 X CLDF Load Capacitance 500 pF VOSDO Output DC Offset Voltage b200 200 mV POWER DISSIPATION (ALL DEVICES) ICC0 Power-Down Current No Load (Note) 0.5 3 mA IBB0 Power-Down Current No Load (Note) 0.05 1 mA ICC1 Power-Up Active Current No Load 6.0 12 mA IBB1 Power-Up Active Current No Load 6.0 12 mA Note: ICC0 and I BB0 are measured after first achieving a power-up state. http:/ /www.national.com5

Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V CC e 5.0V, V BB eb 5.0V, T A e 25§C. All timing parameters are measured at V OH e 2.0V and V OL e 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units 1/tPM Frequency of Master Clocks Depends on the Device Used and the 1.536 MHz BCLKD/CLKSEL Pin. 1.544 MHz MCLKE and MCLK D 2.048 MHz tDM Rise Time of Master Clock MCLK E and MCLK D 50 ns tFM Fall Time of Master Clock MCLK E and MCLK D 50 ns tPB Period of Bit Clock 485 488 15725 ns tDB Rise Time of Bit Clock BCLK E and BCLK D 50 ns tFB Fall Time of Bit Clock BCLK E and BCLK D 50 ns tWMH Width of Master Clock High MCLK E and MCLK D 160 ns tWML Width of Master Clock Low MCLK E and MCLK D 160 ns tSBFM Set-Up Time from BCLK E High First Bit Clock after the Leading 100 ns to MCLK E Falling Edge Edge of FS E tSFFM Set-Up Time from FS E High Long Frame Only 100 ns to MCLK E Falling Edge tWBH Width of Bit Clock High V IHe2.2V 160 ns tWBL Width of Bit Clock Low V ILe0.6V 160 ns tHBFL Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync tHBFS Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync tSFB Set-Up Time from Frame Sync Long Frame Only 115 ns to Bit Clock Low tDBD Delay Time from BCLK E High Load e150 pF plus 2 LSTTL Loads 0 140 ns to Data Valid tDBTS Delay Time to TS E Low Load e150 pF plus 2 LSTTL Loads 140 ns tDZC Delay Time from BCLK E Low to C Le0 pF to 150 pF 50 165 ns Data Output Disabled tDZF Delay Time to Valid Data from C Le0 pF to 150 pF 20 165 ns FSE or BCLK E, Whichever Comes Later tSDB Set-Up Time from D D Valid to 50 ns BCLKD/E Low tHBD Hold Time from BCLK D/E Low to 50 ns DD Invalid tSF Set-Up Time from FS E/D to Short Frame Sync Pulse (1 Bit Clock 50 ns BCLKE/D Low Period Long) tHF Hold Time from BCLK E/D Low Short Frame Sync Pulse (1 Bit Clock 100 ns to FS E/D Low Period Long) tHBFl Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns Bit Clock Low to Frame Sync Clock Periods Long) (FS E or FS D) tWFL Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns Sync Pulse (Low Level) http:/ /www.national.com 6

Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, V IN e 0 dBm0, encode input amplifier connected for unity gain non-inverting. Typicals specified at V CC e 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE Absolute Levels Nominal 0 dBm0 Level is 4 dBm (Definition of Nominal Gain) (600 X) 0 dBm0 1.2276 Vrms tMAX Max Overload Level TP5510, (3.17 dBm0) 2.501 V PK GEA Encode Gain, Absolute T Ae25§C, V CCe5V, V BBeb5V Input at GS Ee0 dBm0 at 1020 Hz b0.5 0.5 dB GER Encode Gain, Relative to G EA fe16 Hz b35 dB fe50 Hz b25 dB fe60 Hz b21 dB fe200 Hz b2.0 b0.1 dB fe300 Hz b3000 Hz b0.5 0.15 dB fe3400 Hz b1.5 0.5 dB fe4000 Hz b10 dB fe4600 Hz and Up, Measure b25 dB Response from 0 Hz to 4000 Hz with Temperature GERL Encode Gain Variations with Sinusoidal Test Method Level Reference Level eb10 dBm0 VFEIa eb40 dBm0 to a3 dBm0 b0.4 0.4 dB VFEIa eb50 dBm0 to b40 dBm0 b0.8 0.8 dB GDA Decode Gain, Absolute T Ae25§C, V CCe5V, V BBeb5V InputeDigital Code Sequence for 0 dBm0 Signal at 1020 Hz b0.5 0.5 dB GDR Decode Gain, Relative to G DA fe0 Hz to 3000 Hz b0.5 0.5 dB fe3400 Hz b1.5 0.5 dB fe4000 Hz b14 dB with Temperature with Supply Voltage GDRL Decode Gain Variations with Sinusoidal Test Method; Reference Level Input PCM Code Corresponds to an Ideally Encoded PCM Level eb40 dBm0 to a3 dBm0 b0.4 0.4 dB eb50 dBm0 to b40 dBm0 b0.8 0.8 dB eb55 dBm0 to b50 dBm0 b2.5 2.5 dB VDO Decode Output Drive Level R Le600X b2.5 2.5 V http:/ /www.national.com 8

Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, V IN e 0 dBm0, encode input amplifier connected for unity gain non-inverting. Typicals specified at V CC e 5.0V, V BB e b5.0V, T A e 25§C. (Continued) Symbol Parameter Conditions Min Typ Max Units NOISE NEC Encode Noise, C Message TP5510 (Note 1) 12 16 dBrnC0 Weighted NDC Decode Noise, C Message Digital Code is Alternating Positive Weighted and Negative Zero ÐTP5510 8 11 dBrnC0 NDS Noise, Single Frequency f e0 kHz to 100 kHz, Loop Around b53 dBm0 Measurement, VF EIa e0 Vrms PPSRE Positive Power Supply Rejection, VF EIa eb 50 dBm0 Encode V CCe5.0 V DCa100 mVrms fe0 kHz–50 kHz (Note 2) b30 dBC NPSRE Negative Power Supply Rejection, VF EIa eb 50 dBm0 Encode V BBeb5.0 V DCa100 mVrms fe0 kHz–50 kHz (Note 2) b30 dBC PPSRD Positive Power Supply Rejection, PCM Code Equals Positive Zero Decode V CCe5.0 V DCa100 mVrms Measure VF D0 fe0 Hz–4000 Hz 30 dBC fe4 kHz–50 kHz 30 dB NPSRD Negative Power Supply Rejection, PCM Code Equals Positive Zero Decode V BBeb5.0 V DCa100 mVrms Measure VF D0 fe0 Hz–4000 Hz 30 dBC fe4 kHz–50 kHz 30 dB http:/ /www.national.com9

Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, V IN e 0 dBm0, encode input amplifier connected for unity gain non-inverting. Typicals specified at V CC e 5.0V, V BB e b5.0V, T A e 25§C. (Continued) Symbol Parameter Conditions Min Typ Max Units SOS Spurious Out-of-Band Signals Loop Around Measurement, 0 dBm0, b30 dB at the Channel Output 300 Hz to 3400 Hz Input Digital Code Applied at D D.

4600 Hz–7600 Hz b30 dB

7600 Hz–8400 Hz b30 dB

8400 Hz–100,000 Hz b30 dB

STDE Signal to Total Distortion Sinusoidal Test Method (Note 3) STDD Encode or Decode e 3.0 dBm0Level 28 dBC Half-Channel e 0 dBm0 to b30 dBm0 30 dBC eb 40 dBm0 25 dBC SFDE Single Frequency Distortion, b41 dB Encode SFDD Single Frequency Distortion, b41 dB Decode IMD Intermodulation Distortion Loop Around Measurement, VFEncodea eb4 dBm0 to b21 dBm0, Two Frequencies in the Range

300 Hz–3400 Hz

CTE-D Encode to Decode Crosstalk, f e300 Hz–3400 Hz 0 dBm0 Encode Level D DeQuiet Code b90 b70 dB CTD-E Decode to Encode Crosstalk, f e300 Hz–3400 Hz, VF EIeMultitone b90 b70 dB 0 dBm0 Decode Level (Note 2) Format at D E Output TP5510 m-Law VIN (at GS E)ea Full-Scale 10000000 VIN (at GS E)e0V 11111111 Ð01111111 VIN (at GS E)ebFull-Scale 00000000 http:/ /www.national.com 10

While the pins of the AFE are well protected against electri- cal misuse, it is recommended but not mandatory that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a ‘‘hot’’ socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 mF supply decou- pling capacitors should be connected from this common ground point to V CC and V BB, as close to the device as possible. For best performance, if more than 1 AFE is on a card, the ground point of each AFE on a card should be connected to a common card ground in star formation, rather than via a ground bus. This common ground point should be decoupled to V CC and VBB with 10 mF capacitors. Physical Dimensions inches (millimeters) unless otherwise noted Molded Small Outline Package (WM) Order Number TP5510WM http:/ /www.national.com11

TP5510 Full Duplex Analog Front End (AFE) for Consumer Applications Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number TP5510N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Southeast Asia Japan Ltd. Fax: a49 (0) 180-530 85 86 Fax: (852) 2376 3901 Tel: 81-3-5620-7561Americas Email: europe.support @ nsc.com Email: sea.support @ nsc.com Fax: 81-3-5620-6179Tel: 1(800) 272-9959 Deutsch Tel: a49 (0) 180-530 85 85Fax: 1(800) 737-7018 English Tel: a49 (0) 180-532 78 32Email: support @ nsc.com Fran3ais Tel: a49 (0) 180-532 93 58 Italiano Tel: a49 (0) 180-534 16 80http:/ /www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.