TP5156A

TP5156A NSC | Alldatasheet

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8| TP5116A, TP5116A-1, TP5156A, TP5156A-1 ~ sane 2 | Monolithic CODECs < General Description Features © | The TP5116A and TP5156A are monolithic PCM CODECs = ™_TP5116A—p-law coding (sign plus magnitude format) = | implemented with double-poly CMOS technology. The ™ TP5156A—A-law coding rq TP5116A is intended for u-law applications and the ™ Synchronous or asynchronous operation Lad TPS156A is for A-law applications. @ Precision voltage reference on-chip ‘| Each device contains separate D/A and A/D circuitry, all m Internal sample-and-hold capacitors 2 necessary sample and hold capacitors, and internal auto- — internal auto-zero circuit ib zero circuits. Each device also contains a precision internal gy {ow operation power—40 mW typical @. | voltage reference, eliminating the need for an extemal refer- 4 5v operation F | ence. There are no internal connections to pins 15 or 16, TIL ope ible digital intert making them directly interchangeable with CODECs using © compatible digital interface external reference components. All devices are intended to be used with the TP3040 mono- lithic PCM filter which provides the input anti-aliasing func- tion for the encoder, smooths the output of the decoder and corrects for the sin x/x distortion introduced by the decoder sample and hold output. Simplified Block Diagram ve at} T= H ‘ANALOG INPUT SAR LOGIC DIGITAL OUTPUT HOLD A/D COMPARATOR rT XMIT SYNC REFERENCE CONTROL yl MASTER CLOCK i RCV CLOCK RCV SYNC ‘SAMPLE AND HOLD ‘ANALOG OUTPUT Z <| P| a sare i OIGITAL INPUT ANALOG GND DIGITAL GND Ve TUH/6663-1 1-202

ay, 3 ANALOG INPUT 1 16 ENC 2 vee 15 enc = vos 14 -ANALOG GROUND 2 Noa 13 ANALOG OUTPUT . WASTER CLOCK 5 12,-oietaL INPUT 3 XMIT SYNC 6 11 0iGiTAL GROUND a XMIT CLOCK 47 10 RCV CLOCK a DIGITAL OUTPUT 48 gfe Rev swe $ TUH/6663-2 a Top View a Order Number TP5116AJ or TP5156AJ a See NS Package Number J16A, > Description of Pin Functions Symbol Function Symbol Function ANALOG INPUT ANALOG INPUT to the encoder. This RCV SYNC Decoder frame sync pulse. Normally oc- signal will be sampled at the beginning curring at an 8 kHz rate, this pulse is of the encoder time slot and the result- nominally eight RCV CLOCK cycles ing PCM code will be shifted out during wide. the subsequent encode time slot. RCV CLOCK Receive bit clock input used to shift in v+ 5V(+5%) Power Supply. the PCM data on DIGITAL INPUT. May v- —5V(+5%) Power Supply. operate from 64 kHz to 2.048 MHz. May NC Unused. be asynchronous with XMIT CLOCK. MASTER CLOCK MASTER CLOCK input used to operate DIGITAL GROUND Al digital levels referenced to the DIGI- the internal encode and decode se- Pin. quencers. Should be 1.536 MHz, DIGITALINPUT Serial PCM data input to the decoder. 1.544 MHz or 2.048 MHz. During the decoder time slot, PCM data XMIT SYNC Encoder frame sync pulse. Normally oc- wifcant bit fret on the Fis pe curring at an 8 kHz rate, this pulse is nominally eight XMIT CLOCK cycles RCV CLOCK. wide. ANALOG OUTPUT ANALOG OUTPUT from the decoder. XMITCLOCK Transmit bit clock input used to shift out The decoder sample and hold amplifier the PCM data on DIGITAL OUTPUT. is updated approximately 15 ys after May operate from 64 kHz to 2.048 MHz. the end of the decode time slot. May be asynchronous with RCV ANALOG - CLOCK. GROUND All analog signals are referenced to the DIGITAL OUTPUT Serial PCM TRI-STATE output from en- ANALOG GROUND pin. coder. During the encoder time slot, the PCM code for the previous sample of ANALOG INPUT is shifted out, most significant bit first, on the rising edge of XMIT CLOCK. 4-203

< ENCODING FORMAT AT DIGITAL OUTPUT b TP5116A TPS186A a Sign + Magnitude ALaw i (Includes Even Bit Inversion) s Vin = +Full-Scale 1 4 4 4 4 4 4 Ff 4 0 4 0 4 0 1 0 ® 1 0 0 0 0 0 O© Of 4 4 O08 4 GO 4 0 1 i] | Yn ov fo 0 0 © © 0 ojo 1 0 + ot oO 4 Ee Vin = —Full-Scale o 4 4 41 4 4 4 4/0 0 4 0 1 +20 1 0 | Functional Description ENCODING DELAY = diate _ =| Approximately 4 ys after the rising edge of the XMIT SYNC he encoding process begins immediately at the beginning wo ‘ of the encode time slot and is concluded no later than 18 a pulse, the voltage present on the ANALOG INPUT is sam- " a i = n time slots later. In normal applications, the PCM data is not pled and the process of encoding that sample into a PCM . " aoa a code is begun. Simultaneously, the 8-bit PCM code corre- shifted out until the next time siot 125 ys later, resulting in PJ Is begun. Simul ye an encoding delay of 125 ys. In some applications it is pos- 4 sponding to the previous sample is shifted out of the DIGI- ' " na sible to operate the CODEC at a higher frame rate to reduce by TAL OUTPUT, MSB first, on the rising edge of the next eight * wo Pitag this delay. With a 2.048 MHz MASTER CLOCK, the FS rate B.| cycles of the XMIT CLOCK. When XMIT SYNG (which is could be increased to 15 kHz, reducing the delay from 125 F | normally eight XMIT CLOCK cycles long) goes low, the TRI- 8 to 67 ps " 9 y STATE DIGITAL OUTPUT is returned to the high imped- ” ws. ance state. On the TP5116A, the PCM code is in a p-law DECODING DELAY sign plus magnitude format. The TP5156A uses the stan- The decoding process begins immediately after the end of dard A-law coding. the decoder time slot. The output of the decoder sample An 8-bit PCM code is shifted into DIGITAL INPUT on the and hold amplifier is updated 28 MASTER CLOCK cycles rising edge of the first eight RCV CLOCK pulses after RCV later. The decoding delay is therefore approximately 28 SYNG goes high. RCV SYNC is nominally eight RCV clock cycles plus one half of a frame time or, 81 ys fora CLOCK cycles wide. Approximately 15 ys after RCV SYNC 1.544 MHz system with an 8 kHz frame rate or, 76 us fora goes low, the ANALOG OUTPUT is updated to the voltage 2.048 MHz system with an 8 kHz frame rate. Again, for corresponding to the PCM input code. some applications the frame rate could be increased to re- All encoding and decoding operations are run from the duce this delay. MASTER CLOCK. MASTER CLOCK should be in the range of 1.536 MHz to 2.048 MHz and must be synchronous with XMIT CLOCK. The XMIT and RCV CLOCK may vary from 64 kHz to 2.048 MHz. 1-204

. . . uv Typical Application a A typical application of these CODECs used in conjunction The power supply decoupling capacitors should be 0.1 pF. a with the TP3040 PCM filter is shown below. The values of In order to take advantage of the excellent noise perform- > resistor R1 and DC blocking capacitor C1, are non-critical. ance of these CODECs, care must be taken in board layout a The capacitor value should exceed 0.1 uF, R1 should be to prevent coupling of digital noise into the sensitive analog a Jess than 50 kf, and the product R1XC1 should exceed 4 lines, For card insertion into a hot connector, care should be — ms. taken to insure that GNDA and GNDD are contacted prior to a R3 + Voc and Ves. > XMIT GAIN = 20 x log (®3*) + 3B = R2 3 R4 uv Vv = — RCV GAIN = 20 x log (x a =) & a xx >0.1 uF vu FROM ANALOG a suc Vey Vpx0 rg 1) MASTER CLK FA a D> Ve 350K DIG OUT g Sy v, XMIT SYNC . V RS TPO Cnoy unto wr cux PwRO- PDN Hv | 1P5116/56 PwROF GNDD GNDD RCV SYNC Re Law] Ven Viel ae em 7 RS O.t uF Voc ot “T 5" uF y Jt eb tout our Vss NOTE: b = ANALOG GROUND aL = DIGITAL GROUND TL/H/6683-5 1-205

p S| Absolute Maximum Ratings

2 If Military/Aerospace specified devices are required, Voltage at Any Analog

a please contact the Natlonal Semiconductor Sales Input or Output V--0.3V to V+ +0.3V ld Office/Distributors for availability and specifications. Voltage at Any Digital s Operating Temperature —25°C to + 125°C Input or Output GNDD-—0.3V toV+ + 0.3V i | Storage Temperature —65°C to + 150°C Lead Temperature eo V+ with Respect to DIGITAL GROUND 7 (Solderdip 10 sec.) 300°C Fy) v with Respect to DIGITAL GROUND -7Wv ESO rating to be determined. %| DC Electrical Characteristics o Unless otherwise noted Ta = 0°C to 70°C, V+ = 5.0V +5%, V- = —5.0V +5%. Typical characteristics are specified at V* = = 5.0V,V- = —5.0V and Ta = 25°C. All digital signals are referenced to DIGITAL GROUND. All analog signals are referenced rd to ANALOG GROUND. Limits printed in bold characters are guaranteed for V+ = 5.0V +5%, V- = —5.0V 45%; Ta = O°C to 70°C by correlation with 100% electrical testing at Ta = 25°C. Ail other limits are assured by correlation with other production = g at Ta 2 tests and/or product design and characterization. S| symbor [Parameter | Conditions [win [tye [wax | unite ib | DIGITAL INTERFACE ANALOG INTERFACE Zz Analog Input Impedance Resistance in Series with ka when Sampling Approximately 70 pF Zo Output Impedance at Analog 0 Output POWER DISSIPATION INPUT is a PCM bit stream generated by passing a 0 dBm0, 1.02 kHz sine wave through an ideal encoder. All output levels are sin x/x corrected, limits printed in bold characters are guaranteed for V+ = 5.0V +5%, V~ = —5.0V +5%;Ta = 0°C to 70°C by correlation with 100% electrical testing at Ta = 25°C. All other limits are assured by correlation with other production tests and/or product design and characterization. symbol | ___ Parameter |= Conditions | in_‘| Typ | Max | Unite Absolute Level The nominal 0 dBm0 levels for the TP5116A is 1.227 Vrms and 1.231 Vrms for the TP5156A. The resulting nominal overload level is 2.5V peak for all devices. All gain measurements for the encode and decode portions of the devices are based on these nominal levels after the necessary sin x/x corrections are made. Gra Receive Gain, Absolute Ta = 25°C, V+ = 5V,V- = —5V TP5116A, TP5156A dB TP5116A-1, TP5156A-1 dB Grat Absolute Receive Gain Ta = 0°C to 70°C « Variation with Temperature 1-206

DIGITAL INPUT is a PCM bit stream generated by passing a 0 dHm0, 1.02 kHz sine wave through an ideal encoder. All output | > levels are sin x/x corrected. Limits printed in bold characters are guaranteed for V+ = 5.0V +5%,V~ = -5.0V 45%; Ta= | 0°C to 70°C by correlation with 100% electrical testing at Ta = 25°C. All other limits are assured by correlation with other uv Production tests and/or product design and characterization. a symbol | ____ Parameter | Conaitons win] typ [Max [unite | Grav Absolute Receive Gain V+ = 5V 46%, V- = -5V+5% ~0.07 0.07 4B i Variation with Supply Voltage 5 Gxa Transmit Gain, Absolute Ta = 25°C, V+ = 5V,V- = —5V uo TP5116A, TP5156A -0.125 8 g TP5116A-1, TP5156A-1 -0.175 g Gyat Absolute Transmit Gain Ta = O°C to 70°C 8 Pd Variation with Temperature 3 Gxav Absolute Transmit Gain V+ = 5V $5%,V~ = —5V 45% _ a Variation with Supply Voltage 0.07 0.07 08 x Grat Absolute Receive Gain CCITT Method 2 Relative to > Variation with Level —10 d8m0 = 0 dBm0 to 3 dBmO -0.3 O38 4B ~40 dBm0 to 0 dBmo -0.2 0.2 dB —50 dBm0 to —40 dBmo -0.4 04 dB —55 dBm0 to —50 d8m0 -1.0 1.0 dB Gxar Absolute Transmit Gain CCITT Method 2 Relative to Variation with Level —10 dBmo 0 dBm0 to 3 dBmo -0.3 os d8 ~ 40 dBm0 to 0 dBmo -0.2 0.2 dB -50 dBm0 to —40 dBmo TP5116A, TP5156A -0.4 0.4 dB TP5116A-1, TP5156A-1 -0.475 0.475 dB —55 dBm0 to —50 d8mo -1.0 1.0 dB STOR Receive Signal to Distortion Sinusoidal Test Method Input Ratio Level —30 dBm0 to 0 dBmo dBc 40 dBm aBC —45 dBm0 aBC STDx Transmit Signal to Distortion Sinusoidal Test Method Input Ratio Level —30 dBm0 to 0 dBmo aBC —40 dBmo aBC —45 dBmo dBc Nr Receive Idle Channel Noise Dp = Idle Code [| {8 _[ _amnco Nx Transmit Idle Channel Noise TP5116A, VFx = OV dBrnCo TP5156A, VFy = OV dBmop PPSRx | Positive Power Supply Input Level = OV, Voc = 5.0 Voc 8 Rejection, Transmit +300 mVims, f = 1.02 kHz PPSAR | Positive Power Supply Dr = Idle Code Rejection, Receive Voc = 5.0 Voc + 300 mVrms, dB f = 1.02 kHz NPSRx | Negative Power Supply Input Level = OV, Vas = —5.0 Voc 4B Rejection, Transmit +300 mVrms, f = 1.02 kHz NPSRp | Negative Power Supply Dp = Steady PCM Code, Rejection, Receive Ves = —5.0 Vp¢ + 300 mVrms, aB f = 1.02 kHz CTxr__| Transmit to Receive Crosstalk | Dp = Steady PCM Code ee ee es 7) CTrx Receive to Transmit Crosswalk | Transmit Input Level = OV TP5116A -70 4B TP5156A -65 dB (Note 2) Note 1: Measured by extrapolation from the distortion test result at —50 dBm0 level. Note 2: Theoretical worst-case for a perfectly zeroed encoder with alternating sign bit, due to the decoding law. 1-207

br Timing Specifications uniess otherwise noted, Ta = 0°C to 70°C, V+ — +5V45%, V- = —5V + 5%. All 2 digital signals are referenced to DIGITAL GROUND and are measured at Vij and Vj as indicated in the Timing Waveforms. a Limits printed in bold characters are guaranteed for V+ = 5.0V +5%,V- = —5.0V +5%; Ta = 0°C to 70°C by correlation 2 | with 100% electrical testing at Ta = 25°C. All other limits are assured by correlation with other production tests and/or product B|_symoor [Parameter | Conaitions [win [tye | Max | unite by | Fu MASTER CLOCK Frequency [| | 18 | zen | ot | Me E| fara [xu rovetock Frequency | |e | 20ee | 21 | Mie &|_PWoux | Glock Pulse width MASTER,xmiT,ACvcLocKs | 150 | | ‘| __ns © |_trotec | Clock Rise and Fall Time MASTER, XmiT,RCvcLocks | | ——s«|_ 50 | ns 4© | tas.tes | Sync Pulse Rise and Fall Time RCV, XMIT, SYNC [| | os = trcs, txos | Clock to Sync Delay RCV, XMIT | o | | | os 8 |_uss XMIT SYNC Set-Up Time a i |_%00 XMIT Data Delay Load=100pF+2ustTLLoads | | _—s«|_200 | __ ns FE | top XMIT Data Present Load= 100pF+2tsTtLLoads | | —*«| 200 | ns xor XMIT Data TRI-STATE® Po co Ps ‘sac RovcLocktoncvsyncDely | | TT thos CY Data Set-Up Time Po Ps tnss RCV SYNC Set-Up Time ee ee ee ee tao# ACY Data Hold Time ee ee ee tysi XMIT SYNC Low Time 64 kHz Operation | so | | [| ns trst RCV SYNC Low Time 64 kHz Operation [a7 {[ | [wots Note 3: RCV SYNC must remain low for at least 17 cycies of MASTER CLOCK, each frame. Timing Waveforms 72 kHz or Greater Operation Yess om KS SASLVSAN SNA AA SO e ‘es he Phe Mor vt one ‘te “top Sor’ nev ‘ee Lock ' ° te Ne RY tees) we ‘eo ts ower XX 2 Xs K+ Xs X 6) Cos XN runveess-3 64 kHz Operation Mt _ LPL ELEL PELL Leer a rn | rs one = oan KX 2 Xs N+ Xs Ke) Oat tt TL LPLELELELELPLELPLELR or A bs ‘sNC ‘es. rot XX XXXII outst Tune06-4 1-208