TP5088 NSC | Alldatasheet
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Technical content
Features
Y Direct microprocessor interface Y Binary data inputs with latches Y Generates 16 standard tone pairs Y On-chip 3.579545 MHz crystal-controlled oscillator Y Better than 0.64% frequency accuracy Y High group pre-emphasis Y Low harmonic distortion Y MUTE output interfaces to speech network Y Low power idle mode Y 3.5V–8V operation Block Diagram TL/H/5004–1 *Crystal Specification: Parallel Resonant 3.579545 MHz, R S s 150X,L e 100 mH, C 0 e 5 pF, C 1 e 0.02 pF. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V DDbVSS) 12V MUTE Voltage 12V Maximum Voltage at Any Other Pin V DD a 0.3V to V SS b 0.3V Operating Temperature, T A b30§Ct o a70§C Storage Temperature b55§Ct o a150§C Maximum Power Dissipation 500 mW
Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V DD e 3.5V to 8V, T A e 0§Ct o a70§Cb y correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/ or product design and characterization. Parameter Conditions Min Typ Max Units Minimum Supply Voltage, V DD (min) Generating Tones 3.5 V Minimum Supply Voltage for Data Input, 2VTONE ENABLE and MUTE Logic Functions Operating Current Idle R L e %, D0–D3 Open 55 350 mA Generating Tones V DD e 3.5V, Mute Open 1.5 2.5 mA Input Pull-Up Resistance D0–D3 100 k X TONE ENABLE 50 k X Input Low Level TONE ENABLE, D0–D3 0.2 V DD V Input High Level TONE ENABLE, D0–D3 0.8 V DD V MUTE OUT Sink Current V DD e 3.5V 0.4 mA(TONE ENABLE LOW) V o e 0.5V MUTE OUT Leakage Current V DD e 3.5V 1 mA(TONE ENABLE HIGH) V o e VDD Output Amplitudes R L e 240 X 130 170 220 mVrmsLow Group V DD e 3.5V 180 230 310 mVrmsHigh Group T A e 25§C Mean Output DC Offset V DD e 3.5V 1.2 V VDD e 8V 3.6 V High Group Pre-Emphasis 2.2 2.7 3.2 dB Dual Tone/Total Harmonic Distortion Ratio 1 MHz Bandwidth, V DD e 5V b20 dBRL e 240X Start-Up Time (to 90% Amplitude), t OSC 4m s Data Set-Up Time, t S (Figure 2 )V DD e 5V 100 ns Data Hold Time, t H VDD e 5V 280 ns Data Duration t W VDD e 5V 600 ns Note 1: RL is the external load resistor connected from TONE OUT to V SS.
TL/H/5004–2 Top View Order Number TP5088WM or TP5088N See NS Package M14B or N14A Functional Description With the TONE ENABLE pin pulled low, the device is in a low power idle mode, with the oscillator inhibited and the output transistor turned off. Data on inputs D0–D3 is ig- nored until a rising transition on TONE ENABLE. Data meet- ing the timing specifications is latched in, the oscillator and output stage are enabled, and tone generation begins. The decoded data sets the high group and low group program- mable counters to the appropriate divide ratios. These counters sequence two ratioed-capacitor D/A converters through a series of 28 equal duration steps per sine wave cycle. On-chip regulators ensure good stability of tone am- plitudes with variations in supply voltage and temperature. The two tones are summed by a mixer amplifier, with pre- emphasis applied to the high group tone. The output is an NPN emitter-follower requiring the addition of an external load resistor to V SS. Table I shows the accuracies of the tone output frequencies and Table II is the Functional Truth Table. TABLE I. Output Frequency Accuracy Tone Standard Tone Output % Deviation Group DTMF (Hz) Frequency from Standard Low 697 694.8 b0.32 Group 770 770.1 a0.02 fL 852 852.4 a0.03 941 940.0 b0.11 High 1209 1206.0 b0.24 Group 1336 1331.7 b0.32 fH 1477 1486.5 a0.64 1633 1639.0 a0.37 Pin Descriptions VDD (Pin 1): This is the positive supply to the device, refer- enced to V SS. The collector of the TONE OUT transistor is also connected to this pin. VSS (Pin 5): This is the negative voltage supply. All voltages are referenced to this pin. OSC IN, OSC OUT (Pins 6 and 7): All tone generation tim- ing is derived from the on-chip oscillator circuit. A low-cost
3.579545 MHz A-cut crystal (NTSC TV color-burst) is need-
ed between pins 6 and 7. Load capacitors and a feedback resistor are included on-chip for good start-up and stability. The oscillator is stopped when the TONE ENABLE input is pulled to logic low. TONE ENABLE Input (Pin 2): This input has an internal pull-up resistor. When TONE ENABLE is pulled to logic low, the oscillator is inhibited and the tone generators and output transistor are turned off. A low to high transition on TONE ENABLE latches in data from D0–D3. The oscillator starts, and tone generation continues until TONE ENABLE is pulled low again. MUTE (Pin 8): This output is an open-drain N-channel de- vice that sinks current to V SS when TONE ENABLE is low and no tones are being generated. The device turns off when TONE ENABLE is high. D0, D1, D2, D3 (Pins 9, 10, 11, 12): These are the inputs for binary-coded data, which is latched in on the rising edge of TONE ENABLE. Data must meet the timing specifications of Figure 2 . At all other times these inputs are ignored and may be multiplexed with other system functions. TONE OUT (Pin 14): This output is the open emitter of an NPN transistor, the collector of which is connected internal- ly to V DD. When an external load resistor is connected from TONE OUT to V SS, the output voltage on this pin is the sum of the high and low group tones superimposed on a DC offset. When not generating tones, this output transistor is turned off to minimize the device idle current. SINGLE TONE ENABLE (Pin 3): This input has an internal pull-up resistor. When pulled to V SS, the device is in single tone mode and only a single tone will be generated at pin 14 (for testing purposes). For normal operation, leave this pin open-circuit or pull to V DD. GROUP SELECT (Pin 4): This pin is used to select the high group or low group frequency when the device is in single tone mode. It has an internal pull-up resistor. Leaving this pin open-circuit or pulling it to V DD will generate the high group, while pulling to V SS will generate the low group fre- quency at the TONE OUT pin.
Physical Dimensions inches (millimeters) Order Number TP5088WM
TP5088 DTMF Generator for Binary Data Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line (N) Order Number TP5088N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
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