TP3421

TP3421 NSC | Alldatasheet

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National PRELIMINARY | 2 Ny Semiconductor ~ TP3421 ISDN S/T Interface Device with GCI (General Circuit Interface) General Description Features The TP3421 S Interface Device (SID™) is a complete ™ 2B + D 4-wire 192 kb/s transceiver monolithic transceiver for data transmission on twisted pair m Selectable TE or NT mode subscriber loops. It is built on National's advanced 1.5 mi- = Provides all CCITT 1.430 layer 1 functions cron ent fen Process, ane yoaures ony a sng at ‘SV m Exceeds 1.430 range: 1.5 km point-to-point ‘supply. inctions specified in recommendation adaptiv iver for hi en i i 1.430 and ANSI T1.605-1988 for ISDN Basic Access at the a ynive hapa nies Ns ‘S' and ‘T’ interfaces are provided, and the device can be | Auer! ronizer ang crash wrest configured to operate either in a TE (Terminal Equipment), ™ Clock resynchronizer and elastic buffers for NT- in an NT-1 or NT-2 (Network Termination) or as a PABX —™ Slave-slave mode for NT-2 trunks line-card or trunk-card device. @ S and Q channels with automatic 3x checking As specified in 1.430, full-duplex transmission at 192 kb/s is GCI (General Circuit Interface) compatible provided on separate transmit and receive twisted wire pairs | ™ TP3054/7 Codec/filter Combo compatibility using inverted Alternate Mark Inversion (AMI) line coding. 2. ™ Single + 5V supply ‘B’ channels, each of 64 kb/s, and 1 ‘D’ channel at 16 kb/s —m 20-pin package are available for users’ data. In addition, the TP3421 pro- vides the 800 b/s “S1” & “Q"multiframe channels for Layer Applications 1 maintenance. m Same Device for NT, TE and PBX Line Card All|.430 wiring configurations are supported by the TP3421 wm Point-to-Point Range Extended to 1.5 km SID, including the “passive bus” for up to 8 TE's distributed iw point-to-Multipoint for all | within 200 meters of low capacitance cable, and pointto- roi we Multipoint hes mes Configurations point and point-to-star connections up to at least 1500 me- ‘quip ters (24AWG). Adaptive receive signal processing ensures low bit error rates on any of the standard types of cable ‘commonly found in premise wiring installations when tested with the noise sources specified in 1.430. SA a Block Diagram XTALZ MCLK/XTAL Yoo op! th en Ea

5 TRANSMIT

FSq ano Lf AND a . pexo/soux TwING | [>] au cover Ws “OST = Y Tt bru. our Pri Al CONTROLLER + ali = = cs i] SIGNAL J INTERFACE im tI Wy f—n DETECT ane ej RECEIVE * ft FITER u $0/8CL/BUS CONTROL AND LS rst <j EQUALIZER uw MO GND TL/H/10565-1 2-69

2 Connection Diagrams

r P3421 SID Name Description ay, By TTL/CMOS input for ‘B' and ‘D’ channel ite by r) ao data to be transmitted to the line; must be wee ate synchronous with BCLK. fs, 5 1eF (80 By n-channel output for ‘B’ and ‘D’ channel Yeo I+ 17 exo data received from the line which is syn- WCLK/XTAL 5 16 wo chronous with BCLK. When not shifting xm 46 ts rst data, this pin is high-impedance; a pull-up 8,47 14 so/ecteus resistor to Vg is required. oe, 48 isp s7/un DEN, In TEM and TES modes, this pin is a peux 49 12+ Pexo/scux CMOS output which is normally low and aio iifests, pulses high to indicate the active bit-times for ‘D’ channel Transmit data at the By in- TL/H/10565-2 put. It is intended to be gated with BCLK to Top View control the shifting of D-channel data from Order Number TP3421J or TP3421N a Layer 2 device to the TP3421 transmit See NS Package Number J20A or N20A buffer. in NT modes, this pulse occurs in every 8 KHz frame and indicates the loca- Pin Descriptions tion of D channel data input on the By pin. Note: For definitions of the modes TEM, TES and NT, see the Initialization RST The Reset pin, which must be pulled low at section. power-on Reset and for normai operation. A high-going pulse on this pin will reset the Name Description device in a configuration determined by GND Negative power supply pin, normally OV the Configuration pins. (ground). All analog and digital signals are PCKO/SCLK — In TEM and NT modes this is PCKO, which referenced to this pin. is a 32 KHz clock output synchronized to Vec Positive power supply input, which must be the GCI clocks; it is provided for synchroni- +5V +5% relative to GND. zation of a switching regulator in line-pow- MCLK/XTAL The 15.36 MHz Master Clock input, which ered equipment. requires either a crystal* to be tied be- In TES mode this is the SCLK output, tween this pin and XTAL2, or a CMOS log- which is a 1.536 MHz clock locked to the ic level clock input from a stable source. received line signal and intended to be When using a crystal, a total of 33 pF load used as the BCLK source. When used on capacitance to GND must also be con- a multi-channel line card, this output may nected. be commoned with the SCLK outputs of XTAL2 The output of the crystal oscillator, which other transceivers. A detector circuit en- should be connected to one end of the sures that this pin will stay high-impedance crystal, and 33 pF of load capacitance to to prevent conflict if any other device is GND. driving the SCLK. BCLK The Bit Clock pin, which determines the Ts5 The Line Signal Detect output, an n-chan- data shift rate for ‘B’ and ‘D’ channel data nel open-drain output which is normally at the GCI. When NT mode or TES mode high-impedance, but pulls low when the is selected, BCLK is a TTL/CMOS input device is powered down and a received which may be any multiple of 8 kHz from line signal is detected. It is intended to be 256 kHz to 4,096 MHz. It need not be syn- used to “wake-up” a microprocessor from chronous with MCLK. a low-power idle mode. This output is high When TEM mode is selected, this pin is a impedance when the device is powered CMOS output at 1.536 MHz This clock is up. phase-locked to the received line signal Lot, Lo Transmit AMI signal differential outputs to and is synchronous with the data on By the line transformer. When used with a 2:1 and B,. step-down transformer, the line signal con- FS In NT modes and TES mode, this pin is the forms to the output pulse masks in |.430. GCI Frame Sync pulse TTL/CMOS input, ut. Li- Receive AMI signal differential inputs from requiring a positive edge to indicate the the line transformer. The Li— pin is also start of the active channel time for transmit the internal voltage reference pin, and ‘B’ and ‘D’ channel data into By. In TEM must be decoupled to GND with a 10 pF mode only, this pin is a digital output pulse capacitor in paralle! with a 0.1 4F ceramic which defines the B1 channel at both By capacitor. | and Br. “Crystal specification: 15.36 MHz parallel resonant; Rg < 1502, OL = 20 pF and Co < 7 pF. **The 33 pF includes any board capacitance. 2-70

Pin Descriptions (Continued) Functional Description g cy CONFIGURATION PINS INITIALIZATION _ MO GCI Mode Selection input pin. To select The TP3421 SID device can be operated at either end of an GCI channel 0 connect MO=0; pin M1 S Interface loop. At the upstream end the mode is called must be used to select TEM or NT1 Mode. “NT” mode, in which the device is the source of INFO2 and To select GCI multiplexed mode connect INFO4 frames; choose this mode for PBX (NT2) line cards MO=1; the GCI channel is then selected and NT1 equipment. A selection of adaptive or fixed receiv- by pins SO, S1 and S2, and the Control er timing (NTA or NTF mode) must also be made, see De- Register must be used to select TE or NT vice Modes section. mode. At the downstream end of the loop the mode is called “TE” S0/BCL/BUS The function of this pin is dependent on mode, in which the device is the source of INFO1 and the device mode selected via the MO pin INFOS frames; choose this mode for terminal equipment and the Control Register, as follows: and NT2 trunk side interfaces. Furthermore the digital inter- $0: in NT modes, and if MO=1, this is face may be configured to be either the master of the timing the SO input pin for the Isb of the 3 on the BCLK and FS pins (TE Master mode) or a slave to pin GCI channel selection. timing from another device (TE Slave mode). Configuring . i = i the TP3421 SID into the required operating modes is ac- Bus: " NT modes, and if Mo 0, this pin complished by polarization of pins, as shown in Table |; for is the the BUS select input pin for on of pin use in NT—-1 lications: when TE Slave mode and applications in an NT2/LT the appropri- BUBSO fied timing recovery Is ate command must also be written via the GCI Monitor selected for use on passive bus channel prior to the Power-Up command. ; ; wiring, and when BUS= 1 adaptive TE Master mode is selected solely by appropriate strapping timing recovery is selected for use of pins MO and M1. The device is then powered up by pull- on point-to-point and extended ing the B, data input pin low momentarily, thereby starting passive bus wiring. the GCI clocks needed for transfer of additional control BCL: In TEM mode only, this pin is an data, _. output BCLK at 768 kHz. It is used When the NT1 configuration is selected, the device is pow- as the BCLK, input to the ered up directly by receiving GCI clocks on BCLK and FSq TP3054/7 or TP3075/6 Codec/fil- inputs (normally by the U transceiver). ter Combos, which clock data at a When NT2 or TE Slave (TES) mode is selected, the device rate of 1 bit per BCLK cycle. must first be correctly configured by writing the appropriate S1/FSp $1: if MO=1 only (GCI multiplexed command via the GCI Monitor Channel, and then writing the mode), this is an input pin for the PUP command on the C/I channel. GCI channel selection. FSp: if M0=0 and M1=0 (TEM mode), this is a Frame Sync output pulse which indicates the active slot for the B2 channel on the GCI. $2/M1 $2: if MO=1 only, (GCI multiplexed mode), this is an input pin for the msb of the GCI channel selection. M1: if MO=0 this pin is the selection for TE Master or NT1 mode as follows: M1=0 selects TEM mode; M1=1 selects NT1 mode (see also BUS input). TABLE |. Mode Selection and Power-Up Control Device Mode MO i=0 i=1 i=o i= $2/M1 i=M1=0 i=s2 i=Mi=1 i= $2 2 | S1/FSp 0 = FS i=S1 Not Used i=S1 $0/BCL/BUS 0 = BCL = 768 kHz i=so i= BUS i= so =0 for NTF =1 for NTA Mode Command _ TES - NTA/NTF Power-Up Pull By Low PUP Command Send BCLK PUP Command Note: { moans input, o means output. 2-71

Functional Description (continued) g PI se Ey 244 FFF 5 pe 2 | i i

2's up to 8 GCI channels may be carried in 1 frame of a GCI GC is also in a slave mode i.e., FS, and BCLK are inputs. GCI PHYSICAL INTERFACE ; ps pk-pk at frequencies below 10 Hz. FS, insures re-initialization of the time-slot counter at the the wire-OR bus. clocked in both directions at half the BCLK input frequency. Figure 3 shows the frame structure at the GC! interface. A device may be either the Master or Slave of the GCI tim- as follows: . sourced externally, typically from a system backplane. E bit, which indicates the end of the byte. Note 1: In TE Master Mode only. FIGURE 3. GC! Interface Frame Structure (Showing 8-Channel Multiplex with BCLK = 4.096 MHz)

4.096 MHz. GCI channel selection is by means of strapping each Monitor channel byte in either direction, see Figure 4. Receive Register, as listed in Table IV. Each access to or transfer until it is successfully acknowledged. FIGURE 4. GCi Monitor Channet Protocol

3 Functional Description (continuea)

e TABLE III. Monitor Channel Control Functions Function Bit Number [z7[e[s[s+[s[e2 }ilfo Device Modes “NT Mode, Adaptive Sampling [era To fotofotofifolfo NT Mode, Fixed Sampling [er fofofofofofsfol|: TE Slave Mode [ms fofofofofof:filo TE Master Mode prow fofofofofofsfi] Monitor Mode Activation [wma [o[of[ofi]1]1] 1 | 1 B1 Channel Enable/Disabie

81 Channel Enabled Pee [fofofofifoftifolfs

“B1 Channel Disabled Leo [Jofofofifo}sfolf: B2 Channel Enable/Disable

2 Channel Enabled [ee tofoto{s{ofrfifo

“B2 Channel Disabled [seo fofofofsfo}tsfsi]s B Channel Exchange “BChannois Mappedtven, Siwateewee | won [olelelel[sfl1le. B Channels Exchanged, B1 to B2, B2 to B1 [ex [ofofofo|] 1 fi] o | 1 End of Message Indication “EOM indication Enabled Pec [Tofofo{+f[ofofol]o OM indication Disabled feo [ofofofifofojol|s: Multiframe Circuit Muttirame Greult Enabled [me Tovtofofifofof:ifo *Multiframe Circuit Disabled [mc [olfofof{i]jo]|]ol|i. | 1 Multiframe Receive Message 3x Checking “Enable 2X Checking [enx | | [ fT J ft ft Disable x Checking [osx | [ [ [ [ | J | Multiframe Transmit Register Write to Multiframe Transmit Register [mer [| o]o]+]1]m {me {ms | mae Loopback Test Modes Loopback B1 towards Line interac Ce ee CC Loopback B2 towards Line Interface [ue [ofoflofi|{+]o]| o | 1 Loopback 28 + D towards GO! fuss fotofof+{+{fofifa Loopback B1 towards GCI [user fotofof+{[+{[ifofo Loopback B2 towards GCI [usse fo fofot+{ +a fos *Clear All Loopbacks Pea ftofolof:{[1]ofi]|: “Indicates intial state following power-on. TABLE IV. Monitor Channel Status Functions Bit Number Fenevon ed ee Q Multiframe Receive Register Requires Service | MFR | o | o | 1 | 1 | m1 | M2 | M3 | M4 2-76

. . uv Functional Description (continued ~ DEVICE MODES 8 NTA _NT Mode, Adaptive Sampling should be selected B1E) When either or both B channels are disabled, bi- when the device is in an NT on any wiring configu- BID) nary 1s are transmitted on the line in those B ration up to the maximum specified length for op- B2E) channel bit positions, regardless of data at the By eration. Multiple terminals, if required, must be input, and the B, output is high-impedance in grouped within approximately 100 meters of each B2D) those bit positions. other (depending on cable capacitance, see 1.430). The GC! is a slave to external BCLK and MULTIFRAME TRANSMIT REGISTER FS sources. MFT With the device in TE Mode, data entered in bit NTF NT Mode Fixed Sampling may be selected when MCE positions Mt, M2, M3 and M4 is transmitted the device is in an NT on a passive bus wiring cl towards the NT in multiframe bit positions Q1, Q2, configuration up to approximately 200 meters in MCD qa and Q4 respectively. With the device in NT length (depending on cable type). In this mode the Mode, data entered in the M bit positions is trans- receiver DPLL is disabled and sampling of the re- mitted towards the TE in multiframe bit positions ceived symbols is fixed, to enable multiple termi- $11, S12, $13 and $14 respectively. The Multi- nals (nominally up to 8) to be connected anywhere frame Channel must be enabled by an MCE com- along the passive bus. Again, the GCIs a slave to mand to use these channels; an MCD command external BCLK and FS sources. will disable them, (see Multiframe Maintenance TEM — TE Master Mode should be selected when the de- Channel section). vice is in a TE. The TP3421 is then the source of the BCLK and FS signals, and access to the MULTIFRAME MESSAGE CHECKING Transmit D channel, including the priority and con- - F tention resolution control, is enabled as described ENaX ENSx enables the checking of certain S and Q in the section on TE Mode D-Channel Access. Dis3x _ channel messages before generating the MFA in- ' dication. DIS3x disables this circuit, so that the re- TES TE Slave Mode, otherwise known as “‘Slave- ceived S or Q word generates MFR once per mul- slave” mode, should be selected when the device tiframe (see Multiframe Maintenance Section). is used on the T-interface side of an NT-2. The GCI is then driven by BCLK and FS sources in the NT-2. Data buffers and a clock re-synchronizer LOOPBACK TEST MODES ; enable this interface to function with jittering Three classes of loopback mode are available on the SID, sources for BCLK and FS. All D Channel access selected by writing the appropriate Control instruction. control circuitry is disabled, i.e. D Channel data at LBS This loopback at the system interface is a full the B, input is continuously transmitted to the line; loopback of the 2B + D channels from the B, input there is no monitoring of the D-echo channel from to the B, output. it may be set when the device is the network direction. Also, the SCLK function is either activated, in which case it is transparent (.e. enabled at the PCKO/SCLK pin. the composite signal is also transmitted to the MMA Intended for test equipment applications, this in- line), or when it is deactivated. struction allows the receive line interface (Lj+) to LBL1/2 These loopbacks turn each individual B channel be connected to the TE-to-NT direction twisted from the line receive input back to the line transmit pair and to activate on the received INFO 3 sig- output. They may be set separately or together. nals while being the master of the GCI. The re- LBB1/2 These loopbacks at the Digital System Interface ceived 2B+D can then be passively monitored loop the B1 (LBB1) or the B2 {LBB2) channel data (the line transmit output L,p+ would not be con- from the By input to the B, output. The By input nected). TE Master mode must be selected prior data is also sent to the line transmit output. to power-up by connecting MO=0 and M1=0. EXTERNAL SELF-ACTIVATING LOOPBACK B CHANNEL CONTROL A quick self-test of the device is possible by connecting BDIR) These commands provide for the exchange of together the line sides of the transmit and receive trans- BEX) data between the B1 and B2 channels as it pass- formers. NTA or NTF mode must be selected, and the de- es through the device (Note 1). vice can then be activated by the normal command se- Nate 1: When enabling a B channel in conjunction with the BEX Command, uence (Note 2). the cl ‘are referenced at the Digital System Interface, not the Note 2: This test mode is not possible by direct connection of Lo + and L+ line interface e.g. to connect the B1 slot on the DS! with the B2 slot pins due to incompatioie internal bias voltages. ‘on the line intertace, use the BEX and B1E commands. MONITOR CHANNEL STATUS INDICATORS 2 | MFR This message indicates when the Multiframe re- ceive data buffer requires servicing, after 1 or 3 consecutive identical Multiframe words have been detected, see Table IV. All Multiframing functions can be disabled via an MCD Command if desired. 277

=| Functional Description (continues) & GCI C/1 CHANNEL sages. A change in status is repeated in the transmit C/I The C/I (Command/Indicate) channel in GCI byte 4 is used channel in at least 2 consecutive GCI frames, while a solely to access the Activation Control and Status indicators change in received message is verified in 2 consecutive GCI in the TP3421. Table V shows the coding of the 4 bit mes- frames before taking the appropriate action. TABLE V. C/I Control Channel Coding Code | reMaater | Teste [nts rz cacacact | ima com. | tnt Com | ind. Com. | inom,

0000 DOR PUP/DR DR PUP/DR TIM DR TIM PUP/DR

0001 x PDN x PDN x x x PDN 0010 x x x x x x x x

0011 EOM (1) x x x x x x x

0100 El x El x El RSY El x

1000 AP ARS AP AR AP AR AP AR

1001 CON (1) AR10 x x x x x x

1010 x ARL x ARL x ARL x ARL, 1011 x x x x x x x x

1100 Ais x Al x Al UAR Al UAR

1101 At10 x x x x x x x

1110 AIL x AIL x AIL x AIL x

1111 Dt dl Ol Dl DI ol Dl Dl

(00) codes reserved (1) codes sent only two times when event occurs. C/I CHANNEL COMMANDS: PUP/DR When in the power-down state this is the power- AR Used in NT and TES applications, this is the Acti- up command, which powers up all the circuitry, vation Request which starts transmission of the starts the XTAL and resets the state machine to appropriate activation sequence. the deactivated state. In TEM mode, the GCI UAR Used in NT applications only, this command must clocks must be started by pulling the By pin low be used after the Al is generated on detection of prior to sending PUP/DR. The PUP/DR or DA INFO 3 from the terminal(s). UAR completes the command is also used In the power-up state as activation, causing transmission of INFO 4 frames the Deactivate Request, which forces transmis- with the 2B + D operational. sion of INFO 0. AR8 Used in TE Master mode only, this command PDN This is the power-down command, which forces functions as an Activate Request followed by an the device to first send the DI indicator in the C/| immediate access to the transmit D channel with channel on B, for 2 GCI frames, and then to pow- a packet of the high priority class (see the section er-down at the end of the assigned GCI channel. ‘on TE Mode D-Channel Access). It should only be used after the TP3421 has been put in a known state, e.g. in a TE after a Di status has been reported, since it does not force se- quencing through any of the deactivation states. 2-78

. . uv Functional Description (continued) g AR10 =‘ Used in TE Master mode only, this command AIL This is the Activation Indication Loopback, which in- 8 functions as an Activate Request followed by an dicates that the complete loopback requested via an immediate access to the transmit D channel with ARL command is in effect. packet of the low priority class (see the section AP This is the Activation Pending indication, which oc- on TE Mode D-Channel Access). curs in a TE when INFO 2 or INFO 4 frames are ARL The Activate Request for Loopback, which oper- detected. An AR command must be sent to allow ates a full loopback of the 2B + D channels from activation to be completed. the B, input to the B, output. It may either be set El This is the Error Indication, which occurs when loss when the device is activated, in which case it is of frame alignment is detected. Also, in a TE, if the transparent (the composite signal is also transmit- line is already activated and the received line signal ted to the line) or when it is deactivated, in which changes from INFO 4 to INFO 2 (during loop testing) case it is non-transparent. this indicator is generated. 1 When used as a command, DI allows the device DI _ This is the Deactivation Indication, which is generat- to automatically power-down if the S Interface is ‘ed in response to a DI command. After the indicator already deactivated. is acknowledged by the A bit, the device may be RSY Effective only in NT modes, and only after Activa- powered down, by the PDN command in a TE or by tion has been completed, this instruction forces stopping the GCI clocks in an NT1 or NT2. the NT to transmit INFO 2 frames instead of EOM This is the End of Message indicator, which occurs INFO 4, normally to allow testing at the U inter- when the closing flag of a D-channel packet has face. Provided INFO 3 is still being received from been transmitted by a TE on the S Interface, indicat- the TE(s), an Al Status message will be generated ing successful completion of a packet. The genera- and loop synchronization maintained, but 2B +D tion of this code can be disabled via the Monitor transmission is inhibited. To restore full loop acti- Channel using the EID command. vation, with the NT sending INFO 4, a UAR com CON Thisis the Contention indicator, which occurs when, mand is required In the normal way. during transmission of a packet in the D channel, a C/\\ CHANNEL STATUS INDICATORS received E bit does not match the last transmitted D TIM Timing Request indicator, which occurs when a de- bit, indicating a lost collision. A new ARB or AR10 activated NT has detected a “wake-up” signal, command is necessary to restart the D channel ac- passed a Line Signal Detect upstream and received cess procedure. he clocks. aM acts. as confirmation that the device ACTIVATION/DEACTIVATION: TP3421 IN NT MODE as powered up. This indicator also occurs in an Activation (i.e. transmission and I mchronization) may activated NT in response to a DA command. be intiated from either end of the loop. To inate Activation DR Deactivate Request indicator which is generated from the NT, the TP3421 must be powered up (see Initializa- when any of the following events occurs: tion Section), followed (Note 3) by an AR command in the — just after power-up when the S line signal has not C/I Channel. Network timing, i.e., an 8 kHz input to FS,, yet been identified; must be present at this time. The device then begins to — detection of INFO 0 on an activated (or partially send data framed as INFO 2 type, in which bits in the B, D aetvaten) me: Gotectd by tho Te: which ropos wih deta remed aa NFO a te tac y the which replies wi as - _ @ PUP command while activation is pend- 3 type, synchronized to received frames. A flywheel circuit in Pane oo the TP3421 NT searches for 3 consecutive correctly format- Al This is the Activation Indication generated when ac- ted receive frames to acquire frame synchronization. if Mul- tivation is completed in response to an AR com- {iframing is enabled (MIE), 60 correct frames (3 multiframes) mand. are required to achieve full loop synchronization. When it is Al8 This is the Activation Indication, generated in TE correctly in sync with received frames, the NT device sends Master mode only, when activation is completed in Alin the C/I channel. A UAR command is required to cause response to an AR8 command; the D channel ac- the NT to send INFO 4 frames, in which the B and D chan- cess procedure is set in the high priority class. nels are enabled for transmission (this command may be AI10 This is the Activation Indication, generated in TE delayed until the upstream link indicates that it is also fully Master mode only, generated when activation is activated). Completed in response to an AR10 command; the D Note 3: A dolay of > 2 mais recommended to ensure that all intemal circuits channel access procedure is set in the low priority have settied, class. 2-79

| Functional Description (continue | when Activations initiated by a TE, the TP3421 in NT mode nal, and acquire bit and frame synchronization. Once INFO will detect the incoming INFO 1 signal and, if it is powered- 2 has been identified, the TP3421 will send AP in the C/I down will pull the LSD pin low, which can be used to “wake- channel. The microprocessor must respond by sending AR up” a microprocessor. The device must then be powered up in order for Activation to proceed. INFO 3 frames are then by the specified initialization procedure. Upon identifying the transmitted. Finally, when the NT replies with INFO 4 INFO 1 signal, the device sends AP in the C/I channel. An frames, Al is sent in the C/I channel. ‘AR command is required to start sending INFO 2 frames, ‘As in NT mode, once Activated, loss of frame alignment is which allows the Activation sequence to proceed as de- assumed by the TP3421 when a time equivalent to three scribed above. frames has passed without it detecting any of the valid pairs Once Activated, loss of frame alignment is assumed by the of line code violations which obey the framing rule. If the TE P3421 when a time which is equivalent to three frames has does detect alignment loss it will cease transmitting immedi- passed without it detecting any of the valid pairs of line code ately. At this point El is sent in the C/| channel, and the violations which obey the framing rule. If the NT does detect receiver searches to re-acquire loop synchronization if alignment loss it will start to transmit INFO 2. At this point El INFO 2 or INFO 4 frames are still being received. If synchro- is sent in the C/I channel and the receiver searches to iden- nization is re-established, Al is sent. If, however, the receiv- tify the incoming signal and attempt to re-acquire loop syn- er subsequently identifies that the incoming line signal has chronization. If it successfully re-establishes synchroniza- ceased, i.e. INFO 0 is being received, the loop is de-activat- tion with the incoming signal (INFO 3 frames), Al is sent in ed, and DI is sent to indicate De-activation. the C/I channel and re-activation can be completed by 1.430 does not provide for Deactivation to be initiated by a sending a UAR command. If, however, the receiver subse- TE. However, a power-down state may be forced if required, quently identifies that the incoming line signal has ceased, normally after Deactivation has been established by the net- i.e. INFO 0 is being received, Status Indicator TIM is sent in work (see POWER-DOWN section). ihe Gi channel with the transmitted frames changed to If required, an extemal Timer 3 should be started when an : Activation Request is sent to the TP3421. The subsequent 1.430 recommends 2 timers should be available in an NT. An Al indication should be used to stop the timer. If the timer Activation Request to the TP3421 should be associated expires before an Al is generated, PUP/DR must be sent to with the start of an external Timer 1, if required. Timer 1 the device to force the transmission of NFO 0. should be stopped when the Al status message is generat- ed following successful Activation. If Timer 1 expires before TE MODE D-CHANNEL ACCESS Al is generated, however, the DR command should be writ- In TE Master and Slave modes the TP3421 SID arbitrates ten to the device to force de-activation. Timer 2,. which is access for Layer 2 Transmit frames to the D-channel bit specified to prevent unintentional reactivation, is not re- positions in accordance with the 1.430 Priority Mechanism quired since the TP3421 can uniquely recognise INFO 1 (1.430 Section 6.1). This mechanism is to resolve contention frames. for the D channel towards the network when 2 or more TEs . are connected to a Passive Bus. The shifting of D-channel ACTIVATION/DEACTIVATION: 7P3421 INTE MODE transmit data from the Layer 2 device into the SID butfer is To activate the loop with the TP3421 at the TE end the controlled by gating the DEN, output with BCLK. When no device must first be powered-up (see Initialization Section), Layer 2 frame is pending, ‘'1"'s are always transmitted by followed by a Control instruction type AR (Note 3). This is the SID in D-bit positions at the S Interface. DEN, output the Activation Request to begin transmission of INFO 1 pulses are inhibited and no D-channel data is shifted into frames after verifying that INFO 0 is being received from the the By input, An external Layer 2 device requiring to start NT. INFO 1 is a continuous pattern of 0+, 0—, and 6 ‘1's transmission of a packet should first prime its Transmit butf- repeated. At this point the TE is running from its local oscil- er such that the opening flag is ready to be shifted across lator and is not receiving any sync information from the NT. the digital interface. Then a C/I command, either AR8 for a When the NT recognises this “wake-up” signal, it begins to Priority Class 1 (signaling) packet or AR10 for a Priority fransmit no zl peaahhiaetan tae ebigy Ihe on Class 2 packet, will initiate the D-channel access sequence. ing activation of the “U” interface, if applicable). This en- ‘ ables the phase-locked loop in the TE’s receiver to correctly In response to the command, the DEN, output is enabled to enna 10 ot pre-fetch the opening flag from the Layer 2 device into the identify bit timing from the NT and to synchronize its own D-channel buffer. Meanwhile, the Priority Counter checks transmission to that of the NT. On identifying INFO 2 for 3 that no other TE connected to the S Interface {in a point-to- consecutive frames, the TE changes its transmit data to no omer nected to" artace (in a po! INFO 3 and awaits the return of INFO 4 from the NT. Identi- multipoint wiring configuration) is transmitting in the D-chan- fication of INFO 4 completes the Activation sequence, nel. This is assured by counting consecutive “1"'s in the E- which the device indicates by sending Al in the C/I channel. bit position of frames received from the NT. At feast 8 con 7 secutive “1"s must be detected before transmission of the | When Activation is initiated by the NT, if the TP3421 in TE pending D-channel frame begins, in accordance with Table mode is powered down, it will pull the LSD pin low on receiv- VL ing a line signal, which can be used to “wake-up” a micro- processor. The specified initialization procedure is required to enable the device to power-up, identify the received sig- 2-80

. uv Functional Description (continuea) Py TABLE VI. D-Channel Access Criteria remented to the lower priority level within each priority | % class, in accordance with the 1.430 algorithm. Priority is sub- Number of Consecutive sequently restored to the higher level when the specified “1s In the E-Channel number of consecutive 1's (9 or 11) is detected in the D- 7 Abort. Possible re-try by echo-bit position. the transmitting TE. MULTIFRAME MAINTENANCE CHANNELS Signalling packet (Priority (S1 AND Q WORDS) Class 1) may begin (Note 1). Each direction of transmission across the S Interface in- — _ cludes a low-speed (800 b/s) channel for loop mainte- Signalli ket may begin ; 8 | umonditanaiiy nance, accessed via the control interface of the TP3421. A multiframe structure, consisting of 20 frames on the S Inter- Any packet type may face, is used to synchronize these channels and convey begin (Priority Class 2) (Note 2). messages coded into 4-bit words, see Table VII. One word Any packet type may is transmitted downstream (NT-to-TE) in the S1 channel, begin unconditionally and one word is transmitted upstream (TE-to-NT) in the Q channel every multiframe. stco ot SS conseeatie "I's nes Deen deen ee penal 8 When the device is in NT mode, the MIE command enables sequence of > 9 consecutive "“1"s has jetected in the E-chanr , Note 2: Only if, since the SID last transmitted a complete packet of either both the transmission of the Multiframe identification algo- class, a sequence of > 11 consecutive "1"s has been detected in the E- rithm (reversal of the FA/N bits every Sth frame and M bit channel. set = 1 every 20th frame) and the generation of the MFR If another TE is active in the D-channel, DEN, pulses are Hien ie won pannel, ™me Blgoritn | is present inhibited once the opening flag is in the Transmit butter, to luring ames. In is Com- prevent further fetching of transmit data from the Layer 2 mand only enables the MFR indication, since the device will device until D-channel access is achieved. As soon as the always search for and synchronize to the multiframing iden- required number of consecutive E-channel “1s has been tification bits if the NT is sending them. In all modes there is counted, the leading 0 of the opening flag is transmitted in an option to enable < disable an automatic checking circuit the next D-bit position towards the NT. DEN, pulses are to validate received S or Q channel words. If this circuit is also re-enabled in order to shift D-channel bits from the ‘enabled by the EN3X instruction, at the end of each multi- Layer 2 device into the SID transmit butter. frame the received 4-bit word is decoded to determine if it , “ein j hould generate an MFR indication immediately, or be During transmission in the D-channel the TP3421 SID con- be ‘ ’ é tinues to compare each E-bit received from the NT with the Sioned ‘ats i boteone marames nave contained the D-channel bit previously transmitted before Proceeding to lists the codes which are 3-times checked Note, however, Son tor the novos Ooi. vesoumed To howe bch won by that no other action is taken by the TP3421 in response to another TE. Transmission of the current packet therefore orien cones (e.g Noapbacks are nod he ee ae ee ceases and “1"s are transmitted in all following D-bit posi- ‘ a " . , tions. Status Indication type CON is sent in the C/I channel, acon. orn erevides fhe freedom eo imblement | mainte” must begin as before, by priming its Transmit buffer with the it the 3 times checking circut is disabled by ine OSS in packet header. It must also reset the C/I channel by send- struction, each received S or Q word generates an ing the DI code to the TP3421 in at least 2 consecutive GCI indication once per muttiframe. frames, prior to sending a new AR8 or AR10 command. The MCD command disables the transmission of the Multi- DEN, pulses stop immediately after receiving the closing Tarne iGeneiication algorithm in v mode and Gisables lhe i the layer 2 device. + flag on the Bx input from the layer 2 device. and MCD commands can only be written to the device when Successful completion of a transmit packet is detected by it is deactivated (either powered-up or powered-down). The the TP3421 when the closing flag is transmitted in the D Multiframe Transmit Register should also be loaded with the channel. ‘1’s are then transmitted in the following D bit posi- appropriate “Idle” messages, by means of an MFT com. tions. Status Indication type EOM is sent, to indicate the mand, prior to activation, End of Message. Also, the Priority Access counters are dec- , : 2-81

x NX &| Functional Description (continued) a - TABLE VII. Codes for Q-Channel and S1-Channel Messages with 3x Checking Enabled [Tore TEtONT Received at TE Number of Repetitions Received at NT Number of Repetitions $11 $12 S13 S14 before MFR Message |g; g2 @3 @4 before MFR Message Loss-of-Power es ee 1 0 0 0 0 Indication STP Pass o o 1 0 --- = STF Fail o o o 1 --- - ST Request —- - |= = C) 1 (Note 1) o 9° STI Indication o 4 41 1 - - - = DTSE-IN 1 0 0 0 1 DTSE-OUT o 4 0 0 1 DTSE-IN&OUT 1 1 0 0 1 LB1 Request —- - - = o 1 4 4 LB1 Indication 1 1 0 14 --- - LB2 Request - - - - 1 0 1 4 LB2 Indication 1 0 14 1 --- = LB1/2 Request - - = = 0 oO 1 (Note 2) ' LB1/2Indication | 1 0 O 1 - - - - Loss-of-Received- Signal Indication All Other Codes [a Jatiottercouss Tt Note 1: The code 0001" will be received by an NT1 when ST Request and any other code (except LP) is sent simultaneously by two or more TEs on a Passive Bus. Note 2: The code “0011” will be received by an NT1 when the LB1 and LBZ requests are transmitted by two. different TEs (NT2s) on a Passive Bus. Applications Information While the pins of the TP3421 SID are well protected against 3. keep the connections between the device and the trans- electrical misuse, it is recommended that the standard formers short. CMOS practice of applying GND to the device before any Figure 5 shows a typical application of the TP3421 in an other connections are made should always be followed. in ISDN Terminal. To provide a voice channel, the TP3054/7 applications where the printed circuit card may be plugged Combo | Codec/filter is shown. Although these Combos into a hot socket with power and clocks already present, an clock PCM data at a rate of 1 CLK cycle per bit, direct com- extra long ground pin on the connector should be used. patibility with the GCI is provided by connecting the BCL To minimize noise sources, all ground connections to each output of the TP3421 (in TEM mode) to the BCLK, input of device should meet at a common point as close as possible the Combo. Data is shifted between devices in the B1 chan- to the GND pin in order to prevent the interaction of ground nel at 768 kHz, with the 1.536 MHz GCI clock (BCLK) pro- return currents flowing through a common bus impedance. viding the MCLK for the Combo. If the network assigns the ‘A decoupling capacitor of 0.1 4F should be connected from B2 channel to a voice call, the BEX command is used to this common point to Voc. Taking care with the pcb layout exchange the B1 and B2 slots between the GCI and S/T in the following ways will help prevent noise injection into interfaces. the receiver front-end and maximize the transmission per- For more in-depth information on a variety of applications, formance: the TP3421 Users Manual is a comprehensive guide to the 1. keep the crystal oscillator components away from the re- hardware and software required to meet the 1.430 interface ceiver inputs and use a shielded ground plane around specification. Performance measurements, demonstrating these components. compliance with |.430 and ANSI transmission requirements, 2. keep the connections between the device and the com- are also included. ponents on the Lj+ inputs short; the Li— capacitors should be connected close to the device pins. 2-82

= . uv Typical Applications g hd rx} 7/|8 6 & r Pl er 2 Gp EER z 33 e +o ofsslo ¢ <7 te ty E u . 4 Ik

3 Bie 'p ra Fi

-ts _ 3 Fd = H 28 3 « ° = 65 ie fd : sh+> i$ 8 gee ek oe of Zz & 8 ad g § bi 85 z < re ee ae gas ee aze St] is |2 3 3 [ee ER) Eg OE a ry ets ¢8 pages iiea 38 gee: g2 Bez ant @ 262 gris = Bese HE 2 | ead: £53? ae BER g 6eE eo aes g538 2-83

=| Absolute Maximum Ratings - If Military/Aerospace specified devices are required, Storage Temperature Range —65°C to+ 150°C please contact the National Semiconductor Sales Current at Lo Pins +100 mA Office/Distributors for availability and specifications. Current at any Digital Output +£50mA VoctoGND Ww Lead Temperature (Soldering, 10 sec.) 300°C Voltage at Lj, Lo Pins Voc +1V to GND —1V ESD rating to be determined. Voltage at any Digital Input Voc +1V to GND —1V

Electrical Characteristics

Unless otherwise noted, limits printed in bold characters are electrical testing limits at Voc = 5.0V and Tq = 25°C. All other limits are design goals for Vcc = 5.0V +5% and Ta = 0 to 70°C. This data sheet is stil preliminary and parameter limits are not indicative of characterization data with respect to power supply or temperature variations. Please contact your National Semi- conductor Sales Office for the most current product information. symbol [mits Tats ee eee DIGITAL INTERFACES Vi. Input Low Voltage Al Digital Inputs [| [or fv Vin___| Input High Voltage All Digital Inputs [ee | | fv Vux | Input Low Voltage MCLK/XTAL Input [| os [ Vinx __ | Input High Voltage MCLK/XTAL Input [voo-os| | [| v Vou Output Low Voltage By, = 3.2mA y All Other Digital Outputs, I, = 1 mA Vou Output High Voltage B, lL = -3.2mA 24 v All Other Digital Outputs, || = —1 mA 24 v All Outputs, IL = — 100 pA Voc — 0.8 Vv \\ Any Digtal input, GND<Viv<Voc_ | -10 | | 10 | pa loz Output Current in High 8, [SB A Impedance State (TRFSTATE®) | GND < Vour < Voc ia LINE INTERFACES Ru Differential Input GND < 4+, li- <Voo , a 2 Resistance Clio _| Load Capacitance Between Lo+ and Lo— [| 200 | Vos | Differential Output Offset Driving Binary 18, 2209 between 420 | mv Voltage at Lo +, Lo— Lot and Lo~ POWER DISSIPATION lec0 All Outputs Open-ircuit [fo TT ms TRANSMISSION PERFORMANCE Transmit Pulse Amplitude R= 2200 Between Lo+ and Lo— 4155 175] vp (Note 2) TransmitPuiseUnbalance | 0+ Relaivetoo- | || ts | Input Pulse Amplitude Differential Betweent+ andu- | +175 | | | mvp Note 1: When the device is activated and driving a correctly terminated line, icc; increases by several mA. A worst-case data pattern, consisting of all binary 0's, increases Ioc} by approximately 8 mA. Note 2: The pulse amplitude at the L, + pins allows for approximately 1 dB tranformer insertion loss to meet the 0.75V pulse mask test when the line is terminated in 500. 2-84

a — 3 Timing Characteristics g symbol | ___Parameter_— | Conditions [min [typ [max [units | = FMCK Master Clock Frequency 15.36 MHz Master Clock Tolerance +100 ppm MCLK/XTAL Input Glock Jitter | External Clock Source [|| 50 _| nspkpk {MH, Clock Pulse Width Vin = Voc — 0.5V ns tML Hi & Low for MCLK Vi, = 0.5 tMA, Rise and Fall Time Used as a ns (MF of MCLK Logic input DIGITAL INTERFACE (Figure 6) tweH __| Period of BCLK High Measured from Vix to Vint [2 | | | os tWBL__| Period of BCLK Low Measured from Vi. to Vi [2 | | | os tRB Rise Time of BCLK Measured from Vit to Vin [|| ts | ons FB Fall Time of BCLK Measured from Vin to Vit [| | ws | ns tHBF | Hold Time, BCLK Low ns to FS, High or Low 1SFB Setup Time, FS High ns to BCLK Low tDBD | Delay Time, BCLK High Load = 150 pF Plus 2 LSTTL Loads ns to Data Valid tDBZ Delay Time, BCLK High 50 ns to Br, Dr Disabled tDFD Delay Time, FS Load = 150 pF Plus 2 LSTTL Loads, High to Data Valid Applies if FS Rises Later than ne BCLK Rising Edge in Non-Delayed Data Mode Only tSDB Setup Time, Data Ch Valid to BCLK Low $ tHDB | Hold Time, BCLK ts Low to Data Invalid 2-85

2 Timing Characteristics (continues)

FIGURE 6. GCI Timing