TP3420A

TP3420A NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 32

Technical content

Features

n 2B+D 4-wire 192 kb/s transceiver n Selectable TE or NT mode n Exceeds I.430 range: 1.5 km point-to-point n Adaptive receiver for high noise immunity n Adaptive and fixed timing options for NT-1 n Clock resynchronizer and elastic buffers for NT-2/LT n Slave-slave mode for NT-2 trunks n Extensive hardware support for SC1, SC2 and Q channel messaging n Bipolar violation detection and FECV messaging n Selectable system interface formats n MICROWIRE ™ and SCP compatible serial control interface n TP3054/7 Codec/Filter COMBO™ compatibility n Single +5V supply n 20-pin package DIP, PLCC

Applications

n Same Device for NT, TE and PBX Line Card n Point-to-Point Range Extended to 1.5 km n Point-to-Multipoint for all I.430 Configurations n Easy Interface to: LAPD Processor MC68302, HPC16400 Terminal Adapter MC68302, HPC16400 Codec/Filter COMBO TP3054/7 and TP3076 “U” Interface Device TP3410 Line Card Backplanes — No External PLL Needed n Line Monitor Mode for Test Equipment TRI-STATE® is a registered trademark of National Semiconductor Corporation. COMBO ™ , MICROWIRE ™ and SID™ are trademarks of National Semiconductor Corporation. PRELIMINARY July 1994 TP3420A ISDN S/T Interface Device © 1999 National Semiconductor Corporation DS009143 www.national.com

GND Negative power supply pin, normally 0V (ground). All analog and digital signals are referenced to this pin. V CC Positive power supply input, which must be +5V ±5% relative to GND. MCLK/XTAL The 15.36 MHz Master Clock input, which requires either a crystal (Note 1) to be tied between this pin and XTAL2, or a CMOS logic level clock input from a stable source. When using a crystal, a total of 33 pF load capacitance to GND must also be connected. (Note 2) XTAL2 The output of the crystal oscillator, which should be connected to one end of the crystal, and 33 pF of load capacitance to GND. (Note 2) If using an external master Clock via the MCLK pin, leave the XTAL2 pin unconnected. BCLK The Bit Clock pin, which determines the data shift rate for “B” and “D” channel data at the digital interface. When NT mode or TES mode is selected, BCLK is a TTL/CMOS input which may be any multiple of 8 kHz from 256 kHz to 4.096 MHz. It need not be synchronous with MCLK. When TEM mode is selected, this pin is a CMOS output at frequency selected by the Digital Interface Format. This clock is phase-locked to the received line signal and is synchronous with the data on B x and Br. DS009143-1 TP3420A SID DS009143-20 Order Number TP3420AV See NS Package Number V20A TP3420A SID DS009143-2 Top View Order Number TP3420AJ or TP3420AN See NS Package Number J20A or N20A www.national.com 2

Pin Descriptions(Continued) Name Description FS a In NT modes and TES mode, this pin is the Transmit Frame Sync pulse TTL/CMOS input, requiring a positive edge to indicate the start of the active channel time for transmit “B” and “D” channel data into B x. In TEM mode only, this pin is a digital output pulse whose positive indicates the start of the “B” channel data transfer at both B x and Br. FS b (Pin 11) In NT modes and TES mode, this pin is the Receive Frame Sync pulse TTL/CMOS input, requiring a positive edge to indicate the start of the active channel time of the device for receive “B” and “D” channel data out from B r.I nT E M mode only, when digital interface Format 1 is selected, this pin is an 8-bit wide pulse which indicates the active slot for the B2 channel on the digital interface. The DCKE command will alter the function of this pin. See Table 2for details. Bx TTL/CMOS input for “B” and “D” channel data to be transmitted to the line; must be synchronous with BCLK. B r CMOS output for “B” and “D” channel data received from the line, which is synchronous with BCLK. When not shifting data, this pin is TRI-STATE ® . DEN x/p2 (Pin 8) In TEM mode, this pin by default is a CMOS output which is normally low and pulses high to indicate the active bit-times for “D” channel Transmit data at the B x input. It is intended to be gated with BCLK to control the shifting of data from layer 2 device to the TP3420A transmit buffer. In NT modes, this pin by default is a pulse output (DEN x) which occurs in every 8 KHz frame and indicates the location of D channel data input on the B x pin. In TES mode, this pin by default is an output synchronized clock (SCLK) at the frequency selected by the Digital Interface Format. This clock is phase-locked to the received line signal, and is intended to be used as the BCLK source. This pin called P2 in Table 1can also be programmed to provide alternate functions. See Table 1for details. CI MICROWIRE control channel serial data TTL/CMOS input. Name Description CO Control channel serial data CMOS output for status information. When not enabled by CS, this output is TRI-STATE. CCLK TTL/CMOS clock input for the Control Channel. CS Chip Select input which enables the control channel data to be shifted in and out when pulled low. When high, this pin inhibits the Control interface. INT Interrupt output, a latched n-channel open-drain output signal which is normally high impedance, and goes low to indicate a change of status of the loop transmission system. LSD/P1 (Pin 18) In all modes, this pin by default is the Line Signal Detect output, an n-channel open-drain output which is normally high-impedance, but pulls low when the device is powered down and a received line signal is detected. It is intended to be used to “wake-up” a microprocessor from a low-power idle mode. This output is high impedance when the device is powered up. This pin P1 in Table 1can also be programmed to provide alternate functions. See Table 1for details. Lo+, Lo− Transmit AMI signal differential outputs to the line transformer. When used with a 2:1 step-down transformer, the line signal conforms to the output pulse masks in I.430. L i+, Li− Receive AMI signal differential inputs from the line transformer. The Li− pin is also the internal voltage reference pin, and must be decoupled to GND with a 10 µf capacitor in parallel with a 0.1 µF ceramic capacitor. Note 1:Crystal specification: 15.36 MHz parallel resonant; Rs ≤ 150Ω , C L = 20 pF and CO < 7p F . Note 2:The 33 pF includes any board capacitance. ALTERNATE PIN FUNCTIONS With a MICROWIRE command PINDEF (B'1110 0 x2 x1 x0) the pin signal functions of these pins can be changed to pro- vide alternate functions (see Table 1and the MICROWIRE command inTable 4). “*” indicates the default pin function af- ter a device mode selection. Power-up default device mode is NTA. www.national.com3

TABLE 1. Alternate Pin Function Assignment PINDEF command is coded as X’EX (i.e. 11100x2x1x0). Note 3:Default pin function after device mode selection. ance when the device is powered up. Table 2. Other configurations of PINDEF are not

8 DTCK

11 TxD

18 DRCK

• DCLK is a burst clock output intended to be used as a clock source for the transmitter of an HDLC device.
• TxD is an input being sampled on the rising edge of DCLK during the active D-channel timeslot.
• DRCK is a burst clock output which pulses 2 BCLK peri- ods every 8 kHz frame. This output is intended to be used as a clock source for the receiver of an HDLC device. The D-channel data at B r is transmitted on the falling edge of the DRCK. Functional Description DEVICE MODES The TP3420A can be programmed into one of four possible modes. For NT applications select NT Adaptive timing (NTA) for all wiring configurations except a Short Passive Bus, for which NT Fixed Timing (NTF) should be selected. In TE ap- plications, select TE Master mode (TEM) for the device to be the master (source) of clocks at the digital interface, or select TE Slave mode (TES) for the digital interface to accept clocks from the system. Selection of these modes is described in the section on Con- trol Register instructions. POWER-ON DEVICE CONDITIONS Following the initial application of power, the TP3420A SID enters the power-down (de-activated) state, in which all the internal circuits including the Master oscillator are inactive and in a low power state except for the Line-Signal Detect circuit; the line outputs L o+/Lo− are in a high impedance state and the Digital System Interface is inactive. All bits in the Control Register power-up as indicated in Table 1.I n both NT and TE modes, a Line-Signal Detect circuit monitors the line while the device is powered-down, to enable loop transmission to be initiated from either end. POWER-OFF DEVICE CONDITION When power to the TP3420A is turned off, the Line outputs L o+/Lo− go into high impedance state, hence if a TE on a passive bus lost power its transmit impedance still meets the specification without any external relay (see AN665 for exter- nal protection components). The receiver impedance also remains in specification. LINE CODING AND FRAME FORMAT For both directions of transmission, Alternate-Mark Inversion (AMI) coding with inverted binary is used, as illustrated in

Figure 1. This coding rule requires that a binary ONE is rep- ity to maintain a d.c.-balanced line signal. Figure 2. Each complete frame consists of 48 bits, with a line

FIGURE 2. Frame Format

SCLK = 512 kHz, Format 4, SCLK= 2.56 MHz. **FIGURE 3. Digital System Interface Formats in NT and TES* modes (DSI Slave)**

*Note:DENR signal is available on pin 18 after using the PINDEF command (seeTable 1). FIGURE 4. Digital System Interface Formats in TEM mode (DSI Master)

TABLE 4. Control Register Functions FIGURE 5. TP3240A Enhanced MICROWIRE Control Interface Timing

TABLE 4. Control Register Functions(Continued)

TABLE 4. Control Register Functions(Continued) Note 6:Indicates initial state following Power-on initialization. Note 8:DACCD is the power up default in TES mode and DACCE is the power up default in TEM mode. TABLE 5. Status Register Functions Note 9:Indicates initial state following Power-on Initialization.

Functional Description(Continued) a packet in the D channel, a received E bit does not match the last transmitted D bit, indicating a lost collision. AI This interrupt indicates that the interface has been successfully Activated in response to an Activation Request. EI Set when loss of frame alignment is detected. DI If set, indicates that the interface has been Deacti- vated. MFR1 This interrupt indicates when the Multiframe SC1/Q channel data buffer requires servicing, see Multiframe Maintenance section. The MID1 com- mand disables this interrupt. MFR2 This interrupt indicates when the Multiframe SC2 channel data buffer requires servicing, see Multi- frame Maintenance section. The MID2 command disables this interrupt. MFC This status interrupt provides a transmit multiframe clock. It can be selected to occur on every multi- frame boundary (5 ms) by the MFC1E command or on each 6 multiframe boundary (30 ms) by the MFC6E command. This interrupt can be used to synchronize the SC1/Q and SC2 multiframe trans- mit messages. RMFE A bipolar Violation or DC balance error causes this Receive Multiframe Error Interrupt in both NT and TE modes. At the NT end, upon receiving the RMFE interrupt, the local microcontroller must in- form the TEs with a FECV message (via the MFT1H register). The NT or the TE end can keep a count of RMFE interrupts to monitor the line block error rate at its receiver. SLIP This interrupt indicates if the clock phase shift in the jitter/wander buffers exceeded the phase shift limit and changed the internal data buffer delay to accommodate it. One interrupt is generated and is coded as X’09 for Tx buffer slip: X’0A for Rx buffer slip: and X’0B for both Tx and Rx buffer slip. NOC This NOC status is returned for every command when there is no change of status to be reported. It is read in the power-up default state and after the DISST command. No interrupt is generated. NOCST This status response occurs only after the ENST command. The NOCST status is returned in re- sponse to any subsequent command when there is no status change that needs to be reported with an interrupt. It contains the device activation state information, see the section on Activation State machine access. CONTROL REGISTER INSTRUCTIONS ACTIVATION/DEACTIVATION PUP This power-up command enables all analog circuitry, starts the XTAL and resets the state machines to the de-activated state, i.e. transmitting INFO 0 (no signal). It also inhibits the LSD output. PDN This power-down command immediately forces the device to a low power state, without sequencing through any of the de-activation states. It should therefore only be used after the TP3420A has been put in a known state, e.g. in a TE after a DI status in- dication has been reported. It also enables the LSD circuit. AR Activation Request initiates the specified Activation sequence. It is recommended that an AR be delayed at least 2 ms after the device is powered-up using the PUP command. DR Deactivation Request, which forces the device through the appropriate deactivation sequence speci- fied in I.430. Should be used at the NT end only. FI2 Effective only in NT modes, and only after Activation has been completed, this instruction forces the NT to transmit INFO 2 frames instead of INFO 4, normally to allow testing at the U interface. Provided INFO 3 is still being received from the TE(s), an AP Status Interrupt will be generated and loop synchronization main- tained, but 2B+D transmission is inhibited. To restore full loop activation, with the NT sending INFO 4, an AR command is required in the normal way. MMA Intended for test equipment applications, this instruc- tion allows the receive line interface (Li ±) to be con- nected to the TE-to-NT direction twisted pair and to activate on the received INFO 3 signals while being the master of the DSI. The received 2B+D can then be passively monitored (the line transmit output Lo would not be connected). TE Master mode must be selected first (TEM). DEVICE MODES NTA NT Mode, Adaptive Sampling should be selected when the device is in an NT on any wiring configura- tion up to the maximum specified length for operation. Multiple terminals, if required, must be grouped within approximately 100 meters of each other (depending on cable capacitance, see I.430). The Digital System Interface is a slave to external BCLK and FS sources. NTF NT Mode Fixed Sampling may be selected when the device is in an NT on a passive bus wiring configura- tion up to approximately 200 meters in length (de- pending on cable type). In this mode the receiver DPLL is disabled and sampling of the received sym- bols is fixed, to enable multiple terminals (nominally up to 8) to be connected anywhere along the passive bus. Again, the DSI is a slave to external BCLK and FS sources. TEM TE Mode DSI Master should be selected when the de- vice is in a TE. The TP3420A is then the source of the BCLK and FS signals, and access to the Transmit D channel, including the priority and contention resolu- tion control, is enabled as described in the section on TE Mode D-Channel Access. TES TE Mode DSI Slave, otherwise known as “Slave-slave” mode, should be selected when the de- vice is used on the T-interface side of an NT-2. The TP3420A System Interface is then driven by BCLK and FS sources in the NT-2. Data buffers and a clock re-synchronizer enable this interface to function with jittering sources for BCLK and FS. All D Channel ac- cess control circuitry is disabled, i.e. D Channel data at the Bx input is continuously transmitted to the line; there is no monitoring of the D-echo channel from the network direction, and DREQ instructions are ignored. Also, the SCLK function is enabled at the DEN x/SCLK pin. www.national.com13

positions Q1, Q2, Q3 and Q4 respectively. section on Multiframe Maintenance Channel. section on Multiframe Maintenance Channel. DISINT Disables RMFE and SLIP interrupts. to any MICROWIRE command thereafter. section on Activation State machine access. Table 1for the selection values. TABLE 6. TP3420A Activation State Table be sure of the state of the device. return the normal NOC (00000000) status back. greater flexibility in performing fault isolation.

1. B1 digital loopback (using LBB1 command) with any

FSa/FSb relationship in all TE or NT modes.

1. B2 digital loopback (LBB2) with any FSa/FSb relation-

Functional Description(Continued) 3. Contiguous B1+B2 (128 kbit/s) digital loopback (LBB1, LBB2) in TEM mode and in NT/TES modes if FSa is phase synchronous with FSb. 4. Contiguous B1+B2+D (144 kbit/s) digital loopback (LBD) in TEM mode and in NT/TES modes if FSa is phase syn- chronous with FSb. 5. B1 line loopback (using LBL1) with any FSa/FSb rela- tionship in all TE or NT modes. 6. B2 line loopback (using LBL2) with any FSa/FSb rela- tionship in all TE nor NT modes. 7. Contiguous B1+B2 (128 kbit/s pipe) line loopback (LBL1, LBL2) with equal delay, available in TEM mode, and in NT/TES modes if FSa is phase synchronous with FSb. Note that a line loopback for the D channel is not specified in the CCITT I.430 or the T1-605 specification, to ensure that D channel signaling is transparently passed end-to-end. ACTIVATION/DEACTIVATION: TP3420A IN NT MODE Activation (i.e. transmission and loop synchronization) may be initiated from either end of the loop. Activation initiated from the NT: to initiate Activation from the NT, the TP3420A must be powered up, using a PUP com- mand, followed (Note 12) by an AR instruction to the Control Register. Network timing, i.e., an 8 kHz input to FS a, must be present at this time. The device then begins to send data framed as INFO 2 type, in which bits in the B, D and D-echo channels are set to binary 0. These frames are detected by the TE, which replies with data framed as INFO 3 type, syn- chronized to received frames. A flywheel circuit in the TP3420A NT searches for 3 consecutive correctly formatted receive frames to acquire frame synchronization. If Multi- framing is enabled (MIE), 60 correct frames (3 multiframes) are required to achieve full loop synchronization. When it is correctly in sync with received frames, the NT interrupts the control processor with Status Indication type AP. A second AR command is required to cause the NT to send INFO 4 frames, in which the B and D channels are enabled for trans- mission; Status Indication type AI is then set, and the INT output is pulled low to indicate Activation complete. Note 12:A delay of≥2 msecs is recommended to ensure that all internal cir- cuits have settled. Activation initiated by a TE: when Activation is initiated by a TE, the TP3420A in NT mode will detect the incoming INFO 1 signal and, if it is powered-down will pull the LSD pin and INT low, either of which can be used to “wake-up” a micro- processor. A PUP command must then be written to power-up the TP3420. Upon identifying the INFO 1 signal, the device will set Status Indication type AP and pull INT low to indicate that Activation is pending. No INFO 2 frames will be transmitted until a Control instruction type AR is written to the device, which allows the Activation sequence to proceed as described above. Once Activated, loss of frame alignment is assumed by the TP3420A when a time which is equivalent to three frames has passed without it detecting any of the valid pairs of line code violations which obey the framing rule. If the NT does detect alignment loss it will start to transmit INFO 2. At this point the Error Indication (EI) primitive is set, the INT output is pulled low and the receiver searches to identify the incom- ing signal and attempt to re-acquire loop synchronization. If it successfully re-establishes synchronization with the in- coming signal (INFO 3 frames), a further interrupt is gener- ated with Status Indication type AI and re-activation can be completed by sending an AR command. If, however, the re- ceiver subsequently identifies that the incoming line signal has ceased, i.e. INFO 0 is being received, Status Indicator EI is set and INT pulled low, with the transmitted frames changed to INFO 2. Deactivation can then be completed by a DR command, following which Status Indication type DI is set and the INT output pulled low to indicate De-activation. If required, a PDN instruction may be written to the Control Register to power-down the device and enable the LSD out- put. I.430 recommends 2 timers should be available in an NT. An Activation Request to the TP3420A should be associated with the start of an external Timer 1, if required. Timer 1 should be stopped when the AI interrupt is generated follow- ing successful Activation. If Timer 1 expires before AI is gen- erated, however, Control Instruction type DR should be writ- ten to the device to force de-activation. Timer 2, which is specified to prevent unintentional reactivation, is not required since the TP3420A can uniquely recognise INFO 1 frames. ACTIVATION/DEACTIVATION: TP3420A IN TE MODE Activation initiated by the TE: to activate the loop with the TP3420A at the TE end the device must first be powered-up by a PUP command, followed (Note 3) by a Control Instruc- tion type AR, which is the Activation Request to begin trans- mission of INFO 1 frames after verifying that INFO 0 is being received from the NT. INFO 1 is a continuous pattern of 0+, 0−, and 6 ‘1’s repeated. At this point the TE is running from its local oscillator and is not receiving any sync information from the NT. When the NT recognises this “wake-up” signal, it begins to transmit INFO 2, synchronized to the network clock (following activation of the “U” interface, if applicable). This enables the phase-locked loop in the TE’s receiver to correctly identify bit timing from the NT and to synchronize its own transmission to that of the NT. On identifying INFO 2 for 3 consecutive frames, the TE changes its transmit data to INFO 3 and awaits the return of INFO 4 from the NT. Identi- fication of INFO 4 completes the Activation sequence, so Status Indication type AI is set, and the INT output pulled low. Activation initiated from the NT: when Activation is initiated by the NT, if the TP3420A in TE mode is powered down, it will pull the LSD pin and INT low on receiving a line signal. Either of these can be used to “wake-up” a microprocessor. A PUP command is required to enable the device to power-up, identify the received signal, and acquire bit and frame synchronization. Once INFO 2 has been identified, the TP3420A will pull INT low, with Status Indication type AP set, to alert the microprocessor that Activation is pending. The microprocessor must respond by writing Control Instruction type AR in order for Activation to proceed. INFO 3 frames are then transmitted. Finally, an AI Status Indication interrupt is generated when the NT replies with INFO 4 frames. As in NT mode, once Activated, loss of frame alignment is assumed by the TP3420A when a time equivalent to three frames has passed without it detecting any of the valid pairs of line code violations which obey the framing rule. If the TE does detect alignment loss it will cease transmitting immedi- ately. At this point the Error Indication (EI) primitive is set in the Status Register, the INT output is pulled low and the re- ceiver searches to re-acquire loop synchronization if INFO 2 or INFO 4 frames are still being received. If synchronization is re-established, a further interrupt is generated, with Status Indication type AI. If, however, the receiver subsequently identifies that the incoming line signal has ceased, i.e. INFO www.national.com 16

force the transmission of INFO 0. packet, or a Priority Class 2 packet, is selected. TABLE 7. D-Channel Access Criteria

8 Signalling packet (Priority

Class 1) may begin (Note 13).

9 Signalling packet may begin

10 Any packet type may begin

(Priority Class 2) (Note 14).

11 Any packet type may

sequence of≥ 9 consecutive “1”s has been detected in the E-channel. is pulled low to interrupt the Layer 2 transmit processor. x output pulses are again inhibited. flag on the Bx input from the layer 2 device. Indication type EOM set, to indicate the End of Message. 1’s (9 or 11) is detected in the D-echo-bit position. mode is to enable the D channel access mechanism.

used to set the E-bit control back to normal condition. across the network having restricted facility links. and does not need to provide an inverted bit stream. Table 8. One word is and SC5 allocated in the downstream direction. status of the network to the TEs. ceptions before generating the MFR1 or MFR2 interrupts. Table 8. When a 3x message is received an interrupt is are validated 3 times before generating the MFR2 interrupt. in response to received SC1, SC2 or Q channel codes (e.g. ms, but not more than 3 messages within 10 ms.

Functional Description(Continued) A 6x multiframe counter (30 ms) in the TP3420A is enabled by the MFC6E command, and disabled with the MFC6D command. When the counter is enabled (MFC6E), an inter- rupt MFC is generated locally every 30 ms and internal logic ensures that the MFT1L messages are transmitted 6 times unless interrupted by an MFT1H message. Alternatively, if the software chooses to keep count of repeti- tions of transmitted multiframe messages, the command MFC1E can be used to cause the interrupt MFC at every multiframe boundary (5 ms). The 6x transmit logic is then disabled. If both MFC6E and MFC1E commands are loaded, the MFC1E command has precedence and causes the 1x (5 ms) interrupt. It is expected that the user will prefer the 30 ms interrupt to control transmission of multiframe mes- sages because it reduces the processor load considerably, as outlined below and in examples in the Appendix A. Software Table of SC1 Messages The software in the NT should keep a table of SC1 mes- sages to be communicated to the TE, and use the MFC (30 ms) interrupt as a synchronous timer to load SC1 messages. Using X’3X command for SC1 messages, the software must write the appropriate Low Priority message to the MFT1L register within 30 ms of the interrupt. The message is then transmitted on the next 6x multiframe boundary and is re- peated 6 times. If the MFT1L register is not updated by a new MICROWIRE command from the CPU within 30 ms, the data from the MFT1L register is re-transmitted another 6 times. Transmission of SC1H - High Priority Messages In the NT mode, commands such as LP, FECV, and DTSE are considered to be High Priority messages. These are loaded through the MFT1H register and sent out once on the next multiframe boundary. In the following multiframe this message gets replaced with the contents of MFT1L, the Low Priority Register. At every multiframe boundary, the device checks whether the MFT1H register has a new message; if it has, that message is sent once, otherwise the contents of the MFT1L register are sent. In TE modes on the receive side, the high priority messages on the SC1 channel (LP, ST, FECV and DTSE) are accepted as valid on the first occurrence and the MFR1 interrupt is generated to indicate the status (see Table 8). Transmission of QH - High Priority Messages In TE modes, a Loss of Power condition is conveyed to the NT by writing the LP command in the MFT1H register for a “one shot” high priority message which overrides any other Q channel message. Write the LP message in the MFT1L register to ensure continuing transmission of the LP mes- sages. Normal maintenance commands such as LB1 Re- quest are written to the MFT1L register. SC2 Channel Messages With the MFC6E enabled, the TP3420A guarantees the 6x transmission of SC2 messages according to the ANSI 1991 spec. The software should load an SC2 message in to the MFT2 register within 30 ms of the MFC interrupt. The multi- frame word for the SC2 stream is then transmitted on the next 6x boundary and repeated 6 times. If the register is not updated by another MFT2 message within 30 ms, then the device will re-cycle the existing message in the SC2 register, i.e. re-transmit it 6 times. www.national.com19

TABLE 8. Codes for SC1, SC2 and Q Channel Messages with 3X Checking Enabled Note 16:The code “0011” will be received by an NT1 when the LB1 and LB2 requests are transmitted by two different TEs (NT2s) on a Passive Bus.

Functional Description(Continued) BIPOLAR VIOLATION DETECTION AND FECV MESSAGING VIA THE SC1 CHANNEL NT Mode A Receive Multiframe Error (RMFE) detector circuit in the TP3420A identifies any multiframes in which one or more bi- polar violations is received, indicating a bit in error. If one or more line code violation errors occur in a received multi- frame (5 ms), the TP3420A generates the RMFE (Receive Multiframe Error) interrupt. The microcontroller has to send the Far End Code Violation, FECV (1110) word over the SC1 channel through the MFT1H register. The FECV message is then sent once, after which the SC1 channel reverts to send- ing the message from the MFT1L register. The RMFE circuit detects frame code violations in 16 frames (out of 20 frames in the multiframe) not containing the multi- frame Q bit data and detects correct DC balancing in all 20 frames, including the frames containing the multiframe data. The RMFE detector is operational whether multiframing messaging is used or not. The RMFE interrupt is disabled by default on power-up. It is normally enabled after activation is completed by writing the ENINT command. TE Mode When the TE end device receives an FECV message in the SC1 channel, it is validated on a single occurrence, and the device generates the MFR1. If one or more line code violation errors occur in the received multiframe, the device will generate the RMFE interrupt. The microcontroller may then keep a count of frame errors being received. Currently, there is no provision in T1-605 for in- forming the NT about the errors received at the TE end. The RMFE circuit detects frame code violations as well as DC balancing in all 20 frames in the multiframe. In the TE re- ceived frames, the S bit (for SC1, SC2, etc.) is independent of the auxiliary framing pulses. The RMFE detector is opera- tional whether multiframing messaging is used or not. The RMFE interrupt is disabled by default on power-up. It is nor- mally enabled after activation is completed by writing the ENINT command. Applications Information While the pins of the TP3420A SID are well protected against electrical misuse, it is recommended that the stan- dard CMOS practice of applying GND to the device before any other connections are made should always be followed. In applications where the printed circuit card may be plugged into a hot socket with power and clocks already present, an extra long ground pin on the connector should be used. To minimize noise sources, all ground connections to each device should meet at a common point as close as possible to the GND pin in order to prevent the interaction of ground return currents flowing through a common bus impedance. A decoupling capacitor of 0.1 µF should be connected from this common point to V CC . Taking care with the pcb layout in the following ways will help prevent noise injection into the receiver front-end and maximize the transmission perfor- mance: 1. keep the crystal oscillator components away from the re- ceiver inputs and use a shielded ground plane around these components. 2. keep the connections between the device and the com- ponents on the L i± inputs short; the Li− capacitors should be connected close to the device pins. 3. keep the connections between the device and the trans- formers short. Figure 6shows a typical application of the TP3420A in an ISDN Terminal. For more in-depth information on a variety of applications, hardware and software required to meet the I.430 interface specification. Performance measurements, demonstrating compliance with I.430 and ANSI transmission requirements, are also included. For additional information on firmware for the maintenance message channels see Appendix A of this datasheet. www.national.com21

Note 17:Primotype EM80-PMI2 or similar. Note 18:Primotype DH31 or similar. Note 19:Only necessary if a mechanical hook switch is connected to the NMI input of the HPC. Note 20:See TP3420A User’s Manual for Line Interface Protection. Note 21:The TP3076 Programmable Combos also require the MICROWIRE Port to be connected. Note 22:R = 22Ω when using a PE64995 transmit transformer and a connecting cord. See AN-872 (TP3420A Line Interface Circuit Considerations) for more details. Note 23:See additional applications note for detailed connections to MCG8302. FIGURE 6. Typical Application in a TE and/or TA

Absolute Maximum Ratings(Note 24) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V CC to GND 7V Voltage at Li,L0 VCC +1V to GND −1V Voltage at any Digital Input V CC +1V to GND −1V Storage Temperature Range −65˚C to+150˚C Current at L0 ±100 mA Current at any Digital Output ±50 mA Lead Temperature (Soldering, 10 sec.) 300˚C ESD rating 2000V

Electrical Characteristics

Unless otherwise noted: limits printed inbold characters are electrical testing limits at VCC = 5.0V and TA = 25˚C. All other limits are design goals for VCC = 5.0V ±5% , and TA = 0˚C to 70˚C. This data sheet is still preliminary and parameter limits are subject to change based on further characterization testing. Symbol Parameter Conditions Limits Units Min Typ Max DIGITAL INTERFACES V IL Input Low Voltage All Digital Inputs 0.7 V VIH Input High Voltage All Digital Inputs 2.2 V VILX Input Low Voltage MCLK/XTAL Input 0.5 V VIHX Input High Voltage MCLK/XTAL Input V CC − 0.5 V VOL Output Low Voltage B r,IL = 3.2 mA 0.4 V All Other Digital Outputs, IL = 1m A VOH Output High Voltage B r,IL = −3.2 mA 2.4 V All Other Digital Outputs, IL = −1 mA 2.4 V All Outputs, IL = −100 µA VCC − 0.5 V II Input Current Any Digital Input, GND < VIN < VCC −10 10 µA IOZ Output Current in High B r, INT, LSD, CO −10 10 µA Impedance State (TRI-STATE) GND < VOUT < VCC LINE INTERFACES R Li Differential Input GND < Li+, Li− < VCC 200 k Ω Resistance CL L0 Load Capacitance Between L o+ and Lo− 200 pF POWER DISSIPATION I CC 0 Power Down Current All Outputs Open-Circuit 1.20 mA ICC 1 Power Up Current As Above, Device Deactivated (Note 25) 25 mA TRANSMISSION PERFORMANCE Transmit Pulse Amplitude R L = 270Ω Between Lo+ and Lo− (Note 26) ±1.90 ±2.14 Vpk Transmit Pulse Unbalance 0+ Relative to 0− ±5 % Input Pulse Amplitude Differential Between Li+ and Li− ±175 mVpk Output Impedance when 50 Ω Load 100 Ω Transmitting Binary Zeroes 400Ω Load (Note 27) 14 Ω Note 24:“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Note 25:When the device is activated and driving a correctly terminated line, ICC1 increases by several mA. A worst-case data pattern, consisting of all binary 0’s, increases ICC1 by approximately 8 mA. Note 26:The pulse amplitude at the Lo± pins allows for approximately 1 dB transformer insertion loss to meet the 0.75V pulse mask test when the line is terminated in 50Ω . Note 27:Using a 2:1 PE64995 transformer and a connecting cord. See AN-872 (TP3420A Line Interface or Circuit Considerations) for more details. www.national.com 24

Symbol Parameter Conditions Min Typ Max Units MCLK SYSTEM CLOCK (See Figure 5) FMCK Master Clock Frequency 15.36 MHz Master Clock Tolerance −100 +100 ppm MCLK/XTAL Input Clock Jitter External Clock Source 50 ns pk-pk t MH , Clock Pulse Width V IH = VCC − 0.5V 20 ns tML Hi & Low for MCLK V IL = 0.5V tMR , Rise and Fall Time Used as a 10 ns tMF of MCLK Logic Input MICROWIRE CONTROL INTERFACE (See Figure 5) tCH CCLK High Duration 50 ns tCL CCLK Low Duration 50 ns tSIC Setup Time, CI 30 ns Valid to CCLK Edge tHCI Hold Time, CCLK 20 ns High to CI Invalid tDCSO Delay Time from CS Bit C7 only 50 ns Low to CO Valid tDCO Delay Time from CCLK Edge 50 ns to CO Data Valid t DCSZ Delay Time from CS High 30 ns to CO TRI-STATE tSCSC1 Setup Time, from CS Low to 30 ns CCLK Edge High tHCSC1 Hold Time, CS High from 40 ns CCLK Edge High tHCSC2 Hold Time, CS Low from 50 ns CCLK Edge High tSCSC2 Setup Time, CS High 50 ns to CCLK Edge High tCSH Duration of CS High 1µ s tDCI Delay Time CS Low to 250 ns INT High-impedance DIGITAL SYSTEM INTERFACE (See Figure 9) FBCK Bit Clock Frequency 256 4096 kHz tBH , Clock Pulse Width V IH = 2.2V 60 ns tBL Hi & Low for BCLK V IL = 0.7V tBR , Rise and Fall Time 15 ns tBF of BCLK tFSa/b Frame Sync Frequency 8 kHz tSBC Set up Time, Bx Valid All Modes 30 ns to BCLK Low tHCB Hold Time, Bx Valid All Modes 20 ns from BCLK Low tDCD Delay Time, BCLK Transition TEM, DCKE Mode 0 40 ns to DTCK Transition t SDT Setup Time, TxD Valid to TEM, DCKE Mode 30 ns BCLK Low t HDT Hold Time, BCLK Low to TxD Invalid TEM, DCKE Mode 20 ns www.national.com25

Note 28:This parameter can be extended by connecting a 10 kΩ pull-up resistor and a 10 pf pull-down capacitor to Br. FIGURE 9. Timing Details for Digital System Interface

Conventions (Continued) VOL VOL is the maximum d.c. output level to which an output placed in a logical zero state will converge when loaded at the maximum specified load current. Threshold Region The threshold region is the range of in- put voltages between V IL and VIH. Valid Signal A signal is Valid if it is in one of the valid logic states, (i.e. above VIH or below VIL). In timing specifications, a signal is deemed valid at the instant it enters a valid state. Invalid Signal A signal is Invalid if it is not in a valid logic state, i.e. when it is in the threshold region between V IL and VIH. In timing specifications, a signal is deemed invalid at the instant it enters the threshold re- gion. TIMING CONVENTIONS For the purposes of this timing specification the following conventions apply: Input Signals All input signals may be characterized as: V L = 0.4V, VH = 2.4V, tR < 10 ns, tF < 10 ns. Period The period of clock signal is designated as tPxxwhere xx represents the mne- monic of the clock signal being specified. Rise Time Rise times are designated as tRyy, where yy represents a mnemonic of the signal whose rise time is being specified. t Ryy is measured from VIL to VIH. Fall Time Fall times are designated as tFyy, where yy represents a mnemonic of the signal whose fall time is being specified. t Fyy is measured from VIH to VIL. Pulse Width High The high pulse width is designated as tWzzH , where zz represents the mne- monic of the input or output signal whose pulse width is being specified. High pulse widths are measured from V IH to VIH. Pulse Width Low The low pulse width is designated as tWzzL , where zz represents the mne- monic of the input or output signal whose pulse width is being specified. Low pulse widths are measured from V IL to VIL. Setup Time Setup times are designated as t Swwxx , where ww represents the mnemonic of the input signal whose setup time is be- ing specified relative to a clock or strobe input represented by mnemonic xx. Setup times are measured from the ww Valid to xx Invalid. Hold Time Hold times are designated as t Hxxww , where ww represents the mnemonic of the input signal whose hold time is being specified relative to a clock or strobe in- put represented by mnemonic xx. Hold times are measured from xx Valid to ww Invalid. Delay Time Delay times are designated as t Dxxyy[ |H|L], where xx represents the mnemonic of the input reference signal and yy represents the mnemonic of the output signal whose timing is being specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the high going or low going transition of the output signal. Maximum delay times are measured from xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This parameter is tested under the load conditions specified in the Conditions column of the Timing Specifications sec- tion of this data sheet. Appendix A FIRMWARE GUIDELINES FOR HANDLING SC1/Q AND SC2 MAINTENANCE MESSAGES This application note describes software guidelines that make use of TP3420A hardware features designed to sup- port the handling of the newly defined maintenance channels SC1/Q and SC2. Please refer to the TP3420A datasheet and the T1.605-1991 specification for explanations of the SC1/Q and SC2 messages. SC1 TRANSMITTER CONTROL IN NT UNIT The microcontroller software must keep a list of flags for SC1 messages of lower priority that need to be sent for 6 frames, in the following priority order as they occur: ST reports, LB indications, LRS, DOI, IDLE. These messages should be sent through the MFT1L register. The software should also keep a list of flags for the high priority messages that have to be sent once in the following priority order: LP, FECV, and DTSE commands. These messages should be sent through the MFT1H register. As part of the TP3420A initialization, the software should write the MFC6E command to cause the de- vice to generate the MFC interrupt every 30 ms, and this in- terrupt status should be used to synchronize the SC1L and any SC2 messages. Events and conditions that cause SC1 messages to be gen- erated arise from 3 different sources, the S interface loop, the U interface loop or from within the NT unit itself. S Loop conditions can cause the RMFE indication to indicate a code violation that must be reported to the TE by the FECV mes- sage. U loop conditions are communicated to the TE by the LRS, DOI and the DTSE messages. The NT local microcon- troller will generate the messages for the ST reports, LB in- dications, LP and the IDLE. Each 30 ms tick, the software should service the list of flags and go down the priority chain. The command (for MFT1L register) corresponding to the highest flag is sent to the MFT1L register and the flag is reset. The MFT1L commands may be updated at every 30 ms tick if any of the relevant flags are set. If a DTSE interrupt is received from the U inter- face, this command is immediately loaded into the MFT1H register. Similarly, a local RMFE interrupt should be re- sponded with a FECV command through the MFT1H register immediately. A double buffer has been implemented in the MFT1H register to ensure that 2 commands can be queued and each will be sent for 1 multiframe. The device has 2 4-bit register FIFOs. At every multiframe boundary, MFT1H FIFO www.national.com 28

is checked to see if it contains new data; if yes the data is sent out from the MFT1H FIFO, if not, then the data from the MFT1L register is sent. If both the buffers are full, then a third load to the MFT1H register will cause the first buffer to be overwritten by the second and the second buffer to be loaded with the third load. This way if a DTSE and FECV are already loaded, and the power on the NT1 starts to fail, the software can still write a LP command in the MFT1H register as well as the MFT1L register. This ensures that the commands will be sent out at the earliest moment and will continue until the power is com- pletely lost. Whenever a MFT1H command is written, a software flag FL__EXT (extend SC1L) should be set. This flag informs the software that 1 occurrence of the present 6x repetition of the SC1L messages was overwritten by a message from SC1H, and hence it is necessary to extend the MFT1L command for another 30 ms to guarantee 6x tranmission. This flag is reset after the next 30 ms tick. Example Assume Software flags and buffers are defined as: SC1L__PB - software variable, indicating previous data sent via the SC1L channel SC1L__NB - software variable, indicating the next value to be sent via the SC1L channel FL__EXT - Flag to Extend SC1L command for another 30 ms. MFT1L, MFT1H and MFT2, are the device registers. The sequences of events shown below indicate activity on the SC1 channel on the line and the actions required by the local microcontroller at each 30 ms (MFC status interrupt) ticks. SC1 Messaging Sequence Time SC1 Actions Required (ms) I430 Frame Content 0 (MFC INT) (IDLE) if FL__EXT flag not set, check for new flags on SC1L, assume LRS. Check for SC2 channel. Send SC2 command> MFT2. SC1__NB(IDLE) > SC1__PD, SC1 command(LRS) > SC1__NB, SC1__NB(LRS) > MFT1L. 5 (IDLE) 10 (IDLE) 15 (IDLE) 20 (IDLE) 25 (IDLE) 0 (MFC INT) (LRS) if FL__EXT flag not set, check for new flags on SC1L, assume IDLE. Check for SC2 channel Flags. Send SC2 command as appropriate. SC1__NB(LRS) > SC1__PB, SC1L command(IDLE) > SC1__NB, SC1__NB > MFT1L(IDLE). 5 (LRS) 10 (LRS) Assume DTSE-IN Interrupt from UID, Send DTSE > MFT1H register. Set the FL__EXT. SC1L__PB> MFT1L (LRS). 15 (DTSE) 20 (LRS) RMFE in Interrupt from local SID, FECV > MFT1H, SC1L__PB > MFT1L(LRS). Set FL-EXT. 25 (FECV) 0 (MFC INT) (LRS) if FL__EXT flag set, do not check for new flags on SC1L, but check for SC2 channel. Reset FL__EXT. Send SC2 command as appropriate, SC1L__NB (IDLE) > MFT1L. 5 (LRS) 10 (LRS) DTSE-IN Interrupt from UID, DTSE > MFT1H register. Set FL__EXT, SC1L__PB > MFT1L register. Also RMFE in Interrupt from local SID, FECV> MFT1H register. Set FL__EXT. SC1L__PB > MFT1L register. Now the FECV command is queued in the MFT1H register. 15 (DTSE) 20 (FECV) 25 (LRS) www.national.com29

SC1 Messaging Sequence (Continued) Time SC1 Actions Required (ms) I430 Frame Content 0 (MFC INT) (LRS) if FL__EXT flag set, do not check for new flags on SC1L, but check for SC2 channel. Reset FL__EXT. Send SC2 command as appropriate. SC1L__NB (IDLE) > MFT1L 5 (LRS) 10 (LRS) 15 (LRS) 20 (LRS) 25 (LRS) 0 (MFC INT) (IDLE) if FL__EXT flag not set, check for new flags on SC1L, assume LB1I. Check for SC2 channel. Send SC2 command as appropriate. SC1__NB(IDLE) > SC1__PB, SC1 command (LBL1I)> SC1__NB, SC1__NB(LB1I) > MFT1L. 5 (IDLE) 10 (IDLE) 15 (IDLE) 20 (IDLE) 25 (IDLE) 0 (MFC INT) (LB1I) if FL__EXT flag not set, Check for new flags on SC1L assume LB2I. Check for SC2 channel. Send SC2 command as appropriate. SC1__NB(LB1I) > SC1__PB, SC1 command(LB2I) > SC1__NB, SC1__NB(LB2I) > MFT1L 5 (LB1I) 10 (LB1I) 15 (LB1I) 20 (LB1I) 25 (LB1I) 0 (MFC INT) (LB2I) if FL__EXT flag not set, check for new flags on SC1L, assume IDLE. Check for SC2 channel. Send SC2 command as appropriate. SC1__NB(LB2I) > SC1__PB, SC1 command (IDLE) > SC1__NB SC1__ NB(IDLE) > MFT1L. 5 (LB2I) 10 (LB2I) 15 (LB2I) 20 (LB2I) 25 (LB2I) 0 (MFC INT) (IDLE) etc. On theTE receive side,the LP, DTSE and FECV messages are checked once, and forevery occurrence an interrupt is generated. The other messages are validated 3 times be- fore an interrupt is generated. Subsequent repetitions of the command do not cause an interrupt. SC2 CHANNEL TRANSMITTER HANDLING The software should keep a list of flags to indicate SC2 com- mands as defined in the spec. At the 30 ms tick MFC INT, the software should scan through the list of flags (top down) and, seeing the first flag, should write the appropriate command in the MFT2 register and keep the value in SC2__NB (soft- ware buffer). On the TE receive side, the SC2 command is verified 3 times before an Interrupt is generated. Subsequent repeti- tions of the command do not cause an interrupt. www.national.com 30

Physical Dimensionsinches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number TP3420AJ Molded Dual-In-Line Package (N) Order Number TP3420AN www.national.com31

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Order Number TP3420AV TP3420A ISDN S/T Interface Device National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.