TP3404V/63SN

TP3404_14 TI1 | Alldatasheet

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www.ti.com SNOS703 –DECEMBER 2004 TP3404QuadDigitalAdapterforSubscriberLoops(QDASL) Check forSamples: TP3404 1FEATURES DESCRIPTION The TP3404 isa combination4-linetransceiverfor 23• 4 COMPLETE ISDN PBX 2-WIRE DATA voice and data transmissionon twisted pairTRANSCEIVERS INCLUDING: subscriber loops, typicallyin PBX line card• Quad 2 B Plus D Channel InterfaceforPBX applications.It is a companion device to the “U ” Interface TP3401/2/3 DASL single-channeltransceivers.In additionto 4 independenttransceivers,a time-slot• 144 kb/sFull-Duplexon 1 TwistedPairUsing assignmentcircuitisincludedtosupportinterfacingtoBurstMode TransmissionTechnique thesystembackplane.• Loop Range up to6 kft(#24AWG) Each QDASL lineoperatesas an ISDN “U ” Interface• AlternateMark InversionCoding withTransmit for short loop applications,typicallyin a PBXPulse Shaping DAC, Smoothing Filter,and environment,providingtransmissionfor2 B channelsScrambler forLow Emi Radiation and 1 D channel.• AdaptiveLineEqualizer Full-duplextransmissionat 144 kb/sisachievedon• On-Chip Timing Recovery,No External single twisted wire pairs using a burst-modeComponents technique(TimeCompressionMultiplexed).Alltiming

• Programmable Time-SlotAssignment TDM sequences necessary for loop activationand de- InterfaceforB Channels activationaregeneratedon-chip.
• SeparateInterfaceforD Channel with AlternateMark Inversion(AMI)linecodingisused to Programmable Sub-SlotAssignment ensure low errorratesinthe presenceof noisewith loweremi radiationthanothercodes such as Biphase• 4.096MHz Master Clock (Manchester).On #24 AWG cable the range is at• 4 Loop-Back TestModes least1.8km (6kft.).
• MICROWIRE ™ Compatible SerialControl Interface
• 5V Operation
• 28-PinPLCC Package BLOCK DIAGRAM Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2MICROWIRE isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2004,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNOS703 –DECEMBER 2004 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) VDDA /VDDD toGNDA/GNDD 7V VoltageatAny Li,Lo Pin VCC + 1V toGND − 1V CurrentatAny Lo ±100 mA VoltageatAny DigitalInput VCC + 1V toGND − 1V CurrentatAny DigitalOutput ±50 mA StorageTemperatureRange −65°C to+150°C Lead Temperature(Soldering,10 sec.) 300°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.Operatingratingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications.

ELECTRICAL CHARACTERISTICS

Unlessotherwisespecified,limitsprintedinBOLD charactersarespecifiedforVCCA = VCCD = 5V ±5%, TA = 0°C to+70°C. TypicalcharacteristicsarespecifiedatVDDA = VDDD = 5.0V,TA = 25°C. AllsignalsarereferencedtoGND, whichisthe common ofGNDA and GNDD Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACES VIH InputHighVoltage AllDigitalInputs(DC) 2 V VIL InputLow Voltage AllDigitalInputs(DC) 0.8 V VOH OutputHighVoltage IL = +1 mA 2.4 V VOL OutputLow Voltage IL = −1 mA 0.4 V IIL InputLow Current AllDigitalInput,GND < VIN < VIL −10 10 μA IIH InputHighCurrent AllDigitalInput,VIH < VIN < VCC −10 10 μA IOZ OutputCurrentinHighImpedance (TRl-STATE) BO, CO, and DO −10 10 μA LINE INTERFACES R Li InputResistance 0V < VLi< VCC 20 kΩ C LLo Load Capacitance From Lo toGND 200 pF ROLS OutputResistance Load = 60Ω inSerieswith2 μF toGND 3 Ω VDC Mean DC VoltageatLo Load = 200Ω inSerieswith2 μF toGND 1.75 2.25 VVoltageatLS+, LS− POWER DISSIPATION ICC 0 Power Down Current BCLK = 0 Hz;MCLK = 0 Hz,CCLK = 0 Hz 10 mA ICC 1 Power Up Current All4 ChannelsActivated 75 mA TRANSMISSION PERFORMANCE TransmitPulseAmplitudeatLo R L = 200Ω inSerieswith2 μF toGND 1.1 1.3 1.5 Vpk InputPulseAmplitudeatLi ±60 mVpk TIMING SPECIFICATIONS Symbol Parameter Conditions Min Typ Max Units MASTER CLOCK INPUT SPECIFICATIONS fMCLK FrequencyofMCLK 4.096 MHz MasterClockTolerance Relative2X MCLK inSlave −100 +100 ppm tWMH PeriodofMCLK High Measured fromVIH toVIH 70 ns tWML PeriodofMCLK Low Measured fromVILtoVIL 70 ns tRM RiseTime ofMCLK Measured fromVILtoVIH 15 ns tFM FallTime ofMCLK Measured fromVIH toVIL 15 ns

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www.ti.com SNOS703 –DECEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) Unlessotherwisespecified,limitsprintedinBOLD charactersarespecifiedforVCCA = VCCD = 5V ±5%, TA = 0°C to+70°C. TypicalcharacteristicsarespecifiedatVDDA = VDDD = 5.0V,TA = 25°C. AllsignalsarereferencedtoGND, whichisthe common ofGNDA and GNDD Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACE TIMING fBCLK BCLK Frequency 4.096 4.1 MHz tWBH , ClockPulseWidthHigh Measured fromVIH toVIH 70 ns tWBL and Low forBCLK Measured fromVILtoVIL 70 tRB , RiseTime and FallTime Measured fromVILtoVIH 15 ns tFB ofBCLK Measured fromVIH toVIL 15 tHBM BCLK TransitiontoMCLK HighorLow −30 30 ns tSFC Setup Time,FS ValidtoBCLK Invalid 20 4 ns tHCF HoldTime,BCLK Low toFS Invalid 40 30 ns tSBC SetupTime,BIValidtoBCLK Invalid 30 11 ns tHCB HoldTime,BCLK ValidtoBIInvalid 40 7 ns tSDC SetupTime,DI ValidtoBCLK Low 30 ns tHCD HoldTime,BCLK Low toDI Invalid 40 ns tDCB DelayTime,BCLK HightoBO Valid Load = 2 LSTTL + 100 pF 80 ns tDCBZ DelayTime,BCLK Low toBO High-Z 80 120 ns tDCD DelayTime,BCLK HightoDO valid Load = 2 LSTTL + 100 pF 80 ns tDCZ DelayTime,BCLK Low toDO HighImpedance 40 120 ns tDCT DelayTime,BCLK HightoTSB Low 120 ns tZBT DisableTime,BCLK Low toTSB High-Z 120 ns MICROWIRE CONTROL INTERFACE TIMING fCCLK FrequencyofCCLK 2.1 MHz tCH PeriodofCCLK High Measured fromVIH toVIH 150 ns tCL PeriodofCCLK Low Measured fromVILtoVIL 150 ns tSSC SetupTime,CS Low toCCLK High 50 ns tHCS HoldTime,CCLK HightoCS Transition 40 ns tSIC SetupTime,CI ValidtoCCLK High 50 ns tHCI HoldTime,CCLK HightoCI Invalid 20 ns tDCO DelayTime,CCLK Low toCO Valid 80 ns tDSOZ DelayTime,CS HightoCO High-Z 80 ns tDCIZ DelayTime,CCLK toINT High-Z 100 ns Copyright© 2004,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TP3404

SNOS703 –DECEMBER 2004 www.ti.com PIN DESCRIPTIONS Pin Pin

Description

No. Name 1 GNDA AnalogGround or0V.Allanalogsignalsarereferencedtothispin. 15 GNDD DigitalGround 0V.Itmust connecttoGNDA witha shortestpossibletrace.Thiscan be done directlyunderneaththepart. 28 VDDA Positivepower supplyinputtoQDASL analogsection.Itmust be 5V ±5%. 16 VDDD Positivepower supplyinputtoQDASL digitalsection.Itmust be 5V ±5%, and connecttoVDDA withtheshortestpossible trace.Thiscan be done directlyunderneaththepart. 11 FS Frame Sync input:thissignalisthe8 kHz clockwhichdefinesthestartofthetransmitand receiveframesatthedigital interfaces. 9 MCLK Thispinisthe4.096MHz MasterClockinput,whichrequiresa CMOS logiclevelclockfroma stablesource.MCLK must be synchronouswithBCLK. 10 BCLK BitClocklogicinput,whichdeterminesthedatashiftrateforB and D channeldataattheBI,BO, DI and DO pins.BCLK may be any multipleof8 kHz from256 kHz to4.096MHz, butmust be synchronouswithMCLK. 12 BI Time-divisionmultiplexedinputforB1 and B2 channeldatatobe transmittedtothe4 lines.Data on thispinisshiftedinon thefailingedge ofBCLK intotheB1 and B2 channelsduringtheselectedtransmittime-slots. 13 BO Time-divisionmultiplexedreceivedataoutputbus.B1 and B2 channeldatafromall4 linesisshiftedouton therisingedge ofBCLK on thispinduringtheassignedreceivetime-slots.AtallothertimesthisoutputisTRI-STATE (highimpedance). 14 TSB Thispinisan open-drainoutputwhichisnormallyhighimpedance butpullslowduringany activeB channelreceivetime slotsattheBO pin. 7 DI Time-divisionmultiplexedinputforD channeldatatobe transmittedtothe4 lines.Data on thispinisshiftedinon the failingedge ofBCLK intotheD channelduringtheselectedtransmitsub-time-slots. 8 DO Time-divisionmultiplexedoutputforD channeldatareceivedfromthe4 lines.Data on thispinisshiftedouton therising edge ofBCLK duringtheselectedreceivesub-time-slot. 19 CCLK MicrowireControlClockinput.ThisclockshiftsserialcontrolinformationintoCI and outfromCO when theCS inputislow, dependingon thecurrentinstruction.CCLK may be asynchronouswiththeothersystemclocks. 21 CI ControldataInput.SerialcontrolinformationisshiftedintotheQDASL on thispinon therisingedges ofCCLK when CS is low. 17 INT Interruptrequestoutput,a latchedoutputsignalwhichisnormallyhighimpedance and goes lowtoindicatea change of statusofany ofthe4 looptransmissionsystems.Thislatchisclearedwhen theStatusRegisterisreadby the microprocessor.BipolarViolationdoes noteffectthisoutput. 20 CO ControldataOutput.Serialcontrol/statusinformationisshiftedoutfromtheQDASL on thispinon thefallingedges of CCLK when CS islow. 18 CS ChipSelectinput.When thispinispulledlow,theMicrowireinterfaceisenabledtoallowcontrolinformationtobe written intoand outfromthedeviceviatheCI and CO ins.When high,thispininhibitstheMicrowireinterface. 4 Lo0 Linedrivertransmitoutputsforthe4 transmissionchannels.Each outputisan amplifierintendedtodrivea transformer.

3 Lo1

26 Lo2

25 Lo3

5 Li0 Linereceiveamplifierinputsforthe4 transmissionchannels.Each Lipinisa self-biasedhighimpedance inputwhich 2 Li1 shouldbe connectedtothetransformerviatherecommended lineinterfacecircuit.

27 Li2

24 Li3

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NC * CI CO CCLK Li0 NC DI DO MCLK BCLK FS Lo0 Lo1 Li1 GNDA VDDA Li2 Lo2 BI BO TSB GNDD VDDD INT CS NRND TP3404 www.ti.com SNOS703 –DECEMBER 2004 CONNECTION DIAGRAM *Do notconnecttothispin. Figure1. Top View See Package Number FN0028A Copyright© 2004,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TP3404

SNOS703 –DECEMBER 2004 www.ti.com FUNCTIONAL DESCRIPTION The QDASL contains4 transceivers,each of which can interoperatewithany of the TP340X familyof single- channelDASL transceivers.Each QDASL transceiverhas itsown independentlinetransmitand receivesection, timingrecoverycircuit,scrambler/descramblerand loopactivationcontroller.Functionswhicharesharedby the4 transceiversincludetheMicrowirecontrolportand thedigitalinterfacewithtime-slotassignment. BURST MODE OPERATION For full-duplexoperationovera singletwisted-pair,burstmode timingisused,withtheQDASL end ofeach line actingas thelooptimingmaster,and theDASL attheterminalbeingthetimingslave(theQDASL transceivers cannotoperateinlooptimingslavemode). Each burstwithina DASL lineisinitiatedby theQDASL Mastertransmittinga startbit,forburstframing,followed by theB1, B2 and D channeldatafrom2 consecutive8 kHz frames,combined intheformatshown inFigure2. Duringtransmitburststhereceiverinputforthatchannelisinhibitedtoavoiddisturbingtheadaptivecircuits.The slave'sreceiverisenabled at thistime and itsynchronizesto the startbitof the burst,which isalways an unscrambled“1”(oftheoppositepolaritytothelast“1”sentinthepreviousburst).When theslavedetectsthat 36 bitsfollowingthestartbithave been received,itdisablesthereceivedinput,waits6 linesymbol periodsto match theotherend settlingguardtime,and thenbeginstotransmititsburstback towardsthemaster,whichby thistimehas enableditsreceiverinput.The burstrepetitionrateisthus4 kHz. LINE TRANSMIT SECTIONS AlternateMark Inversion(AMI)linecoding,inwhich binary“1”s are alternatelytransmittedas a positivepulse thena negativepulse,isused on each DASL linebecause ofitsspectralefficiencyand nullDC energycontent. Alltransmittedbits,excludingthestartbit,arescrambledby a 9-bitscramblertoprovidegood spectralspreading witha strongtimingcontent.The scramblerfeedbackpolynomialis:X9 + X5 + 1. Figure2. BurstMode Timing on theLine Pulseshapingisobtainedby means ofa DigitaltoAnalogConverterfollowedby a ContinuousSmoothingFilter, inorderto limitRF energy and crosstalkwhileminimizingInter-SymbolInterference(ISI).Figure3 shows the pulseshape attheLo output,whilea templateforthetypicalpower spectrumtransmittedtothelinewithrandom dataisshown inFigure4. Each line-driveroutput,Lo0–Lo3,isdesignedtodrivea transformerthrougha capacitorand terminationresistor. A 1:1transformer,terminatedin100Ω,resultsinsignalamplitudeoftypically1.3Vpk on theline.Over-voltage protectionmust be includedineach interfacecircuit.

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www.ti.com SNOS703 –DECEMBER 2004 LINE RECEIVE SECTIONS The inputof each receivesection,Li0–Li3,consistsof a continuousanti-aliasfilterfollowedby a switched- capacitorlow-passfilterdesignedtolimitthenoisebandwidthwithminimum intersymbolinterference.To correct pulseattenuationand distortioncaused by thetransmissionlinean AGC circuitand first-orderequalizeradaptto thereceivedpulseshape,thusrestoringa “flat” channelresponsewithmaximum receivedeye openingovera widespreadofcableattenuationcharacteristics. From theequalizedoutputa DPLL (DigitalPhase-LockedLoop)recoversa low-jitterclockforoptimum sampling ofthereceivedsymbols.The MCLK inputprovidesthereferenceclockfortheDPLL at4.096MHz. Followingdetectionof the recoveredsymbols,the receiveddata isde-scrambledby the same X9 + X5 + 1 polynomialand presentedtothedigitalsysteminterfacecircuit. When a transmissionlineisde-activated,a Line-SignalDetectCircuitisenabled to detectthe presence of incomingburstsifthefar-endstartstoactivatetheloop. Figure3. TypicalAMI Waveform atLo Figure4. TypicalAMI TransmitSpectrum Measured atLO Output (WithRGB = 100 Hz) Copyright© 2004,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TP3404

SNOS703 –DECEMBER 2004 www.ti.com ACTIVATION AND LOOP SYNCHRONIZATION Activation(i.e.power-up and loopsynchronization)may be initiatedfrom eitherend of the loop.Ifthe master (QDASL) end isactivatingtheloop,itsends normalburstsofscrambled“1”s which are detectedby theslave's line-signal-detectcircuitry.The slavethen replieswithburstsof scrambled“1”s synchronizedto the received bursts,and the Framing Detectioncircuitat each end searchesfor4 consecutivecorrectlyformattedreceive burststo acquirefullloop synchronization.The QDASL receiverindicateswhen itis correctlyin sync with receivedburstsby settingan indicationintheStatusRegisterand pullingtheINT pinlow. For theslaveend toinitiateactivation,itbeginstransmissionofalternateburstsi.e.,theburstrepetitionrateis2 kHz,not4 kHz.At thispointtheslaveisrunningfromitslocaloscillatorand isnotreceivingany sync information fromthemaster.When themaster'sLine-SignalDetectCircuitrecognizesthis“wake-up”signal,theappropriate QDASL linemust be activatedby writingto the ControlRegister.The master begins to transmitbursts synchronized,as normal,to the FS inputwitha 4 kHz repetitionrate.This enablesthe slave'sreceiverto correctlyidentifybursttimingfrom the master and to re-synchronizeitsown bursttransmissionsto those it receives.The FramingDetectionCircuitsthenacquirefullloopsyncas describedearlier. Loop synchronizationisconsideredtobe lostiftheFramingDetectionCircuitdoes notfindfourframingmarks of thefourconsecutive4 kHz lineframes.At thispointan indicationissetintheStatusRegister,theINT outputis pulledlow,and thereceiversearchestore-acquireloopsync. MICROWIRE CONTROL INTERFACE A serialinterface,whichcan be clockedindependentlyfromtheB and D channelsystem interfaces,isprovided formicrocontrolleraccess to the time-slotassignment,Controland StatusRegistersin the QDASL. The microcontrollerisnormallythetimingmasterofthisinterface,and itsuppliestheCCLK and CS signals. Alldatatransfersconsistofsimultaneousreadand writecycles,inwhich2 continuousbytesaresampled on the CI pin,atthesame timeas 2 bytesare shiftedoutfrom theCO pin,see Figure7.The firstbyteisa register addressand thesecond isthedata.To initiatea Microwireread/writecycle,CS must be pulledlow for16 cycles ofCCLK. Data on CI issampled on risingedges ofCCLK, and shiftedoutfromCO on failingedges.When CS is high,theCO pinisinthehigh-impedanceTRI-STATE, enablingtheCO pinsofmany devicestobe multiplexed together. Whenever a change (exceptBipolarViolation)inany oftheQDASL statusconditionsoccurs,theInterruptoutput INT ispulledlow toalertthemicroprocessortoinitiatea readcycleoftheStatusRegister.Thislatchedoutputis clearedwhen thereadcycleisinitiated. Table 1 liststhe address map of controlfunctionsand statusindicators.Table 2 liststhe addressesforthe ControlRegistersforeach QDASL line.Even-numbered addressesare read-writecycles,in which the data returnedby theCO pinispreviouscontentsoftheaddressedregister.Odd-numbered addressesare readback commands only. Table1.GlobalRegisterAddress Map Address Registers (Hex) 00–0F LINE 0 Control(TSX,TSR,CTRL) 10–1F LINE 1 Control(TSX,TSR,CTRL) 20–2F LINE 2 Control(TSX,TSR,CTRL) 30–3F LINE 3 Control(TSX,TSR,CTRL) 40–CF Not used FF Common StatusRegisterforalllines(0–3). See Table6

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(1) Bit7 ofbytes1 and 2 isalwaysthefirstbitclockedintooroutfromtheCI and CO pins. (2) N = 0,1,2,or3 instraightBinarynotationforLine0,1,2,or3 respectively. activation,Ioopbacks,Interruptenablingand D channelinterfaceenabling.Table3 liststhefunctions. Line-SignalDetectCircuitcontinuallymonitorsitsline,todetectifthefar-endinitiateslooptransmission. Table 3. SettingC7 low de-activatesthe loop,or putsthe channelinpower-down state.Duringpower-down state,internalregisterdataisretained,and stillcan be accessed. pinback totheLo pin.Data outon BO/DO isstillthesame as receivedattheLiinput. theline.TransmitdataintheB2 and D channelsisfromtheBi/DIpins. – As (2)butfortheB2 channel.

SNOS703 –DECEMBER 2004 www.ti.com – Thisloopwilltransferalldata(2B+D) receivedatBI/DIback toBO/DO. The dataisalsotransmittedtothe line. TIME-SLOT ASSIGNMENT The digitalinterfaceoftheQDASL uses time-divisionmultiplexing,withdataframed inup to64 possible8-bit time-slotsper125 μs frame.ChannelsB1 and B2 forall4 linesareclockedin(towardstheline)attheBIpinand clockedout(fromtheline)attheBO pin.A separateportisprovidedfortheD channeldataforall4 lines,which isclockedinon DI and outon DO. Inadditiontotime-slotassignment,D channeldatamay be assignedinto2-bit sub-slotswithineach timeslot,withup to256 sub-slotsperframe(withBCLK = 4.096MHz). Each framestarts withthefirstpositiveedge ofBCLK aftertheFS signalgoes high,and countingoftimeslotsstartsfrom zeroat thebeginningoftheframe.Figure5 shows thetiming,withsome example time-slotassignments. For each ofthe4 QDASL linesthereare 6 Time-SlotAssignmentcontrolregisters,one each fortransmitand receiveB1, B2 and D channels.Selectionoftime-slotsfortransmitdataintotheBI orDI pinismade by writing thetimeslotnumber (inHex notation)intotheappropriateTSX register.TSXB1 isthetime-slotassignmentfor thetransmitB1, TSXB2 isthetime-slotassignmentregisterforthetransmitB2 channeland TSXD isthesub-slot assignmentregisterforthetransmitD channel. Table3.Byte 2 ofControlRegister(CTRLN) BitNumber Function 7 6 5 4 3 2 1 0

0 DeactivateLine

1 ActivateLine

0 DisableDigitalLoopback

1 Enable2B+D DigitalLoopback

0 DisableLineLoopback

1 Enable2B+D LineLoopback

0 DisableB1 LineLoopback

1 EnableB1 LineLoopback

0 DisableB2 LineLoopback

1 EnableB2 LineLoopback

0 DisableInterruptfromthisLine

1 EnableInterruptfromthisLine

0 D ChannelenabledfromDO toLine

1 D ChanneldisabledfromDO toLine

0 D ChannelenabledfromLinetoDI

1 D ChanneldisabledfromLinetoDI

Inthesame manner thetime-slotnumber shouldbe writtenintotheappropriateTSR registersforreceivedataat the BO and DO pins.TSRB1 isthe time-slotassignmentforthe receiveB1 channel,TSRB2 isthe time-slot assignmentregisterforthereceiveB2 channeland TSRD isthesub-slotassignmentregisterforthereceiveD channel. Whenever any receivetime-slotisactiveatBO, theTSB outputisalsopulledlow. REGISTERS TSXB1, TSXB2, TSRB1, TSRB2 The dataformatforallB channeltime-slotassignmentregistersisshown inTable4. BIT 7 TRANSPARENCY CONTROL: EB Thisbitenablesordisablesdatatransparencybetween thedigitalinterfaceand thelineinterfacefortheselected channel. EB = 0 disablesthechannel. EB = 1 enablesthechannel.

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www.ti.com SNOS703 –DECEMBER 2004 When thetransmitdirection(towardstheline)isdisabledtherewillbe all“ONE's” (scrambled)as dataforthis channelat the Lo pin.Ifthe receivedirection(fromthe line)isdisabled,BO willstayhighimpedance forthe programmed timeslotwhile,ifitisenabled,dataouton BO intheassignedtimeslotisthedatafromLi. BITS 5–0:TS5 –TS0 These bitsdefinethebinarynumber ofthetime-slotselected.Time-slotsare numbered from 0–63.The frame syncsignalisused as markerpulsesforthebeginningoftimeslot0. Table4.Byte 2 ofRegisterTSXB1, TSXB2, TSRB1 or TSRB2 forB Channel Time-SlotAssignment BitNumber and Name Function 7 6 5 4 3 2 1 0 EB X TS5 TS4 TS3 TS2 TS1 TS0

0 X X X X X X X DisableB1 and/orB2

1 X AssignOne BinaryCoded Time-Slotfrom0–63 EnableB1 and/orB2

REGISTERS TXD, TRD The dataformatforallD channeltime-slotassignmentregistersisas follows: Data transparencybetween thedigitalinterfaceand thelineinterfacefortheD channelscan be controlledviathe ChannelControlRegister,see Table3. BITS 7–0:TS7 –TS0 These bitsdefinethebinarynumber ofthesub-slotselected.Sub-slotsare numbered from 0–255.The frame syncsignalisused as markerpulsesforthebeginningofSub-slot0. Table5.Byte 2 ofRegisterTSXD or TSRD forD Channel Time-SlotAssignment BitNumber and Name 7 6 5 4 3 2 1 0 SS SS SS SS SS SS SS SS 7 6 5 4 3 2 1 0 AssignOne BinaryCoded Sub-Slotfrom0–255 forD Channel Figure5. QDASL DigitalInterfaceTiming Copyright© 2004,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TP3404

SNOS703 –DECEMBER 2004 www.ti.com Table6.StatusRegisterFunctions Byte 2 Indication 7 6 5 4 3 2 1 0 0 0 Line3:deactivated 0 1 Line3:linesignalpresentbutnotinsync 1 0 Line3:activated,bipolarviolation(1) 1 1 Line3:activated,no bipolarviolation 0 0 Line2:deactivated 0 1 Line2:linesignalpresentbutnotinsync 1 0 Line2:activated,bipolarviolation(1) 1 1 Line2:activated,no bipolarviolation 0 0 Line1:deactivated 0 1 Line1:linesignalpresentbutnotinsync 1 0 Line1:activated,bipolarviolation(1) 1 1 Line1:activated,no bipolarviolation 0 0 Line0:deactivated 0 1 Line0:linesignalpresentbutnotinsync 1 0 Line0:activated,bipolarviolation(1) 1 1 Line0:activated,no bipolarviolation (1) BipolarViolationdoes notcause an Interrupt. STATUS REGISTER Statusinformationforall4 channelsmay be readfromthecommon StatusRegisterby addressinglocationX′FF. 2 bitsperlinearecoded as shown inTable6.A change inthestatusof1 ormore linesisindicatedby theINT pinbeingpulledlow,providedbit2 ofthecorrespondingcontrolregisterissetto“ONE ”toenabletheinterruptfor thatline. BIPOLAR VIOLATION DETECTOR On an activatedline,whenever a lineerrorisreceivedtherewillbe a violationoftheAMI codingrule.Thisis reportedby settingthecode 10 forthatline.The violationindicationisclearedto11 aftera read oftheStatus Register. As an example of the interpretationof the StatusRegistercontents,ifthe byte2 read back from the Status Register=00111001 (=X′39),thisindicatesthefollowingstatusofthe4 lines:line3 isdeactivated;line2 isin sync withno errorsincethelastreadcycle;line1 isinsync buttherehas been 1 ormore errorssincethelast readcycleoftheStatusRegister;line0 isreceivinga linesignalbutthelinetransmissionisnotsynchronized.

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www.ti.com SNOS703 –DECEMBER 2004 APPLICATIONS INFORMATION POWER SUPPLIES WhilethepinsoftheTP3404 QDASL devicearewellprotectedagainstelectricalmisuse,itisrecommended that the standardCMOS practiceof applyingGND to the devicebeforeany otherconnectionsare made should alwaysbe followed.Inapplicationswhere theprintedcircuitcardmay be pluggedintoa hotsocketwithpower and clocksalreadypresent,an extralonggroundpinon theconnectorshouldbe used. To minimizenoisesources,theVDDA and VDDD pinsshouldbe connectedtogetherviatheshortestpossible trace;likewisethe GNDA and GNDD pinsmust be connectedtogether.These two connectionscan be done directlyunderneaththe part.Allotherground connectionsto each deviceshouldmeet at a common pointas closeas possibletotheGNDD pininordertopreventtheinteractionofgroundreturncurrentsflowingthrougha common bus impedance.A power supplydecouplingcapacitorof0.1μF shouldbe connectedfromthiscommon pointtoVDDD as closeas possibletothedevicepins. Figure6 shows a typical4 lineapplicationoftheQDASL. The currentlistofsuitablecommercialtransformersis: SchottCorporation(Nashville); Phone 615-889-8800. Partnumbers:67110850 (dry); Partnumbers:67110860 (50mA DC). PulseEngineering(San Diego); Phone 619-674-8100. Partnumber:TBD. Note thattheZener diodeprotectionshown inFigure9 isonlyintendedas secondaryprotectionforinsidewiring applications;primaryprotectionisalsonecessary.Furtherinformationcan be found in the datasheetforthe TP3401/2/3 DASL devices(SNOSC12 ) and in ApplicationNote AN-509 “Using the TP3401/2/3 ISDN PBX Transceivers”. Copyright© 2004,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TP3404

SNOS703 –DECEMBER 2004 www.ti.com Figure6. TypicalApplication

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www.ti.com SNOS703 –DECEMBER 2004 Figure7. MicrowireControlInterfaceTiming Details Figure8. B Channel DigitalInterfaceDetails Figure9. D-Channel DigitalInterfaceTiming Details Copyright© 2004,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TP3404

www.ti.com 12-Jul-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TP3404V/63SN NRND PLCC FN 28 750 Green (RoHS & no Sb/Br) CU SN Level-2A-245C-4 WEEK TP3404V TP3404V/NOPB NRND PLCC FN 28 35 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR TP3404V (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 12-Jul-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MPLC004A – OCTOBER 1994 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B 03/95

20 PIN SHOWN

0.026 (0,66) 0.032 (0,81) D2/E2 0.020 (0,51) MIN 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D2/E2 0.013 (0,33) 0.021 (0,53) Seating Plane MAX D2/E2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) NOM 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D E1E MINMAXMIN PINS 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) D/E 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) NO. OF D1/E1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

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