TP3404

TP3404 NSC | Alldatasheet

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4 COMPLETE ISDN PBX 2-WIRE DATA TRANSCEIVERS

INCLUDING: Y Quad 2 B plus D channel interface for PBX ‘‘U’’ interface Y 144 kb/s full-duplex on 1 twisted pair using Burst Mode Transmission Technique Y Loop range up to 6 kft ( Ý24AWG) Y Alternate Mark Inversion coding with transmit Pulse Shaping DAC, Smoothing Filter, and scrambler for low emi radiation Y Adaptive line equalizer Y On-chip timing recovery, no external components Y Programmable Time-Slot Assignment TDM interface for B channels Y Separate interface for D channel with Programmable Sub-Slot Assignment Y 4.096 MHz master clock Y 4 loop-back test modes Y MICROWIRETM compatible serial control interface Y 5V operation Y 28-pin PLCC package Block Diagram TL/H/11924–1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. MICROWIRETM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. V DDA/VDDD to GNDA/GNDD 7V Voltage at Any Li, Lo Pin V CC a 1V to GND b 1V Current at Any Lo g100 mA Voltage at Any Digital Input V CC a 1V to GND b 1V Current at Any Digital Output g50 mA Storage Temperature Range b65§Ct o a150§C Lead Temperature (Soldering, 10 sec.) 300 §C Electrical Characteristics Unless otherwise specified, limits printed in BOLD characters are guaranteed for VCCA e VCCD e 5V g5%, T A e 0§Ct o a70§C. Typical characteristics are specified at V DDA e VDDD e 5.0V, T A e 25§C. All signals are referenced to GND, which is the common of GNDA and GNDD Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACES VIH Input High Voltage All Digital Inputs (DC) 2 V VIL Input Low Voltage All Digital Inputs (DC) 0.8 V VOH Output High Voltage I L ea 1m A 2.4 V VOL Output Low Voltage I L eb 1m A 0.4 V IIL Input Low Current All Digital Input, GND k VIN k VIL b10 10 mA IIH Input High Current All Digital Input, V IH k VIN k VCC b10 10 mA IOZ Output Current in High Impedance BO, CO, and DO b10 10 mA(TRl-STATEÉ) LINE INTERFACES RLi Input Resistance 0V k VLi k VCC 20 k X CLLo Load Capacitance From Lo to GND 200 pF ROLS Output Resistance Load e 60X in Series with 2 mF to GND 3 X VDC Mean DC Voltage at Lo Load e 200X in Series with 2 mFt oG N D 1.75 2.25 VVoltage at LS a,L S b POWER DISSIPATION ICC0 Power Down Current BCLK e 0 Hz; MCLK e 0 Hz, CCLK e 0H z 1 0 m A ICC1 Power Up Current All 4 Channels Activated 75 mA TRANSMISSION PERFORMANCE Transmit Pulse Amplitude at Lo R L e 200X in Series with 2 mF to GND 1.1 1.3 1.5 Vpk Input Pulse Amplitude at Li g60 mVpk TIMING SPECIFICATIONS Symbol Parameter Conditions Min Typ Max Units MASTER CLOCK INPUT SPECIFICATIONS fMCLK Frequency of MCLK 4.096 MHz Master Clock Tolerance Relative 2X MCLK in Slave b100 a100 ppm tWMH Period of MCLK High Measured from V IH to V IH 70 ns tWML Period of MCLK Low Measured from V IL to V IL 70 ns tRM Rise Time of MCLK Measured from V IL to V IH 15 ns tFM Fall Time of MCLK Measured from V IH to V IL 15 ns

Electrical Characteristics Unless otherwise specified, limits printed in BOLD characters are guaranteed for VCCA e VCCD e 5V g5%, T A e 0§Ct o a70§C. Typical characteristics are specified at V DDA e VDDD e 5.0V, T A e 25§C. All signals are referenced to GND, which is the common of GNDA and GNDD (Continued) TIMING SPECIFICATIONS (Continued) Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACE TIMING fBCLK BCLK Frequency 4.096 4.1 MHz tWBH, Clock Pulse Width High Measured from V IH to V IH 70 nstWBL and Low for BCLK Measured from V IL to V IL 70 tRB, Rise Time and Fall Time Measured from V IL to V IH 15 nstFB of BCLK Measured from V IH to V IL 15 tHBM BCLK Transition to MCLK High or Low b30 30 ns tSFC Set up Time, FS Valid to BCLK Invalid 20 4n s tHCF Hold Time, BCLK Low to FS Invalid 40 30 ns tSBC Setup Time, BI Valid to BCLK Invalid 30 11 ns tHCB Hold Time, BCLK Valid to BI Invalid 40 7n s tSDC Setup Time, DI Valid to BCLK Low 30 ns tHCD Hold Time, BCLK Low to DI Invalid 40 ns tDCB Delay Time, BCLK High to BO Valid Load e 2 LSTTL a 100 pF 80 ns tDCBZ Delay Time, BCLK Low to BO High-Z 80 120 ns tDCD Delay Time, BCLK High to DO valid Load e 2 LSTTL a 100 pF 80 ns tDCZ Delay Time, BCLK Low to DO High 40 120 nsImpedance tDCT Delay Time, BCLK High to TSB Low 120 ns tZBT Disable Time, BCLK Low to TSB High-Z 120 ns MICROWIRE CONTROL INTERFACE TIMING fCCLK Frequency of CCLK 2.1 MHz tCH Period of CCLK High Measured from V IH to V IH 150 ns tCL Period of CCLK Low Measured from V IL to V IL 150 ns tSSC Setup Time, CS Low to CCLK High 50 ns tHCS Hold Time, CCLK High to CS Transition 40 ns tSIC Setup Time, CI Valid to CCLK High 50 ns tHCI Hold Time, CCLK High to CI Invalid 20 ns tDCO Delay Time, CCLK Low to CO Valid 80 ns tDSOZ Delay Time, CS High to CO High-Z 80 ns tDCIZ Delay Time, CCLK to INT High-Z 100 ns Notes: For the purposes of this specification the following conditions apply a. All input signals are defined as V IL e 0.4V, V IH e 2.7V, t r k 10 ns, t f k 10 ns. b. Delay times are measured from the input signal Valid to the output signal Valid. c. Setup times are measured from the Data input Valid to the clock input Invalid. d. Hold times are measured from the clock signal Valid to the Data input Invalid.

Pin Pin DescriptionNo. Name 1 GNDA Analog Ground or 0V. All analog signals are referenced to this pin. 15 GNDD Digital Ground 0V. It must connect to GNDA with a shortest possible trace. This can be done directly underneath the part. 28 VDDA Positive power supply input to QDASL analog section. It must be 5V g5%. 16 VDDD Positive power supply input to QDASL digital section. It must be 5V g5%, and connect to VDDA with the shortest possible trace. This can be done directly underneath the part. 11 FS Frame Sync input: this signal is the 8 kHz clock which defines the start of the transmit and receive frames at the digital interfaces. 9 MCLK This pin is the 4.096 MHz Master Clock input, which requires a CMOS logic level clock from a stable source. MCLK must be synchronous with BCLK. 10 BCLK Bit Clock logic input, which determines the data shift rate for B and D channel data at the BI, BO, DI and DO pins. BCLK may be any multiple of 8 kHz from 256 kHz to 4.096 MHz, but must be synchronous with MCLK. 12 BI Time-division multiplexed input for B1 and B2 channel data to be transmitted to the 4 lines. Data on this pin is shifted in on the failing edge of BCLK into the B1 and B2 channels during the selected transmit time-slots. 13 BO Time-division multiplexed receive data output bus. B1 and B2 channel data from all 4 lines is shifted out on the rising edge of BCLK on this pin during the assigned receive time-slots. At all other times this output is TRI-STATE (high impedance). 14 TSB This pin is an open-drain output which is normally high impedance but pulls low during any active B channel receive time slots at the BO pin. 7 DI Time-division multiplexed input for D channel data to be transmitted to the 4 lines. Data on this pin is shifted in on the failing edge of BCLK into the D channel during the selected transmit sub-time-slots. 8 DO Time-division multiplexed output for D channel data received from the 4 lines. Data on this pin is shifted out on the rising edge of BCLK during the selected receive sub-time-slot. 19 CCLK Microwire Control Clock input. This clock shifts serial control information into CI and out from CO when the CS input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. 21 CI Control data Input. Serial control information is shifted into the QDASL on this pin on the rising edges of CCLK when CS is low. 17 INT Interrupt request output, a latched output signal which is normally high impedance and goes low to indicate a change of status of any of the 4 loop transmission systems. This latch is cleared when the Status Register is read by the microprocessor. Bipolar Violation does not effect this output. 20 CO Control data Output. Serial control/status information is shifted out from the QDASL on this pin on the falling edges of CCLK when CS is low. 18 CS Chip Select input. When this pin is pulled low, the Microwire interface is enabled to allow control information to be written in to and out from the device via the CI and CO ins. When high, this pin inhibits the Microwire interface. 4 Lo0 Line driver transmit outputs for the 4 transmission channels. Each output is an amplifier intended to drive a transformer.3 Lo1

26 Lo2

25 Lo3

5 Li0 Line receive amplifier inputs for the 4 transmission channels. Each Li pin is a self-biased high impedance input which should be connected to the transformer via the recommended line interface circuit.2 Li1

27 Li2

24 Li3

loop sync as described earlier. low, and the receiver searches to re-acquire loop sync. Figure 6. The first byte is a register address and the vices to be multiplexed together. the read cycle is initiated. numbered addresses are readback commands only. FF Common Status Register for all lines (0–3). Note 1: N e 0, 1, 2, or 3 in straight Binary notation for Line 0, 1, 2, or 3 respectively. Note 2: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI and CO pins.

Functional Description (Continued) LINE CONTROL REGISTERS CTRLN Each of the 4 transceivers has a Line Control Register, CTRL0–CTRL3, which provides for control of loop activa- tion, Ioopbacks, Interrupt enabling and D channel interface enabling. Table 3 lists the functions. POWER ON INITIALIZATION Following the initial application of power, the QDASL enters the power-down (de-activated) state, in which all the internal circuits are inactive and in a low power state except for a Line-Signal Detect Circuit for each of the 4 lines, and the necessary bias circuits. The 4 line outputs, Lo0–Lo3, are in a high impedance state and all digital outputs are inactive. All bits in the Line Control Registers power-up initially set to ‘‘0’’. While powered-down, each Line-Signal Detect Circuit continually monitors its line, to detect if the far-end initiates loop transmission. POWER-UP/DOWN CONTROL To power-up the device and initiate activation, bit C7 in any of the 4 Line Control Registers must be set high, see Table III. Setting C7 low de-activates the loop, or puts the channel in power-down state. During power-down state, internal reg- ister data is retained, and still can be accessed. LOOPBACKS Four different loopbacks can be set for each line. They are enabled and disabled by setting the corresponding bits in the Control Register, see Table III. In addition, a line must be activated to see the effect of loopback commands. 1. 2B aD Line Loopback When bit 5 is set to 1, this loop will transfer all three channels, B1, B2 and D, that are received at the Li pin back to the Lo pin. Data out on BO/DO is still the same as received at the Li input. 2. B1 Line Loopback When bit 4 is set high, the loop path is the same as (1) but only data on the B1 channel is looped back to the line. Transmit data in the B2 and D channels is from the Bi/DI pins. 3. B2 Line Loopback As (2) but for the B2 channel. 4. 2B aD Digital Loopback This loop will transfer all data (2B aD) received at BI/DI back to BO/DO. The data is also transmitted to the line. TIME-SLOT ASSIGNMENT The digital interface of the QDASL uses time-division multi- plexing, with data framed in up to 64 possible 8-bit time- slots per 125 ms frame. Channels B1 and B2 for all 4 lines are clocked in (towards the line) at the BI pin and clocked out (from the line) at the BO pin. A separate port is provided for the D channel data for all 4 lines, which is clocked in on DI and out on DO. In addition to time-slot assignment, D channel data may be assigned into 2-bit sub-slots within each time slot, with up to 256 sub-slots per frame (with BCLK e 4.096 MHz). Each frame starts with the first posi- tive edge of BCLK after the FS signal goes high, and count- ing of timeslots starts from zero at the beginning of the frame. Figure 4 shows the timing, with some example time- slot assignments. For each of the 4 QDASL lines there are 6 Time-Slot As- signment control registers, one each for transmit and re- ceive B1, B2 and D channels. Selection of time-slots for transmit data into the BI or DI pin is made by writing the timeslot number (in Hex notation) into the appropriate TSX register. TSXB1 is the time-slot assignment for the transmit B1, TSXB2 is the time-slot assignment register for the trans- mit B2 channel and TSXD is the sub-slot assignment regis- ter for the transmit D channel. TABLE III. Byte 2 of Control Register (CTRLN) Bit Number Function 76543210

0 Deactivate Line

1 Activate Line

0 Disable Digital Loopback

1 Enable 2B

0 Disable Line Loopback

1 Enable 2B aD Line Loopback

0 Disable B1 Line Loopback

1 Enable B1 Line Loopback

0 Disable B2 Line Loopback

1 Enable B2 Line Loopback

0 Disable Interrupt from this Line

1 Enable Interrupt from this Line

0 D Channel enabled from DO to Line

1 D Channel disabled from DO to Line

0 D Channel enabled from Line to DI

1 D Channel disabled from Line to DI

assignment register for the receive D channel. isters is shown in Table IV. signed time slot is the data from Li.

1 X Assign One Binary Coded Time-Slot Enable B1 and/or

data out on Bo is not valid while data out on Lo is valid. nel Control Register, see Table III. FIGURE 4. QDASL Digital Interface Timing

FIGURE 5. Typical Application

TP3404 Quad Digital Adapter for Subscriber Loops (QDASL) Physical Dimensions inches (millimeters) Plastic Chip Carrier (V) Order Number TP3404V LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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