TP3401 NSC | Alldatasheet
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Complete ISDN PBX 2-Wire Data Transceiver including: Y 2 B plus D channel interface for PBX U Ê Interface Y 144 kb/s full-duplex on 1 twisted pair using Burst Mode Y Loop range up to 6 kft ( Ý24AWG) Y Alternate Mark Inversion coding with transmit filter and scrambler for low emi radiation Y Adaptive line equalizer Y On-chip timing recovery, no external components Y Standard TDM interface for B channels Y Separate interface for D channel Y 2.048 MHz master clock Y Driver for line transformer Y 4 loop-back test modes Y Single a5V supply Y MICROWIRETM compatible serial control interface Y Applications in: PBX Line Cards Terminals Regenerators Y Available in both 20-pin DIP and 28-pin PLCC Block Diagram TL/H/9264–1Note 1: TP3401 only. TRI-STATEÉ is a registered trademark of National Semiconductor Corporation MICROWIRETM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/H/9264–2 Order Number TP3401J See NS Package Number J20A TP3402 DASL TL/H/9264–15 Order Number TP3402J See NS Package Number J20A TL/H/9264–16 Order Number TP3403V See NS Package Number V28A Pin Descriptions Name Description GND Negative power supply pin, normally 0V. All analog and digital signals are referred to this pin. V CC Positive power supply input, which must be a5Vg5%. MCLK The 2.048 MHz Master Clock input, which (TP3401 only) requires a CMOS logic level clock input from a stable source. Must be synchronous with BCLK. MCLK/XTAL This pin is the 2.048 MHz Master Clock in- (TP3402/3403 put, which requires either a crystal to be con- only) nected between this pin and XTAL2 or a CMOS logic level clock from a stable source, which must be synchronous with BCLK. XTAL2 This pin is the output side of the oscillator (TP3402 and amplifier. TP3403 only) MBS/FS C In Master Mode, this pin is the Master Burst (TP3401 and Sync input, which may be clocked at 4 kHz TP3403 only) to synchronize Transmit bursts from a num- ber of devices at the Master end only. The 4 kHz should be nominally a square wave sig- nal. If not used leave this pin open. In Slave mode, this pin is a short Frame Sync output, suitable for driving another DASL in Master Mode to provide a regenerator (i.e. range-ex- tender) capability. BCLK Bit Clock logic signal which determines the data shift rate for B channel data on the digi- tal interface side of the device. In Master mode this pin is an input which may be any multiple of 8 kHz from 256 kHz to
2.048 MHz, but must be synchronous with
MCLK. In Slave mode this pin is an output at 2.048 MHz. FS a In Master mode only, this pin is the Transmit Frame Sync pulse input, requiring a positive edge to indicate the start of the active chan- nel time for transmit B channel data into B FSa must be synchronous with BCLK and MCLK. In Slave mode only, this pin is a digi- Name Description tal output pulse which indicates the 8-bit pe- riods of the B1 channel data transfer at both B x and B r. FSb In Master mode only, this pin is the Receive Frame Sync pulse input, requiring a positive edge to indicate the start of the active chan- nel time of the device for receive B channel data out from B r;F S b must be synchronous with BCLK and MCLK. In Slave mode only, this pin is a digital output pulse which indi- cates the 8-bit periods of the B2 channel data transfer at both B x and B r. Bx Digital input for B1 and B2 channel data to be transmitted to the line; must be synchro- nous with BCLK. B r Digital output for B1 and B2 channel data received from the line. TSr/LSD In Master mode only, this pin is an open- drain output which is normally high imped- ance but pulls low during both B channel ac- tive receive time slots. In Slave mode only, this pin is an output which is normally high impedance and pulls low when a valid line signal is received. D x Digital input for D channel data to be trans- mitted to the line; must be synchronous with DCLK. D r Digital output for D channel data received from the line. DCLK/DEN In Master mode this pin is an input for the 16 kHz serial shift clock for D channel data on D x and D r, which should be synchronous with BCLK. It may also be re-configured via the Control Register to act as an enable in- put for clocking the D channel interface syn- chronized to BCLK. In Slave mode this is a 16 kHz clock output for D channel data. *Crystal specifications: 2.048 MHz parallel resonant, R S s 100X with a 20 pF load. Crystal tolerance should be g75 ppm for aging and tempera- ture.
Pin Descriptions (Continued) Name Description CI MICROWIRE control channel serial data in- put. CO MICROWIRE control channel serial data out- put. CCLK Clock input for the MICROWIRE control channel. CS Chip Select input which enables the MICRO- WIRE control channel data to be shifted in and out when pulled low. When high, this pin inhibits the MICROWIRE interface. INT Interrupt output, a latched output signal which is normally high-impedance and goes low to indicate a change of status of the loop transmission system. This latch is cleared when the Status Register is read by the mi- croprocessor. L o Transmit AMI signal output to the line trans- former. This pin is capable of driving a load impedance t 60X. Li Receive AMI signal input from the line trans- former. This is a high impedance input. Functional Description POWER-UP/POWER-DOWN CONTROL Following the initial application of power, the DASL enters the power-down (de-activated) state, in which all the internal circuits are inactive and in a low power state except for the line-signal detect circuit and the necessary bias circuit; the line output L o is in a low impedance state and all digital outputs are inactive. All bits in the Control Register power- up initially set to ‘0’, so that the device always initializes as the Master end. Thus, at the Slave end, a control word must be written through the MICROWIRE port to select Slave mode. While powered-down, the Line-Signal Detect circuits in both Master and Slave devices continually monitor the line, to enable loop transmission to be initiated from either end. To power-up the device and initiate activation, bit C6 in the Control Register must be set high. Setting C6 low de-acti- vates the loop and powers-down the device, see Table I. TABLE I. Master Mode Burst Sync Control (TP3401 Only) MBS/FSc C6Pin I/P State Action at Master Don’t Care 0 Powered-down, Line-Signal Detect active Open 1 Powered-up, sending bursts synchronized to FS a 4 kHz 1 Powered-up, sending bursts synchronized to MBS LINE TRANSMIT SECTION Alternate Mark Inversion (AMI) line coding is used on the DASL because of its spectral efficiency and null dc energy content. All transmitted bits, excluding the start bit, are scrambled by a 9-bit scrambler to provide good spectral spreading with a strong timing content. The scrambler feed- back polynomial is: x 9 a x5 a 1. Pulse shaping is obtained by means of a raised cosine switched-capacitor filter, in order to limit rf energy and crosstalk while minimizing inter-symbol interference (isi). Figure 3 shows the pulse shape at the L o output, while a template for the typical power spectrum transmitted to the line with random data is shown in Figure 4 . The line-driver output, L o, is designed to drive a transformer through a capacitor and termination resistor. A 1:1 trans- former, terminated in 100 X, results in a signal amplitude of typically 1.3V pk-pk on the line. Over-voltage protection must be included in the interface circuit. LINE RECEIVE SECTION The front-end of the receive section consists of a continu- ous anti-alias filter followed by a switched-capacitor low- pass filter designed to limit the noise bandwidth with mini- mum intersymbol interference. To correct pulse attenuation and distortion caused by the transmission line an AGC cir- cuit and first-order equalizer adapt to the received pulse shape, thus restoring a ‘‘flat’’ channel response with maxi- mum received eye opening over a wide spread of cable attenuation characteristics. From the equalized output a DPLL (Digital Phase-Locked Loop) recovers a low-jitter clock for optimum sampling of the received symbols. The MCLK input provides the refer- ence clock for the DPLL at 2.048 MHz. At the Master end of the loop this reference is the network clock (BCLK), which controls all transmit functions; the DPLL clock is used only for received data sampling. At the Slave end, however, a
2.048 MHz crystal is required to generate a stable local os-
cillator which is used as a reference by the DPLL to run both the receive and transmit sides of the DASL device. Following detection of the recovered symbols, the received data is de-scrambled by the same x 9ax5a1 polynomial and presented to the digital system interface circuit. When the device is de-activated, a Line-Signal Detect circuit remains powered-up to detect the presence of incoming bursts if the far-end starts to activate the loop. From a ‘‘cold’’ start, acquisition of bit timing and equalizer conver- gence with random scrambled data takes approximately 25 ms at each end of the loop. Full loop burst synchroniza- tion is achieved approximately 50 ms after the ‘‘activate’’ command at the originating end.
1 Slave Mode Read Back C7 from Control Register
1 Power Up and Activate Read Back C6 from Control Register
1 Loopback to Digital Interface Read Back C5 from Control Register
1 Loopback B1 aB2aD to Line (Note 1) Read Back C4 from Control Register
1 Loopback B1 Only to Line (Note 1) Read Back C3 from Control Register
1 Loopback B2 Only to Line (Note 1) Bipolar Violation Since Last READ (Note 2)
1 DCLK/DEN pin e D Channel Enable (Note 3) Loop In-Sync and Activation Complete
1 B1/B2 Channels Exchanged Line Signal Present at Receiver Input
Note 1: Receive data active. Note 2: After the device is in sync. Note 3: In Master mode only. Note 4: C7 is the first bit clocked in and out of the device. FIGURE 6. B Channel Interface Timing: Master Mode
FIGURE 13. Control Interface Timing
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. V CC to GND 7V Voltage at L i,L o VCCa1V to V SSb1V Voltage at any Digital Input V CCa1V to V SSb1V Storage Temperature Range b65§Ct o a150§C Current at L o g100 mA Current at any Digital Output g50 mA Lead Temperature (Soldering, 10 sec.) 300 §C ESD (Human Body Model) 2000V Electrical Characteristics Unless otherwise noted, limits printed in bold characters are guaranteed for V CC e 5.0V g5% and T A e 0§Ct o a70§C by correlation with 100% electrical testing at V CC e 5.0V and T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. Typical characteristics are specified at V CC e 5.0V and T A e 25§C. All digital signals are referenced to GND. Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACES VIL Input Low Voltage All Digital Inputs (not MCLK) 0.7 V VIH Input High Voltage All Digital Inputs (not MCLK) 2.2 V VOL Output Low Voltage I L e 1 mA 0.4 V VOH Output High Voltage I L eb 1 mA 2.4 V IIM Input Current at MBS/FS c GND k VIN k VCC b600 10 mA II Input Current Any Other Digital Input, GND k VIN k VCC b10 10 mA IOZ Output Current in B r, INT ,T S r,C O High Impedance GND k VOUT k VCC b10 10 mA State (TRI-STATE É) LINE INTERFACES RLi Input Resistance 0V k Li k 5.0V 50 k X CLLo Load Capacitance CL Lo from L o to GND. 100 pF RO Output Resistance Load e 60X in Series with 2 mFt oG N D 3.0 Xat L o VDC Mean d.c. Voltage Load e 60X in Series with 2 mFt oG N D 1.5 2.5 Vat L o POWER DISSIPATION ICC0 Power Down Current 1.3 2.2 mA ICC1 Power Up Current (Activated) Load at L o e 200X in Series with 2 mFt o 18 mAGND (in Master Mode) TRANSMISSION PERFORMANCE Transmit Pulse Amplitude at L o RL e 200X in Series with 2 mFt oG N D g0.9 g1.1 Vpk Input Pulse Amplitude at L i g60 mVpk Timing Recovery Jitter BCLK at Slave Relative to MCLK at Master 100 ns pk-pk
Unless otherwise noted: V CC ea 5V g5%, T A e 0§Ct o7 0 §C. Typical characteristics are specified at V CC e 5V, T A e 25§C. All signals are referenced to GND. Symbol Parameter Conditions Min Typ Max Units MASTER CLOCK INPUT SPECIFICATIONS FMCK Master Clock Frequency 2.048 MHz Master Clock Tolerance Measured Relative to the Slave MCLK b100 a100 ppm Master Clock Input Jitter 2.048 MHz Input, 18 kHz k f k 200 kHz 200 ns pk-pk tWMH, Clock Pulse Width V IH e VCC b 0.5V 190 nstWML Hi & Low for MCLK V IL e 0.5V tMR, Rise and Fall Time Used as a Logic Input 15 nstMF of MCLK B CHANNEL INTERFACE (Figure 10) FBCK Bit Clock Frequency Master Mode Only 2.048 MHz tWBH, Clock Pulse Width V IH e 2.2V 190 nstWBL Hi & Low for BCLK V IL e 0.7V tBR, Rise and Fall Time Master Mode requirement for BCLK 15 nsSourcetBF of BCLK tSFB Set-Up Time, FS a and Master Mode Only 70 nsFSb to BCLK Low tHCFL Hold Time, BCLK Low to Master Mode Only 100 nsFSa and FS b Low tWBH Output Pulse Width Slave Mode Only 195 nstWBL High and Low for BCLK Load e 2 LSTTL Inputs Plus 50 pF tDCF Delay Time, BCLK High to Slave Mode Only 115 nsFSa,F S b and FS c Transitions Load e 2 LSTTL Inputs Plus 50 pF tSBC Set Up Time, B X Valid 30 nsto BCLK Low tHCB Hold Time, BCLK Low to 50 nsBX Invalid tDCB Delay Time, BCLK High Load e 2 LSTTL Inputs Plus 100 pF 160 nsto B r Valid tDCBZ Delay Time, BCLK Low to Slave Mode Only 60 220 nsBr High-Impedance tDCT Delay Time, BCLK High Load e 2 LSTTL Inputs Plus 100 pF 180 nsto TS r Low tDCTZ Delay Time, BCLK Low to 60 185 nsTSr High-Impedance tSMBC Set-Up Time, MBS Master Mode Only 60 nsto BCLK Low (Note 1) (TP3401 and TP3403 only) tWMBH Width of MBS Input Master Mode Only 125 msHigh (TP3401 and TP3403 only) Note 1: MBS transitions may occur anywhere in the Frame, and require no specific relationship to FS a or FS b.
Timing Characteristics (Continued) Unless otherwise noted: V CC ea 5V g5%, T A e 0§Ct o7 0 §C. Typical characteristics are specified at V CC e 5V, T A e 25§C. All signals are referenced to GND. Symbol Parameter Conditions Min Max Units D CHANNEL INTERFACE (Figure 11 & 12) tSDDC Set Up Time, D X 100 nsValid to DCLK Low tHCD Hold Time, DCLK Low 100 nsto D X Invalid tDDCD Delay Time, DCLK High to Load e 100 pF 220 nsDr Data Valid a2 LSTTL Inputs tSDCB Set-Up Time, DCLK Master Mode 50 nsTransitions to BCLK High Only tHBDC Hold Time, BCLK High Master Mode 50 nsto DCLK Transitions Only tSDCF Set-Up Time, DCLK Master Mode 70 nsTransitions to FS a HIgh Only tDDED Delay Time, DEN High Load e 100 pF a 200 nsto D r Valid 2 LSTTL Inputs tSDEB Set-Up Time, DEN to 100 nsBCLK Low tSDBC Set-Up Time, D x 50 nsto BCLK Low tHBCD Hold Time, BCLK 50 nsLow to D x Invalid tDBCD Delay Time, BCLK Load e 100 pF 190 nsHigh to D r Valid a2 LSSTL Inputs tDCDZ Delay Time, DEN 140 nsLow to D r High Impedance CONTROL INTERFACE (Figure 13) tCH CCLK High Duration 250 ns tCL CCLK Low Duration 250 ns tSIC Setup Time, CI 100 nsValid to CCLK High tHCI Hold Time, CCLK High 0 nsto CI Invalid tSSC Setup Time from CS 200 nsLow to CCLK High tHCS Hold Time from CCLK 10 nsLow to CS tDCO Delay Time from CCLK Low Load e 100 pF 150 nsto C0 Data Valid a2 LSTTL Inputs tDSO Delay Time from CS 1st Bit Only 100 nsLow to CO Valid tDSZ Delay Time from CS High 100 nsto CO High Impedance tDCI Delay Time from CCLK1 120 nsHigh to INT High Impedance
Definitions and Timing Conventions DEFINITIONS VIH VIH is the d.c. input level above which an input level is guaranteed to appear as a logical one. This parameter is to be measured by performing a function- al test at reduced clock speeds and nominal timing, (i.e. not minimum setup and hold times or output strobes), with the high level of all driving signals set to V IH and maximum supply voltages applied to the device. VIL VIL is the d.c. input level below which an input level is guaranteed to appear as a logical zero to the device. This pa- rameter is measured in the same man- ner as V IH but with all driving signal low levels set to V IL and minimum supply voltages applied to the device. VOH VOH is the minimum d.c. output level to which an output placed in a logical one state will converge when loaded at the maximum specified load current. V OL VOL is the maximum d.c. output level to which an output placed in a logical zero state will converge when loaded at the maximum specified load current. Threshold Region The threshold region is the range of in- put voltages between V IL and V IH. Valid Signal A signal is Valid if it is in one of the valid logic states, (i.e. above V IH or be- low V IL). In timing specifications, a sig- nal is deemed valid at the instant it en- ters a valid state. Invalid Signal A signal is Invalid if it is not in a valid logic state, i.e. when it is in the thresh- old region between V IL and V IH. In tim- ing specifications, a signal is deemed invalid at the instant it enters the threshold region. TIMING CONVENTIONS For the purpose of this timing specification the following conventions apply: Input Signals All input signals may be characterized as: V L e 0.4V, V IH e 2.4V, t R k 10 ns, tF k 10 ns. Period The period of clock signal is designat- ed at t Pxx where xx represents the mnemonic of the clock signal being specified. Rise Time Rise times are designated at t Ryy, where yy represents a mnemonic of the signal whose rise time is being specified. t Ryy is measured from V IL to VIH. Fall Time Fall times are designated as t Fyy, where yy represents a mnemonic of the signal whose fall time is being specified. t Fyy is measured from V IH to VIL. Pulse Width High The high width is designated as t WzzH, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. High pulse widths are measured from V IH to V IH. Pulse Width Low The low pulse width is designed as tWzzL, where zz represents the mne- monic of the input or output signal whose pulse width is being specified. Low pulse widths are measured from V IL to V IL. Setup Time Setup times are designated as t Swwxx, where ww represents the mnemonic of the input signal whose setup time is be- ing specified relative to a clock or strobe input represented by mnemonic xx. Setup times are measured from the ww Valid to xx Invalid. Hold Time Hold times are designated as t Hxxww, where ww represents the mnemonic of the input signal whose hold time is be- ing specified relative to a clock or strobe input represented by mnemonic xx. Hold times are measured from xx Valid to ww invalid. Delay Time Delay times are designated as t Dxxyy [ lHlL], where xx represents the mne- monic of the input reference signal and yy represents the mnemonic of the out- put signal whose timing is being speci- fied relative to xx. The mnemonic may optionally be terminated by an H or L to specifiy the high going or low going transition of the output signal. Maxi- mum delay times are measured from xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy inval- id. This parameter is tested under the load conditions specified in the Condi- tions column of the Timing Specifica- tion section of this data sheet.
Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number TP3401J or TP3402J
TP3401, TP3402, TP3403 DASL Digital Adapter for Subscriber Loops Physical Dimensions inches (millimeters) (Continued) Plastic Chip Carrier (V) Order Number TP3403V LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
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