TP3155

TP3155 NSC | Alldatasheet

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Technical content

Features

Y Controls up to 8 COMBO CODEC/Filters Y Independent transmit and receive time slot assignments Y 8-channel unidirectional mode Y Up to 32 time slots per frame Y Serial control interface compatible with TP3020/TP3021 CODECs Y LS TTL and CMOS compatible inputs Y 5 mW, 5V operation Typical Application TL/H/5118–1 TRI-STATEÉ is a registered trademarks of National Semiconductor Corp. COMBOTM is a trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. V CC Relative to GND 7V Voltage at Any Input or Output V CC a 0.3V to GND b0.3V Operating Temperature Range (Ambient) b25§Ct o a125§C Storage Temperature Range (Ambient) b65§Ct o a150§C Maximum Lead Temperature (Soldering, 10 seconds) 300 §C ESD rating to be determined. Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g5%; T A e 0§Ct o a70§Cb y correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/ or product design and characterization. Typicals specified at V CC e 5.0V, T A e 25§C. Parameter Conditions Min Typ Max Units Input Voltage Levels VIH, Logic High 2.0 V VIL, Logic Low 0.7 V Input Currents All Inputs Except MODE V IL k VIN k VIH b11 mA MODE V IN e 0V b100 mA Output Voltage Levels VOH, Logic High FS X and FS R Outputs, I OH e 3 mA 2.4 V VOL, Logic Low FS X and FS R Outputs, I OL e 5 mA 0.4 V TSX Output, I OL e 5m A 0.4 V Power Dissipation BCLK e 2.048 MHz, 1 1.5 mA Operating Current All Outputs Open-Circuit Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g5%, T A e 0§Ct o a70§Cb y correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/ or product design and characterization. Typicals specified at V CC e 5.0V, T A e 25§C. All timing parameters are measured at VOH e 2.0V and V OL e 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Max Units tPC Period of Clock BCLK, CLK C 480 ns tWCH Width of Clock High BCLK, CLK C 160 ns tWCL Width of Clock Low BCLK, CLK C 160 ns tSDC Set-Up Time from D C to CLK C 50 ns tHCD Hold Time from CLK C to D C 50 ns tSCC Set-Up Time from CS to CLK C 30 ns tHCC Hold Time from CLK C to CS 100 ns tSCHC Set-Up Time from Channel Select to CLK C 50 ns tHCHC Hold Time from Channel Select to CLK C 50 ns tDBF Delay Time from BCLK Low to FS X/R 0–3 C L e 50 pF 100 ns High or Low tHSYNC Hold Time from BCLK to Frame Sync 50 ns tSSYNC Set-Up Time from Frame Sync to BCLK 100 ns tDTL Delay to TS X Low CL e 50 pF 140 ns tDTH Delay to TS X High RL e 1k to V CC 30 140 ns tRC,t FC Rise and Fall Time of Clock BCLK, CLK C 50 ns

TL/H/5118–2 Timing Diagrams Control Interface TL/H/5118–3 Output TL/H/5118–4

Plastic Chip Carrier (PCC) Package TL/H/5118–5 Order Number TP3155V See NS Package Number V20A Dual-In-Line Package TL/H/5118–6 Top View Order Number TP3155N See NS Package Number N20A Pin Descriptions Symbol Description FSX1 A conventional CMOS frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made. FS R1 A conventional CMOS frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made. FS X0 A transmit frame sync output similar to pin 1. FSR0 A receive frame sync output similar to pin 2. TSX An open-drain N-channel output which is nor- mally high impedance but pulls low during any active transmit time slot. D C The input for an 8-bit serial control word. X is the first bit clocked in. CLKC The clock input for the control interface. CS The active-low chip select for the control in- terface. MODE The mode select input. When left open-circuit or connected to V CC, mode 1 is selected, and when connected to GND, mode 2 is selected. GND The 0V ground connection to the device. Symbol Description BCLK The bit clock input, which should run at the same rate as that for the COMBO CODEC/ Filter COMBO. XSYNC The transmit TS0 sync pulse input. Must be synchronous with BCLK. RSYNC/CH2 The function of this input is determined by the MODE input (pin 9). In mode 1 this is the re- ceive TS0 sync pulse, RSYNC, which must be synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word. CH1 The input for the next significant bit of the channel select word. CH0 The input for the LSB of the channel select word, which defines the frame sync output af- fected by the following control word. FS X3 A transmit frame sync output similar to pin 1. FSR3 A receive frame sync output similar to pin 2. FSX2 A transmit frame sync output similar to pin 1. FSR2 A receive frame sync output similar to pin 2. VCC The positive supply to the device. 5V g5%.

The TP3155 control interface requires an 8-bit serial control word which is compatible with the TP3020/TP3021 and 2910/2911 CODECs. Two bits, X and R , define which of the two groups of frame sync outputs, FS X0t oF S X3o rF S R0t o FSR3, is affected by the control word, and a 6-bit assign- ment field specifies the selected time slot, from 0 to 31. A frame sync output is active-high for one time slot, which is always 8 cycles of BCLK. A frame may consist of any num- ber of time slots up to 32. If a timeslot is assigned which is beyond the number of time slots in a frame, the FS X or FS R output to which it was assigned will remain inactive. Two modes of operation are available. Mode 1 is for sys- tems requiring different time slot assignments for the trans- mit and receive direction of each channel. Mode 1 is select- ed by leaving pin 9 (MODE) open-circuit or connecting it to V CC. In this case, Pin 13 is the RSYNC input which defines the start of each receive frame, and the four outputs, FS R0–FS R3, are assigned with respect to RSYNC. The XSYNC input defines the start of each transmit frame and outputs FS X0–FS X3 are assigned with respect to XSYNC. XSYNC may have any phase relationship with RSYNC. In- puts CH0 and CH1 select the channel, from 0 to 3 (see Table Ia). Mode 2 provides the option of assigning all 8 frame sync outputs with respect to the XSYNC input. Mode 2 is select- ed by connecting pin 9 (MODE) to GND. This makes the TP3155 TSAC useful for either an 8-channel undirectional controller or for systems in which the transmit and receive directions of each channel are always assigned to the same time slot as the other, i.e., the FS X and FS R inputs on the COMBO CODEC/Filter are hard-wired together. In this case, logical selection of the channel to be assigned is made via inputs CH0, CH1 and CH2 (see Table Ib). POWER-UP INITIALIZATION During power-up, all frame sync outputs, FS X0–FS X3 and FSR0–FS R3, are inhibited and held low. No outputs will go active until a valid time slot assignment is made. LOADING CONTROL DATA During the loading of control data, the binary code for the selected channel must be set on inputs CH0 and CH1 (and CH2 in mode 2), see Tables Ia and Ib. Control data is clocked into the D C input on the falling edges of CLK C while CS is low. A new time slot assignment is transferred to the selected assignment register on the high going transition of CS . The new assignment is re-synchronized to the system clock such that the new FS output pulses will start at the next complete valid time slot after the rising edge of CS TIME SLOT COUNTER OPERATION At the start of TS0 of each transmit frame, defined by the first falling edge of BCLK after XSYNC goes high, the trans- mit time slot counter is reset to 000000 and begins to incre- ment once every 8 cycles of BCLK. Each count is compared with the 4 transmit assignment registers and, on finding a match, a frame sync pulse is generated at that FS X output. Similarly, the first falling edge of BCLK after RSYNC goes high defines the start of receive TS0, and outputs FS R0–FS R3 are generated with respect to TS0 when the receive time slot counter matches the appropriate receive assignment register. TS X OUTPUT In mode 1 (separate transmit and receive assignments), this output pulls low whenever any FS X output pulse is being generated. In mode 2, this output pulls low whenever any FS X or FS R output is being generated. At all other times it is open-circuit, allowing the TS X outputs of a number of TSACS to be wire-ANDed together with a common pull-up resistor. This signal can be used to control the TRI-STATE É enable input of a line driver to buffer the transmit PCM bus from the CODEC/Filters to the backplane. TABLE Ia. Control Mode 1 (TP3020/TP3021 Compatible) X R T5 T4 T3 T2 T1 T0 X is the first bit clocked into the D C input. Control Data Format T5 T4 T3 T2 T1 T0 Time Slot 000000 0 000001 1 000010 2 011110 3 0 011111 3 1

1 X X X X X (Note 1)

0 0 Assign to FS x0 and/or FS R0 0 1 Assign to FS x1 and/or FS R1 1 0 Assign to FS x2 and/or FS R2 1 1 Assign to FS x3 and/or FS R3 X R Action 0 0 Assign time slot to both selected FS X and FS R 0 1 Assign time slot to selected FS X only 1 0 Assign time slot to selected FS R only 1 1 Disable both selected FS X and FS R TABLE Ib. Control Mode 2 CH2 CH1 CH0 Channel Selected 0 0 0 Assign to FS X0 0 0 1 Assign to FS X1 0 1 0 Assign to FS X2 0 1 1 Assign to FS X3 1 0 0 Assign to FS R0 1 0 1 Assign to FS R1 1 1 0 Assign to FS R2 1 1 1 Assign to FS R3 X R Action 0 1 Assign time slot to selected output 1 1 Disable selected output Note 1: When T5 e 1, then the appropriate FS X or FS R output is inactive.

Definitions and Timing Conventions DEFINITIONS VIH VIH is the d.c. input level above which an input level is guaranteed to appear as a logical one. This parameter is to be measured by performing a function- al test at reduced clock speeds and nominal timing, (i.e. not minimum setup and hold times or output strobes), with the high level of all driving signals set to V IH and maximum supply voltages applied to the device. VIL VIL is the d.c. input level below which an input level is guaranteed to appear as a logical zero to the device. This pa- rameter is measured in the same man- ner as V IH but with all driving signal low levels set to V IL and minimum supply voltages applied to the device. VOH VOH is the minimum d.c. output level to which an output placed in a logical one state will converge when loaded at the maximum specified load current. V OL VOL is the maximum d.c. output level to which an output placed in a logical zero state will converge when loaded at the maximum specified load current. Threshold Region The threshold region is the range of in- put voltages between V IL and V IH. Valid Signal A signal is Valid if it is in one of the valid logic states, (i.e. above V IH or below VIL). In timing specifications, a signal is deemed valid at the instant it enters a valid state. Invalid Signal A signal is Invalid if it is not in a valid logic state, i.e. when it is in the thresh- old region between V IL and V IH. In tim- ing specifications, a signal is deemed Invalid at the instant it enters the threshold region. TIMING CONVENTIONS For the purposes of this timing specification the following conventions apply: Input Signals All input signals may be characterized as: V L e 0.4V, V H e 2.4V, t R k 10 ns, tF k 10ns. Period The period of clock signal is designated as t Pxx where xx represents the mne- monic of the clock signal being speci- fied. Rise Time Rise times are designated as t Ryy, where yy represents a mnemonic of the signal whose rise time is being speci- fied. t Ryy is measured from V IL to V IH. Fall Time Fall times are designated as t Fyy, where yy represents a mnemonic of the signal whose fall time is being speci- fied. t Fyy is measured from V IH to V IL. Pulse Width High The high pulse width is designated as tWzzH, where zz represents the mne- monic of the input or output signal whose pulse width is being specified. High pulse widths are measured from V IH to V IH. Pulse Width Low The low pulse width is designated as tWzzL, where zz represents the mne- monic of the input or output signal whose pulse width is being specified. Low pulse widths are measured from V IL to V IL. Setup Time Setup times are designated as t Swwxx, where ww represents the mnemonic of the input signal whose setup time is be- ing specified relative to a clock or strobe input represented by mnemonic xx. Setup times are measured from the ww Valid to xx Invalid. Hold Time Hold times are designated as t Hxxww, where ww represents the mnemonic of the input signal whose hold time is be- ing specified relative to a clock or strobe input represented by mnemonic xx. Hold times are measured from xx Valid to ww Invalid. Delay Time Delay times are designated as t Dxxyy[ lHlL], where xx represents the mnemonic of the input reference signal and yy represents the mnemonic of the output signal whose timing is being specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the high going or low going transition of the output signal. Maximum delay times are measured from xx Valid to yy Valid. Minimum de- lay times are measured from xx Valid to yy Invalid. This parameter is tested un- der the load conditions specified in the Conditions column of the Timing Speci- fications section of this data sheet.

FIGURE 3. Digital Interconnections on a Typical Synchronous Line Card

Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number TP3155N

TP3155 Time Slot Assignment Circuit Physical Dimensions inches (millimeters) (Continued) Lit. Ý113982 Plastic Chip Carrier Package (V) Order Number TP3155V LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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