TP3094

TP3094 NSC | Alldatasheet

Document overview

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Technical content

Features

• Handles four voice channels
• Complete Codec and Filter system including: - Transmit and receive channel filters - A-law or µ-law companding encoder/decoder
• Power down mode for low power consumption
• Compatible to standard time division multi- plexed PCM bus - 8 bit mode, frame signal from external reference - 32 bit mode, internal TSA, with consecutive TS
• Up to 128 channels (32 devices) can be cas- caded
• Programmable functions (common for all 4 channels): - A-law or µ-law - Single MCLK clock,automatically selectable from 8.192MHz, 4.096MHz, 2.048MHz and 1.536/1.544MHz - Digital and Analog loopback test modes
• Designed for CCITT and LSSGR applications
• Single +5V power supply
• 44 lead PLCC surface mount package
• Maximize line card circuit density
• Use in Central Office, Loop Carrier, and PBX equipment subscriber line and trunk cards
• Wide operating temperature range -40°C to 85°C Connection Diagram Order Number TP3094V TP3094 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 PD N 3 AVC C 1 VR O 3 G XO 3 VXI3 PD N 2 PD N 1 PD N 0 A/µLaw M C LK AGND1 VXI2 GXO2 VRO2 VRO1 NC GXO1 VXI1 NF AGND0 VXI0 G XO 0 VR O 0 AVC C 0 PT1 PC M M ode TSX PT2 TST FSR 0 FSX0 FSR1 FSX1 FSR2 FSX2 FSR3 FSX3 DVCC NC DGND DX D R PT4 PT3 See NS Package V44A COMBO ® and TRI-STATE® are registered trademarks of National Semiconductor Corporation

FIGURE 1. Simplified block diagram

3 www.national.com Pin Descriptions MCLK (input) Master and PCM bit clock input. Must be either 1.536MHz/1.544MHz, 2.048MHz, 4.096MHz or 8.192MHz. Its value is automatically detected in- ternally on power up with the valid frame sync in- put. AVCC0, AVCC1 Positive supply pins for the analog circuitry. AVCC0 is for channel 0 and channel 1. AVCC1 is for channel 2 and channel 3. AVCC0=AVCC1=+5V ±5%. These two pins should be connected together outside the device. AGND0, AGND1 Analog ground. All analog signals are referenced to AGND0 and AGND1. AGND0 is the analog ground for channel 0 and channel 1. AGND1 is the analog ground for channel 2 and channel 3. These two pins should be connected together outside the device. DVCC Positive supply for the digital circuitry. DVCC=+5V ±5%. DGND Digital ground. All logic signals are referenced to DGND. This ground has to be connected to the ground of other digital devices at board level. Analog ports VXI0-, VXI1-, VXI2-, VXI3- (inputs) Inverting analog inputs of the transmit input am- plifiers of channels 0-3. They are referenced to an internal reference voltage of about 2.4V. GXO0, GXO1, GXO2, GXO3 (outputs) Outputs of the transmit input amplifiers of chan- nels 0-3. They are referenced to an internal refer- ence voltage of about 2.4V VRO0, VRO1, VRO2, VRO3 (ouputs) Analog outputs of the receive amplifiers for chan- nels 0-3. They are referenced to an internal refer- ence voltage of about 2.4V PCM Port DX (ouput) Transmit PCM data output. Serial PCM data is shifted out on the rising edge of MCLK during the assigned transmit time-slot. Tristated when the assigned transmit time-slot is not active. TSx (ouput) Open drain output that pulses low during the as- signed transmit time-slots (for all four channels). DR (input) Receive PCM data input. Serial PCM data is shifted into the device on the falling edge of MCLK during the assigned receive time-slot. FSX0, FSR0 (inputs) Transmit and Receive Frame synchronization in- puts for channel 0. They identify the beginning of a new frame in the transmit and receive direction. They are 8 KHz logic signals, and must be syn- chronous to MCLK. Short Frame Sync and Long Frame Sync are both supported. In 32-bit mode these signals constitute the 8kHz reference for all channels. Only Short Frame Sync is supported in 32-bit mode. FSX1, FSR1 (inputs/outputs) Transmit and Receive Frame synchronization in- puts for channel 1. In 32-bit mode these pins become outputs and generate a frame sync signal with the last bit of the 32-bit stream, in order to allow to cascade an- other TP3094 in 32-bit mode. FSX1 is the Trans- mit Frame output and FSR1 is the Receive Frame output. FSX2,FSX3, FSR2,FSR3 (inputs) Transmit and Receive Frame synchronization in- puts for channel 2 and 3. These pins are recom- mended to be connected to analog ground when in 32-bit mode. A/u LAW select (input) A/u law select. Through this pin either A-law (+5V) or u-law (0V) is selected. PDN0-3 (input) Power Down control signals. Each channel has a dedicated Power Down input. When active high, these pins set the low power mode, shutting down most of the circuitry dedicated to it and reducing the power consumption. The relative analog out- puts VROi and GXOi, and the digital output DX are put in high impedance. TST (input) Test Modes Enable. When active (HIGH), togeth- er with the PDNi pins selects one of the available test modes (see the text for a full description of these modes). PCMMode (input) PCM Mode selection. When this signal is LOW (0V), the 8 bit mode is selected and each channel

4 www.national.com expects its individual transmit and receive frame signal. When it is HIGH, the 32 bit mode is select- ed; in this mode FSX0 and FSR0 are used as framing signals and the TS are allocated consec- utively from these frames, starting from Ch0 to Ch3. In this mode FSX1 and FSR1 become out- puts and produce 1 bit long frame signals with the last bit of the 32 bit stream. These Frame signals can be used to cascade another device in 32 bit mode. NF Noise Filter Pin. For optimal noise rejection a 100nF capacitor must be connected between this pin and the analog ground AGND0. PT1, PT2, PT3, PT4 (inputs) These pins are used by National for internal man- ufacturing test. They must be connected to digital ground for normal device operation. NC All NC pins must be connected to nearest analog ground, to reduce the device noise sensitivity. Functional Description The TP3094 performs the complete CODEC/filter functions for four voice channels using a digital signal processing architecture. MCLK provides the clock reference to the whole circuitry and the bit clock for the PCM bus. Its value can be either 8.192MHz, 4.096MHz, 2.048MHz or 1.536/ 1.544MHz, and it is automatically selected inter- nally. The TP3094 handles the conversion be- tween the analog signals on the subscriber line and the PCM data samples on a PCM highway. Digital filters are used to band-limit the voice sig- nals. The device can work in a 8 bit mode where each channel has an independently selected Time Slot, or in the 32 bit mode, where the four chan- nels use four consecutive Time Slots. The time- division multiplexed PCM data is transferred to the PCM highway through the standard serial PCM bus. Each channel has its dedicated Power Down in- put. Power Initialization When power is first applied to the device, power- on reset circuitry initializes the device and places it in the power down state. All non-essential cir- cuits are de-activated. PCM output DX and ana- log outputs VRO 0-3 are placed in the high impedance state, while FSX1 and FSR1 outputs are held low (in case 32-bit mode is selected). In the power down mode, power consumption is re- duced to a minimum, typically 2mW. The device will remain in this state as long as no MCLK is ap- plied and no Frame Signal is applied (just FSX0 and FSR0 in case of 32-bit mode). For each channel, when the PDN input is not ac- tive, MCLK is applied, and a FS (receive or trans- mit) pulse is running, the device enters the active power up mode. The MCLK frequency is detected with any available FS signal; the clock rate detec- tion may last for up to 4ms, after which the device is ready for powering up. Analog and PCM output signals will be available after a few frames; it will take about 100ms until the first activated channel is fully functional. The device will only power up when at least one of the FS signals and the MCLK signal are in a valid frequency ratio. Power Down and Reset When one channel is in Power Down Mode, the DX output will remain in high impedance state and the input on the DR will be ignored when its FS signal is active; the analog output VRO will be in high impedance. Each channel will enter the power down mode when at least one of the following conditions oc- curs

• The PDN signal is active for more than 16 MCLK cycles (and TST is not active at the same time)
• More than 4 pulses of the respective FS are missing.
• MCLK is missing for a 12us. When the PDN input is active (HIGH) for at least

16 MCLK clock cycles, the channel will go into

power down mode and reset its state within a frame sync. The channel will recover from Power Down, after having detected the PDN signal inac- tive (LOW) for at least 16 MCLK clock cycles and after 1 frame sync pulse. This power down mode will work only in presence of the master clock at the pin MCLK. Pin Descriptions (continued)

frame syncs (transmit or receive) will be active. channels will operate after less than 100ms. digital input to the signal processing unit. samples to the PCM interface block. The analog input is dc biased at the value of 2.4V. level, at the op-amp output, is 1.12Vrms. load of 5kOhm+100pF is 1.12Vrms.

• DX, DR - transmit and receive digital signals, carrying the pcm samples
• FSX0-3, FSR0-3 - transmit and receive frame signals
• TSX - output time slots signal, indicating the time slot occupied on the DX by the device
• PCMMode - PCM interface select
• A/uLaw - A-law/ u-law select signal

TABLE 1. A/uLaw Coding

• MCLK - bit clock signal MCLK is both the system master clock and the PCM bus bit clock, and it is selected internally to be either 8.192MHz, 4.096MHz, 2.048MHz, or 1.536/ 1.544MHz. The internal clock selection is perfomed, based on the relative ratio between the frame signals (FS) and the clock signals. For proper functional- ity all the channel FS must have the same valid rate of 8kHz (giving a valid clock rate). In case one of the frame syncs runs other than 8kHz, the device will not function properly. Each bit on DX is clocked out on the rising edges of the bit clock (MCLK), starting from the Most Significant Bit (Sign bit). Each bit on DR is clocked in on the falling edges of the bit clock, starting from the MSB. The device may operate on to the PCM bus in two modes, selected by the input pin PCMMode; when PCMMode is “0V” the 8bit mode is selected and when PCMMode is “+5V” the 32-bit mode is selected. PCMMode = HIGH PCMMode = LOW 32 bit 8 bit A/uLaw = HIGH A/uLaw = LOW A-law u-law

6 www.national.com 8-bit Mode In the 8-bit mode, PCM data is transferred inde- pendently for each of the four channels. Each channel has its dedicated transmit and receive frame signals, which determine the time-slots to be taken on the PCM bus. Both short sync and long sync frame are supported. All the channels must have the same FS format (either short or long sync), in case a channel will have a valid frame with different FS format, the device will not function properly. In the short sync, the frame signals must be one bit long; with FSX high during a falling edge of MCLK, the next rising edge of MCLK enables the DX tristate output buffer, which will output the sign bit. The following 7 rising edges clock out the remaining 7 bits, and the next rising edge (9th) disables the DX output. With FSR high during a falling edge of MCLK, the next falling edge of MCLK latches in the sign bit. The following 7 neg- ative edges of MCLK will then latch the remaining 7 bit of the incoming byte. In the long sync frame, the Frame signals must be at least three bits long. The DX output buffer is enabled with the rising edge of FSX or on the ris- ing edge of MCLK, whichever comes later, and the first bit (sign) is clocked out. The following 7 rising edges of MLCK clock out the remaining 7 bits. The DX output is disabled by the 9th rising edge of MCLK. A rising edge on FSR will cause the PCM data at DR to be latched in on the next falling edges of MCLK. For timing diagrams refer to Fig.2, Fig.4, Fig.5 and Fig.6. 32-bit Mode In the 32-bit mode, the four PCM data bytes of the four channels are treated as a single 32-bit data word. The PCM transfer is started by the positive pulses on the transmit or receive frame sync (FSX0, FSR0) inputs. The following 32 negative edges of MCLK will then latch the input PCM data at DR, for all 4 channel starting from channel 0; while the positive edges will clock out the transmit PCM data at DX, from channel 0 to channel 3. In this mode the pins FSX1 and FSR1 become the frame signal carry-out signals, providing a single- bit-long frame pulse during the last bit of the 32- bit stream and allowing another TP3094 to be connected in 32-bit mode. In case any channel is powered down (through the PDN pin) during its assigned time slot the DX pin will be set in tristate and the DR signal will be ignored. In case all the channels are placed in power down, the device will still generate the FS carry output on FSX1, FSR1. For timing diagrams refer to Fig.7 and Fig.8. Test Modes The TP3094 includes the following test modes

• digital loopback
• analog loopback
• DC conversion These modes can be programmed per channel or for all 4 channels simultaneously. The device is programmed into any test mode by exercising the pins TST, PDN0, PDN1, PDN2, PDN3 together. The signals to this pins must be stable for at least 16 MCLK cycles before the de- vice enters any selected test mode. When exiting the test mode, the PDN must return to the previ- ous state to resume the original operating state. During any test mode (TST=1), it will not be pos- sible to change the PU/PD state for any channel not involved in the test mode configuration (e.g. not in test mode). The channel(s) under test must be placed in power up prior the test mode selec- tion, in case left in power down, any programmed test mode will not be operational. When the device exits the test mode, normal op- eration will return, and the PU/PD programmabil- ity will be available, by the state of the PDN signals. The programming of the test modes is according to the table below. The digital loopback is a bit true feedback from the PCM highway to the PCM highway, per- formed exactly at the PCM internal interface. Each byte is looped back from RX to TX on the programmed time slot (FS). The analog output is forced to 0Vac level (typically 2.4Vdc), with low output impedance. The analog loopback is performed from the out- put of the D/A converter (before the output ampli- fier) and the input of the A/D, so the RX signal is looped back towards the TX direction, through the device. The analog output is at 0Vac level, with high output impedance. In the DC conversion mode, the channel under test is programmed to transfer any DC signal (within the available range) in the TX direction, from the analog GXO to the DX digital output, by Functional Description (continued)

7 www.national.com bypassing the low frequency filter. Where A0, A1 select the channel under test, ac- cording to the following table Test Modes TST PDN0 PDN1 PDN2 PDN3 Description Normal Operation 0 x x x x Single Channel Digital Loopback1 1 1 A0 A1 Ch. select with PDN2, PDN3 Single Channel Analog Loopback 1 0 1 A0 A1 Ch. select with PDN2, PDN3 Single Channel DC Conversion 1 1 0 A0 A1 Ch. select with PDN2, PDN3

4 Channels Digital Loopback 1 0 0 0 0

4 Channels Analog Loopback 1 0 0 0 1

4 Channels DC Conversion 1 0 0 1 0

Functional Description (continued)

11 www.national.com Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Dis- tributors for availability and specifications. V CC to DGND 7V Voltage at any digital inputs or outputs VCC +0.3V to DGND -0.3V Voltage at any analog inputs or outputs VCC +0.3V to AGND-0.3V Storage temperature range -65oC to +150oC Lead temperature(Soldering, 10 Sec) 260oC ESD (human body model) 2000 V Latch-up immunity on any pin 200 mA

Electrical Characteristics

Unless otherwise noted, limits printed in bold characters are guaranteed for VCC (all supplies)=5.0V±5%, DGND=AGND=0V, T A=-40°C to 85°C by correlation with 100% electrical testing at TA=25°C. All other limits are assured by correlation with other production tests and/or product design and characterization. All digital signals are referenced to DGND, and all analog signals are referenced to AGND. Typical are specified at VCC =+5V, TA=25°C. Digital Interface Analog Interface Symbol Parameter Conditions Min Typ Max Units VIL Input low voltage All digital inputs 0.8 V VIH Input high voltage All digital inputs 2.2 V VOL Output low voltage IL=2mA 0.4 V VOH Output high voltage IL=-2mA IL=-100uA 2.4 3.5 V V IIL Input low current DGND<V IN<V IL, all digital inputs-10 10 µA IIH Input high current VIH<V IN<V CC , all digital inputs-10 10 µA IOZ Output current in high impedance state DGND<V O <V CC (DX) -10 10 µA Ci Input Capacitance 10 pF IXI Input leakage current 1V<V XI<4V, all analog inputs in Power UP mode -200 200 nA R XI Input resistance 1V<V XI<4V, all analog inputs 10 M Ω C XI Input capacitance 1V<V XI<4V, all analog inputs 10 pF VCMXI Transmit input common mode voltage range -10% 2.375 +10% V VCMXO Receive input common mode voltage range -10% 2.375 +10% V R RO Output resistance All analog outputs 5 10 Ω R ROZ Output resistance in PDN 2000 Ω RL RO Load resistance 0.7V<VRO <4.1V, VROi 5000 Ω CL RO Load capacitance VRO 100 pF AVXA Voltage Gain VXI to GXO,RL on GXO>10kΩ 5000 V/V FU XA Unity Gain Bandwidth 1 2 MHz RL GXO Load resistance 0.7V<VGX <4.1V, GXOi 10000 Ω CL GXO Load capacitance GXO 50 pF VRO RX output drive level R L=5000Ω 1.12 Vrms

12 www.national.com Power Dissipation Amplitude Response Symbol Parameter Conditions Min Typ Max Units ICC 0 Power down current (all channels down) Measured after having first achieved power-up state. MCLK=2.048MHz 0.9 1.5 mA I CC 1 Power up active current (all channel active) No load, MCLK=2.048MHz 35 50 mA Absolute Levels Nominal 0dBm0 level is 0dBm at the analog inputs/outputs

0.7746 Vrms

tmax Virtual decision value defined per ITU G.711 Max overload level 3.17dBm0 (µ-law) 3.14dBm0 (A-law) 1.116 1.112 Vrms Vrms G XA Transmit gain, absoluteTA=25oC, VCC =5V, Input at VXI=0dBm0 at 1015.625Hz -0.15 0.15 dB G XAT/V Cumulative Transmit gain Variation with sup- plies and temperature ranges T A=0oC to 70oC, VCC =5V ±5% , TA=-40oC to +85oC, VCC =5V ±5% Input at GXO=0dBm0 at 1015.625Hz -0.2 -0.3 0.2 0.3 dB dB G XR Transmit gain, relative to GXA f=16Hz f=50Hz f=60Hz f=200Hz f=300-3000Hz f=3300Hz f=3400Hz f=4000Hz f=4.6KHz and up (Note 2), measure response from 0 to 4000Hz -1.8 -0.15 -0.35 -0.7 -35 -30 -30 0.15 0.15 -14 -32 dB dB dB dB dB dB dB dB dB dB G XAL Transmit gain variation with level Sinusoidal test method, refer- ence level = -10dBm0 at VXI GXO=-40dBm0 to +3dBm0 GXO=-50dBm0 to -40dBm0 GXO=-55dBm0 to -50dBm0 -0.2 -0.4 -1.0 0.2 0.4 1.0 dB dB dB G RA Receive gain, absoluteTA=25oC, VCC =5V ±5% Input PCM level at DR=0dBm0 at 1015.625Hz -0.15 0.15 dB G RAT/V Cumulative Receive gain Variation with supplies and temperature ranges T A=0oC to 70oC, VCC =5V ±5% , TA=-40oC to 85oC, VCC =5V ±5% , Input PCM level at DR=0dBm0 at 1015.625Hz -0.2 -0.3 0.2 0.3 dB G RR Receive gain, relative to G RA f=0-3000Hz f=3300Hz f=3400Hz f=4000Hz -0.15 -0.35 -0.7 0.15 0.15 -14 dB dB dB dB Electrical Characteristics (continued)

13 www.national.com Note 2: Measure voiceband image signal, stimulus signal level is -25dBm0. Distortion G RAL Receive gain variation with level Sinusoidal test method, PCM level=-40dBm0 to +3dBm0 PCM Level=-50dBm0 to -40dBm0 PCM Level=-55dBm0 to -50dBm0 -0.2 -0.4 -1.0 0.2 0.4 1.0 dB dB dB STD XP Transmit signal to total distortion Sinusoidal test method, A-law (psophometric filter), u-Law (C message filter), FSX=FSR, f XI=1015.625Hz GXO=+3dBm0 GXO=0 to -30dBm0 GXO= -40dBm0 GXO= -45dBm0 GXO= -50dBm0 GXO= -55dBm0 dB dB dB dB dB dB SFD X Transmit single fre- quency distortion Sinusoidal test method, PCM code for all channels equals to positive zero, FSX=FSR, f XI=1015.625Hz, GXO=0dBm -46 dB STD RP Receive signal to total distortion Sinusoidal test method, A-law, (psophometric filter), u-Law (C message filter), FSX=FSR, f=1015.625Hz, PCM level=+3dBm0 PCM level=0 to -30dBm0 PCM level=-40dBm0 PCM level=-45dBm0 PCM level=-50dBm0 PCM level= -55dBm0 dB dB dB dB dB SFD R Receive single fre- quency distortion Sinusoidal test method, PCM code for all channels equals to 0dBm0, FSX=FSR, f=1015.625Hz, GXO=0Vrms -46 dB SOS RS Receive spurious out of band signals Single frequency, PCM code for all channels equals 0 dBm0, 300Hz-3.4KHz, FSX=FSR, GXO=0Vrms f=4.6KHz-7.6KHz f=7.6KHz-8.4KHz f=8.4KHz-100KHz -30 -40 -30 dB dB dB Electrical Characteristics (continued) Symbol Parameter Conditions Min Typ Max Units

14 www.national.com Envelope delay distortion Noise Power supply rejection Symbol Parameter Conditions Min Typ Max Units D XA Transmit delay, absolutef=1400Hz, 275 330 µS D XR Transmit delay, relative to DXA GXO=-10dBm0 f=500-600Hz f=600-1000Hz f=1000-2600Hz f=2600-2800Hz 150 220 145 100 140 µs µs µs µs D RA Receive delay, absolutef=1400Hz, 112 220 µS D RR Receive delay, relative to D RA PCM level=-10dBm0 f=500-600Hz f=600-1000Hz f=1000-2600Hz f=2600-2800Hz f=2800-3000Hz -40 -40 -15 -10 105 145 125 175 µs µs µs µs µs N XP Transmit Idle channel noise, A-law Psophometric weighted, PCM code for all channels equals to positive zero, FSX=FSR, GXO=0Vrms -73 -69 dBm0p N XC Transmit Idle channel noise, µ-law C-message weighted, PCM code for all channels equals to alternat- ing positive and negative zeros, FSX=FSR, GXO=0Vrms 12 16 dBrnC0 N RP Receive Idle channel noise, A-law Psophometric weighted, PCM code for all channels equals to positive zero, FSX=FSR, GXO=0Vrms -83 -79 dBm0p N RC Receive Idle channel noise, µ-law C-message weighted, PCM code for all channels equals to alternat- ing positive and negative zeros, FSX=FSR, GXO=0Vrms 7 11 dBrnC0 N XR Analog to Analog NoiseDX connected to DR, f=0-100kHz FSX=FSR, GXO=0Vrms -70 -53 dBm0 PPSR X Positive power supply rejection, transmit PCM code for all channels equals to positive zero, A-law, FSX=FSR, GXO=0Vrms, V CC =5.0V+100mV rms f=0-4000Hz f=4.6KHz-25KHz dB dB PPSR R Positive power supply rejection, receive PCM code for all channels equals to positive zero, A-law, FSX=FSR, GXO=0Vrms, V CC =5.0V+100mV rms f=0-4000Hz f=4.6KHz-25KHz dB dB Electrical Characteristics (continued)

15 www.national.com Crosstalk Symbol Parameter Conditions Min Typ Max Units CT R-X Receive to transmit crosstalk (Intra-channel Crosstalk) PCM code for stimulated channel equals to 0dBm0, 300Hz- 3.4KHz, PCM code for all other channels equals to positive zero, FSX=FSR, Measure PCM response. -80 -75 dB CTFE X Far end crosstalk with analog stimulus (Inter- channel crosstalk) PCM code for all channels equals to positive zero, FSX=FSR, Stimulating signal GXO=0dBm0, f=750Hz All other channels GXO=0V rms -80 -73 dB CTNE X Near end crosstalk with digital stimulus (Inter- channel crosstalk) PCM code for stimulated channel equals to 0dBm0, f=750Hz, PCM code for all other channels equals to positive zero, FSX=FSR, All other channels GXO=0V rms -80 -73 dB CT X-R Transmit to receive crosstalk (Intra-channel crosstalk) PCM code for all channels equals to positive zero, FSX=FSR, Stimulating signal GXO=0dBm0, 300Hz-3.4KHz, all other channels GXO=0V rms, -80 -75 dB CTFE R Far end crosstalk with digital stimulus (Inter- channel crosstalk) PCM code for stimulated channel equals to 0dBm0, f=750Hz, PCM code for all other channels equals to positive zero, FSX=FSR, All other channels GXO=0V rms -80 -76 dB CTNE X Near end crosstalk with analog stimulus (Inter- channel crosstalk) PCM code for all channels equals to positive zero, FSX=FSR, Stimulating signal GXO=0dBm0, f=750Hz All other channels GXO=0V rms -80 -76 dB Electrical Characteristics (continued)

16 www.national.com Timing Specifications Clock and Data Timing All timing parameters are measured at VOH =2.0V and VOL =0.7V Long Frame Timing Note: when measuring signals going to TRI-STATE® , the timing delay is measured when the signal is 10% away from the starting level. Symbol Parameter Conditions Min Typ Max Units 1/tPM Frequency of MCLK 1.536 1.544 2.048 4.096 8.192 MHz MHz MHz MHz MHz DC MCLK MCLK Duty Cycle 40 60 % tRM Rise time of MCLK 10 ns tFM Fall time of MCLK 10 ns tSDB Setup time DR valid to MCLK low 20 ns tHDB Hold time DR valid from MCLK low 20 ns tDBD Delay from MCLK high to DX valid C L=100pF+2LSTTL loads 0 35 ns tDZC Delay from MCLK high to DX disabled C L=100pF+2LSTTL loads 20 ns tTSZC Delay from MCLK high to TSX disabled C L=100pF+2LSTTL loads 20 ns tDBTS Delay time to TS X low C L = 0pF to 150pF 50 ns tPDN PDN persistence 16xtPM tSF Set-up Time from FS to MCLK Low Short Frame Sync Pulse 20 ns tHF Hold Time from MCLK Low to FS Low Short Frame Sync Pulse 20 ns Symbol Parameter Conditions Min Typ Max Units tHBFL Holding time from Clock to Frame Sync Long Frame Only 10 ns tSBF Set-up time from Frame Sync to Clock low Long Frame Only 35 ns t ZDF Delay time Valid Data from FS or MCLK, whichever comes later C L = 0pF to 150pF 50 ns

FIGURE 9. Typical application in a non cascaded mode

FIGURE 10. TP3094 in a cascade mode

TP3094 Q uad PC M C odec/Filter Physical Dimensions inches (millimeters) unless otherwise noted 44-Lead Molded Plastic Chip Carrier (PLCC) Order Number TP3094V LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life sup- port device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or ef- National Semiconductor Corporation Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: (+49) 0-180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National Semiconductor Asia Pacific Customer Response Group Tel: 65-254-4466 Fax: 65-250-4466 Email: sea.support@nsc.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specification.