TP3076 NSC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
Features
n Complete CODEC and Filter system including: — Transmit and receive PCM channel filters — µ-law or A-law companding coder and decoder — Receive power amplifier drives 300Ω — 4.096 MHz serial PCM data (max) n Programmable functions: — Transmit gain: 25.4 dB range, 0.1 dB steps — Receive gain: 25.4 dB range, 0.1 dB steps — Time-slot assignment; to 64 slots/frame — 4 interface latches — A or µ-law — Analog loopback — Digital loopback n Direct interface to solid-state SLICs n Standard serial control interface n 80 mW operating power (typ) n 1.5 mW standby power (typ) n Designed for CCITT and LSSGR specifications n TTL and CMOS compatible digital interfaces Note:See also AN-614 COMBO II application guide. Block Diagram TRI-STATE® and COMBO ® are registered trademarks of National Semiconductor Corporation. MICROWIRE/PLUS ™ is a trademark of National Semiconductor Corporation. DS009758-1 FIGURE 1. April 1994 TP3076 COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications © 1999 National Semiconductor Corporation DS009758 www.national.com
VCC +5V ±5% power supply. VBB −5V ±5% power supply. GND Ground. All analog and digital signals are referenced to this pin. FS X Transmit Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the transmit time slot assigned to this device (non-delayed data timing mode), or the start of the transmit frame (delayed data timing mode using the internal time-slot assignment counter). FS R Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the receive time slot assigned to this device (non-delayed data timing mode), or the start of the receive frame (delayed data timing mode using the internal time-slot assignment counter). BCLK Bit clock input used to shift PCM data into and out of the D R and DX pins. BCLK may vary from 64 kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK. MCLK Master clock input used by the switched capacitor filters and the encoder and decoder sequencing logic. Must be 512 kHz, 1.536/1.544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK. VF XI The Transmit analog high-impedance input. Voice frequency signals present on this input are encoded as an A-law or µ-law PCM bit stream and shifted out on the selected D X pin. VF R O The Receive analog power amplifier output, capable of driving load impedances as low as 300Ω (depending on the peak overload level required). PCM data received on the assigned D R pin is decoded and appears at this output as voice frequency signals. Pin Description D X1 This transmit data TRI-STATE® output remains in the high impedance state except during the assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted out on the rising edges of BCLK. TS X1 Normally this open drain output is floating in a high impedance state except when a time-slot is active on the D X output, when the TSX1 output pulls low to enable a backplane line-driver. D R 1 This receive data input is inactive except during the assigned receive time slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK. CCLK Control Clock input. This clock shifts serial control information into CI or out from CO when the CS input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. CI Control Data Input pin. Serial control information is shifted into COMBO II on this pin when CS is low. Byte 1 of control information is always written into COMBO II, while the direction of byte 2 data is determined by bit 2 of byte 1, as defined in Table 1. CO Control Data Output pin. Serial control or status information is shifted out of COMBO II on this pin when CS is low. CS Chip Select input. When this pin is low, control information can be written to or read from COMBO II via CI or CO. IL3–IL0 Each Interface Latch I/O pin may be individually programmed as an input or an output determined by the state of the corresponding bit in the Latch Direction Register (LDR). For pins configured as inputs, the logic state sensed on each input is latched into the Interface Latch Register (ILR) whenever control data is written to COMBO II, while CS is low, and the information is shifted out on the CO pin. When configured as outputs, control data written into the ILR appears at the corresponding IL pins. Functional Description POWER-ON INITIALIZATION When power is first applied, power-on reset circuitry initial- izes the COMBO II and puts it into the power-down state. The gain control registers for the transmit and receive gain sections are programmed for no output, the power amp is disabled and the device is in the non-delayed timing mode. The Latch Direction Register (LDR) is pre-set with all IL pins programmed as inputs, placing the SLIC interface pins in a high impedance state. The CO pin is in TRI-STATE condi- tion. Other initial states in the Control Register are indicated in Section 2.0. DS009758-4 Order Number TP3076J See NS Package Number J20A www.national.com 2
initialized via the control port prior to a Power-up command. Table 1. It is recommended that the ability to monitor and control the SLIC. XI, is a high impedance input. canceled by an internal auto-zero circuit. lected time slot on eight rising edges of BCLK. ±3.8V or a 15 kΩ load to±4.0V at peak overload. TABLE 1. Programmable Register Instructions Note 1:Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI or CO pin. X= don’t care. Note 3:Other register address codes are invalid and should not be used. ning of the 8-bit transmit and receive time-slots respectively.
time-slot in a frame is identified by the appropriate FS input. mined by the internal Time-Slot Assignment counters. Receive time-slot on the falling edges of BCLK. struction; and bit 0 is not used. Table 1. CS must be many devices to be multiplexed together. byte count are reset and register contents are not affected. single byte instruction, bit one (1) must be reset to a 0. TABLE 2. Control Register Byte 2 Functions
76543210 Function
0 X Select µ255 Law (Note 4)
0 Delay Data Timing
1 Non-Delayed
1 X Digital Loopback
0 Power Amp
1 Power Amp
Note 4:state at power-on initialization. ization to select the correct internal divider.
coding or A-law coding, with or without even bit inversion. that overload levels are not exceeded anywhere in the loop. Table 2. This always be programmed as “1” (outputs). TABLE 3. Byte 2 Functions of Latch Direction Register
0 Input
1 Output
Off-Hook detect output of a SLIC. All bits of the ILR, i.e. read back in the 2nd byte of a READ from the ILR. followed immediately by the Latch Direction Register. TABLE 4. Interface Latch Data Bit Order TABLE 5. Coding Law Conventions Note 5:The MSB is always the first PCM bit shifted in or out of COMBO II.
TABLE 6. Time-Slot and Port Assignment Instruction Note 6:The “PS” bit MUST be set to “1” for both transmit and receive for the TP3076. D X1, as appropriate, to be enabled or disabled. On the TP3076, the “PS” bit MUST always be set to 1. mit and receive time-slot and port assignment instructions. AN-614 for more information on this subject. TABLE 7. Byte 2 of Transmit Gain Instruction
00000000 N o Output (Note 8)
codes representing idle noise. Table 8. Note the following restrictions on output drive capa-
- 0 dBm0 levels≤ 1.96 Vrms at VFR O may be driven into
- 0 dBm0 levels≤ 1.85 Vrms at VFR O may be driven into
a load of≥ 600Ω to GND; Receive Gain set to 0.5 dB.
- 0 dBm0 levels≤ 1.71 Vrms at VFR O may be driven into
a load of≥ 300 Ω to GND. Receive Gain set to −1.2 dB.
TABLE 8. Byte 2 of Receive Gain Instruction
00000000 N o Output (Low Z to GND)
return currents flowing through a common bus impedance. to the device pins as possible. CODEC/Filter Family Application Guide”.
Note 9: Primo type EM80–PMI2 or similar. Note 10: Primo type DH31 or similar. Sidetone≅ −21.5 dB for 1200Ω . FIGURE 2. Typical Application in an ISDN Phone
Absolute Maximum Ratings(Note 12) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V CC to GND 7V Voltage at VFXIV CC +0.5V to VBB −0.5V Voltage at Any Digital Input VCC +0.5V to GND −0.5V Storage Temperature Range −65˚C to +150˚C VBB to GND −7V Current at VFR 0 ±100 mA Current at Any Digital Output ±50 mA Lead Temperature (Soldering, 10 sec.) 300˚C
Electrical Characteristics
Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACES V IL Input Low Voltage All Digital Inputs (DC Meas.) 0.7 V VIH Input High Voltage All Digital Inputs (DC Meas.) (Note 13) 2.0 V VOL Output Low Voltage D X1, TSX1, and CO, IL = 3.2 mA, 0.4 V All Other Digital Outputs, IL = 1m A VOH Output High Voltage D X1 and CO, IL = −3.2 mA, 2.4 V All Other Digital Outputs (except TSX), IL = −1 mA All Digital Outputs, IL = −100 µA V CC − 0.5 V IIL Input Low Current Any Digital Input, GND < VIN < VIL −10 10 µA IIH Input High Current Any Digital Input, except MR, VIH < VIN < VCC −10 10 µA MR Only −10 100 IOZ Output Current in D X1, TSX1 and CO High Impedance IL3–IL0 when Selected as Inputs −10 10 µA State (TRI-STATE ) GND < VOUT < VCC ANALOG INTERFACES I VFXI Input Current, VFXI −3.3V < VF XI< 3.3V −1.0 1.0 µA R VFXI Input Resistance −3.3V < VF XI< 3.3V 1.0 M Ω VOS X Input Offset Voltage Transmit Gain= 0 dB 200 mV Applied at VFXI Transmit Gain = 25.40 dB 10 mV RL VFRO Load Resistance Receive Gain = 0 dB 15k Receive Gain= −0.5 dB 600 Ω Receive Gain= −1.2 dB 300 CL VFRO Load Capacitance RL VFRO ≥ 300Ω 200 pF CL VFRO from VFR Ot oG N D RO VFRO Output Resistance Steady Zero PCM Code Applied to D R 1 1.0 3.0 Ω VOS R Output Offset Voltage Alternating± Zero PCM Code Applied −200 200 mV at VFRO D R 1, Maximum Receive Gain POWER DISSIPATION I CC 0 Power Down Current CCLK, CI, CO = 0.4V, CS= 2.4V Interface Latches Set as Outputs with No Load, 0.1 0.6 mA All Other Inputs Active, Power Amp Disabled IBB 0 Power Down Current As Above −0.1 −0.3 mA ICC 1 Power Up Current CCLK, CI, CO = 0.4V, CS= 2.4V No Load on Power Amp 8.0 11.0 mA Interface Latches Set as Outputs with No Load IBB 1 Power Up Current As Above −8.0 −11.0 mA ICC 2 Power Down Current As Above, Power Amp Enabled 2.0 3.0 mA IBB 2 Power Down Current As Above, Power Amp Enabled −2.0 −3.0 mA Note 12:“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. www.national.com9
Electrical Characteristics(Continued) Note 13:See definitions and timing conventions section. Timing Specifications Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ;V BB = −5V ±5% ;TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units MASTER CLOCK TIMING f MCLK Frequency of MCLK Selection of Frequency is Programmable 512 kHz (See Table 5) 1536 kHz 1544 kHz 2048 kHz 4096 kHz t WMH Period of MCLK High Measured from V IH to VIH (Note 14) 80 ns tWML Period of MCLK Low Measured from V IL to VIL (Note 14) 80 ns tRM Rise Time of MCLK Measured from V IL to VIH 30 ns tFM Fall Time of MCLK Measured from V IH to VIL 30 ns tHBM HOLD Time, BCLK LOW 50 ns to MCLK HIGH tWFL Period of FSX Measured from VIL to VIL 1 MCLK or FSR Low Period PCM INTERFACE TIMING f BCLK Frequency of BCLK May Vary from 64 kHz to 4096 kHz 64 4096 kHz in 8 kHz Increments tWBH Period of BCLK High Measured from V IH to VIH 80 ns tWBL Period of BCLK Low Measured from V IL to VIL 80 ns tRB Rise Time of BCLK Measured from V IL to VIH 30 ns tFB Fall Time of BCLK Measured from V IH to VIL 30 ns tHBF Hold Time, BCLK Low 30 ns to FSX/R High or Low tSFB Setup Time, FSX/R 30 ns High to BCLK Low tDBD Delay Time, BCLK High Load = 100 pF Plus 2 LSTTL Loads 80 ns to Data Valid tDBZ Delay Time, BCLK Low to DX1D X1 disabled is measured Disabled if FSX Low, FSX Low to at V OL or VOH according D X1 disabled if 8th BCLK to Figure 5 15 80 ns Low, or BCLK High to DX1 Disabled if FSX High tDBT Delay Time, BCLK High to Load = 100 pF Plus 2 LSTTL Loads TS X Low if FSX High, or 60 ns FS X High to TSX Low if BCLK High (Nondelayed mode); BCLK High to TS X Low (delayed data mode) tZBT TRI-STATE Time, BCLK Low to TS X High if FSX Low, FSX Low to TSX High if 8th BCLK Low, or 15 60 ns BCLK High to TSX High if FSX High tDFD Delay Time, FSX/R Load = 100 pF Plus 2 LSTTL Loads, www.national.com 10
Timing Specifications(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ;V BB = −5V ±5% ;TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at VCC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units PCM INTERFACE TIMING High to Data Valid Applies if FS X/R Rises Later Than 80 ns BCLK Rising Edge in Non-Delayed Data Mode Only t SDB Setup Time, DR 1 30 ns Valid to BCLK Low tHBD Hold Time, BCLK 15 ns Low to DR 1 Invalid SERIAL CONTROL PORT TIMING f CCLK Frequency of CCLK 2048 kHz tWCH Period of CCLK High Measured from V IH to VIH 160 ns tWCL Period of CCLK Low Measured from V IL to VIH 160 ns tRC Rise Time of CCLK Measured from V IL to VIH 50 ns tFC Fall Time of CCLK Measured of V IH to VIL 50 ns tHCS Hold Time, CCLK Low CCLK1 10 ns to CS Low tHSC Hold Time, CCLK CCLK8 100 ns Low to CS High tSSC Setup Time, CS 60 ns Transition to CCLK Low tSSC0 Setup Time, CS To Insure CO is Not Enabled 60 ns Transition to CCLK High for Single Byte tSDC Setup Time, CI 50 ns Data In to CCLK Low tHCD Hold Time, CCLK 50 ns Low to CO Invalid t DCD Delay Time, CCLK High Load = 100 pF Plus 2 LSTTL Loads 80 ns to CO Data Out Valid tDSD Delay Time, CS Low Applies Only if Separate 80 ns to CO Valid CS Used for Byte 2 tDDZ Delay Time, CS or 9th CCLK Applies to Earlier of CS 15 80 ns High to CO High Impedance High or 9th CCLK High INTERFACE LATCH TIMING t SLC Setup Time, IL to Interface Latch Inputs Only 100 ns CCLK 8 of Byte 1 tHCL Hold Tme, IL Valid from 50 ns 8th CCLK Low (Byte 1) t DCL Delay Time CCLK8 of Interface Latch Outputs Only 200 ns B y t e2t oI L C L = 50 pF Note 14:Applies only to MCLK Frequencies≥ 1.536 MHz. At 512 kHz a 50:50±2% Duty Cycle must be used. www.national.com11
FIGURE 5. Control Port Timing
Transmission Characteristics Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. f= 1015.625 Hz, VFXI= 0 dBm0, DR 1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correla- tion with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE Absolute Levels The Maximum 0 dBm0 Levels Are: VF XI 1.375 Vrms VF R O (15 kΩ Load) 1.964 Vrms The Minimum 0 dBm0 Levels are: VF XI 73.8 mVrms VF R O (Any Load≥ 300Ω ) 105.0 mVrms G XA Transmit Gain Transmit Gain Programmed for Maximum Absolute Accuracy 0 dBm0 Test Level. Measure Deviation of Digital Code from Ideal 0 dBm0 PCM Code at D X1. TA = 25˚C −0.15 0.15 dB G XAG Transmit Gain T A = 25˚C, VCC = 5V, VBB = 5V Variation with Programmed Gain from 0 dB to 19 dB Programmed Gain (0 dBm0 Levels of 1.619 Vrms to 0.182 Vrms) −0.1 0.1 dB Programmed Gain from 19.1 dB to 25.4 dB (0 dBm0 Levels of 0.180 Vrms to 0.087 Vrms)−0.3 0.3 dB Note:±0.1 dB Min/Max is Available as a Selected Part G XAF Transmit Gain Relative to 1015.625 Hz, (Note 18) Variation with Minimum Gain < G X < Maximum Gain Frequency f = 60 Hz −26 dB f= 200 Hz −1.8 −0.1 dB f= 300 Hz to 3000 Hz −0.15 0.15 dB f= 3400 Hz −0.7 0.0 dB f= 400 Hz −14 dB f≥ 4600 Hz. Measure Response −32 dB at Alias Frequency from 0 kHz to 4 kHz G X = 0.0 dB, VFXI= 1.375 Vrms Relative to 1015.625 Hz f= 62.5 Hz −24.9 dB f= 203.125 Hz −1.7 −0.1 dB f= 343.75 Hz −0.15 0.15 dB f= 515.625 Hz −0.15 0.15 dB f= 2140.625 Hz −0.15 0.15 dB f= 3156.25 Hz −0.15 0.15 dB f= 3406.250 Hz −0.74 0.0 dB f= 3984.375 Hz −13.5 dB Relative to 1062.5 Hz (Note 18) f= 5250 Hz, Measure 2750 Hz −32 dB f= 11750 Hz, Measure 3750 Hz −32 dB f= 49750 Hz, Measure 1750 Hz −32 dB G XAT Transmit Gain Measured Relative to G XA ,V CC = 5V, Variation with V BB = −5V, −0.1 0.1 dB Temperature Minimum gain < G X < Maximum Gain www.national.com 14
Transmission Characteristics(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. f= 1015.625 Hz, VFXI= 0 dBm0, DR 1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correla- tion with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE G XAL Transmit Gain Sinusoidal Test Method. Variation with Reference Level = 0 dBm0 Signal Level VF XI= −40 dBm0 to +3 dBm0 −0.2 0.2 dB VF XI= −50 dBm0 to −40 dBm0 −0.4 0.4 dB VF XI= −55 dBm0 to −50 dBm0 −1.2 1.2 dB G RA Receive Gain Receive Gain Programmed for Maximum Absolute Accuracy 0 dBm0 Test Level. Apply 0 dBm0 −0.15 0.15 dB PCM Code to D R 1. Measure VFR 0. TA = 25˚C G RAG Receive Gain T A = 25˚C, VCC = 5V, VBB = −5V Variation with Programmed Gain from 0 dB to 19 dB Programmed Gain (0 dBm0 Levels of 1.964 Vrms to 0.220 Vrms) −0.1 0.1 dB Programmed Gain from 19.1 dB to 25.4 dB (0 dBm0 Levels of 0.218 Vrms to 0.105 Vrms)−0.3 0.3 dB Note:±0.1 dB Min/Max is Available as a Selected Part G RAT Receive Gain Measured Relative to G RA . Variation with V CC = 5V, VBB = −5V. −0.1 0.1 dB Temperature Minimum Gain < G R < Maximum Gain G RAF Receive Gain Relative to 1015.625 Hz, (Note 18) Variation with D R 1 = 0 dBm0 Code. Frequency Minimum Gain < G R < Maximum Gain f= 200 Hz −0.25 0.15 dB f= 300 Hz to 3000 Hz −0.15 0.15 dB f= 3400 Hz −0.7 0.0 dB f= 4000 Hz −14 dB G R = 0 dB, DR 1 = 0 dBm0 Code, G X = 0 dB (Note 18) f= 296.875 Hz −0.15 0.15 dB f= 1875.00 Hz −0.15 0.15 dB f= 2906.25 Hz −0.15 0.15 dB f= 2984.375 Hz −0.15 0.15 dB f= 3406.250 Hz −0.74 0.0 dB f= 3984.375 Hz −13.5 dB G RAL Receive Gain Sinusoidal Test Method. Variation with Reference Level = 0 dBm0. Signal Level D R 1 = −40 dBm0 to +3 dBm0 −0.2 0.2 dB D R 1 = −50 dBm0 to −40 dBm0 −0.4 0.4 dB D R 1 = −55 dBm0 to −50 dBm0 −1.2 1.2 dB DR 1 = 3.1 dBm0 −0.5 R L = 600Ω ,G R = −0.5 dB −0.2 0.2 dB R L = 300Ω ,G R = 1.2 dB −0.2 0.2 dB ENVELOPE DELAY DISTORTION WITH FREQUENCY D XA Tx Delay, Absolute f = 1600 Hz 315 µs www.national.com15
Transmission Characteristics(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. f= 1015.625 Hz, VFXI= 0 dBm0, DR 1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correla- tion with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units ENVELOPE DELAY DISTORTION WITH FREQUENCY D XR Tx Delay, Relative to DXA f = 500 Hz–600 Hz 220 µs f= 600 Hz–800 Hz 145 µs f= 800 Hz–1000 Hz 75 µs f= 1000 Hz–1600 Hz 40 µs f= 1600 Hz–2600 Hz 75 µs f= 2600 Hz–2800 Hz 105 µs f= 2800 Hz–3000 Hz 155 µs D RA Rx Delay, Absolute f = 1600 Hz 200 µs D RR Rx Delay, Relative to DRA f = 500 Hz–1000 Hz −40 µs f= 1000 Hz–1600 Hz −30 µs f= 1600 Hz–2600 Hz 90 µs f= 2600 Hz–2800 Hz 125 µs f= 2800 Hz–3000 Hz 175 µs NOISE N XC Transmit Noise, C Message (Note 15) 11111111 12 15 dBrnC0 Weighted, µ-Law Selected in Gain Register N XP Transmit Noise, P Message (Note 15) 11111111 −74 −67 dBm0p Weighted, A-Law Selected in Gain Register N RC Receive Noise, C Message PCM Code is Alternating Positive 8 11 dBrnC0 Weighted, µ-Law Selected N RP Receive Noise, P Message PCM Code Equals Positive Zero −82 −79 dBm0p Weighted, A-Law Selected N RS Noise, Single Frequency f = 0 kHz to 100 kHz, Loop Around −53 dBm0 Measurement, VFXI= 0 Vrms PPSR X Positive Power Supply V CC = 5.0 VDC + 100 mVrms Rejection, Transmit f = 0 kHz–4 kHz (Note 16) 36 dBC f= 4 kHz–50 kHz 30 dBC NPSR X Negative Power Supply V BB = −5.0 VDC +100 mVrms Rejection, Transmit f = 0 kHz–4 kHz (Note 16) 36 dBC f= 4 kHz–50 kHz 30 dBC PPSR R Positive Power Supply PCM Code Equals Positive Zero Rejection, Receive V CC = 5.0 VDC + 100 mVrms Measure VFR O f= 0 Hz–4000 Hz 36 dBC f= 4 kHz–25 kHz 40 dB f= 25 kHz–50 kHz 36 dB NPSR R Negative Power Supply PCM Code Equals Positive Zero Rejection, Receive V BB = −5.0 VDC + 100 mVrms Measure VFR O f= 0 Hz–4000 Hz 36 dBC f= 4 kHz–25 kHz 40 dB f= 25 kHz–50 kHz 36 dB www.national.com 16
Transmission Characteristics(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C by correlation with 100% electrical testing at TA = 25˚C. f= 1015.625 Hz, VFXI= 0 dBm0, DR 1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB Gain). All other limits are assured by correla- tion with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units NOISE SOS Spurous Out-of-Band 0 dBm0 300 Hz to 3400 Hz Input PCM Code Signals Applied at the at D R 1 Channel Output 4600 Hz–7600 Hz −30 dB
7600 Hz–8400 Hz −40 dB
8400 Hz–50,000 Hz −30 dB
X Signal to Total Distortion Sinusoidal Test Method STD R Transmit or Receive Level = 3.0 dBm0 33 dBC Half-Channel, µ-Law = 0 dBm0 to −30 dBm0 36 dBC Selected = −40 dBm0 30 dBC = −45 dBm0 25 dBC STD RL Single to Total Distortion Sinusoidal Test Method Receive with Resistive Level = +3.1 dBm0 Load R L = 600Ω ,G R = −0.5 dB 33 dBC R L = 300Ω ,G R = −1.2 dB 33 dBC SFD X Single Frequency −46 dB Distortion, Transmit SFD R Single Frequency −46 dB Distortion, Receive IMD Intermodulation Distortion Transmit or Receive Two Frequencies in the Range −41 dB
300 Hz–3400 Hz
X-R Transmit to Receive Crosstalk, f= 300 Hz–3400 Hz −90 −75 dB 0 dBm0 Transmit Level D R = Idle Code CT R-X Receive to Transmit Crosstalk, f= 300 Hz–3400 Hz −90 −70 dB 0 dBm0 Receive Level (Note 16) Note 15:Measured by grounded input at VFXI. Note 16:PPSR X, NPSRX, and CTR-X are measured with a −50 dBm0 activation signal applied to VFXI. Note 17:A signal is Valid if it is above VIHor below VILand Invalid if it is between VILand VIH. For the purposes of this specification the following conditions apply: a) All input signals are defined as: VIL = 0.4V, VIH = 2.7V, tR < 10 ns, tF < 10 ns. b) tR is measured from VILto VIH.tF is measured from VIH to VIL. c) Delay Times are measured from the input signal Valid to the output signal Valid. d) Setup Times are measured from the data input Valid to the clock input Invalid. e) Hold Times are measured from the clock signal Valid to the data input Invalid. f) Pulse widths are measured from V ILto VILor from VIH to VIH. Note 18:A multi-tone test technique is used. www.national.com17
Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Ceramic Dual-In-Line Package (J) Order Number TP3076J TP3076 COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.