TP3070V-X

TP3070 NSC | Alldatasheet

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n Complete CODEC and FILTER system including: — Transmit and receive PCM channel filters — µ-law or A-law companding encoder and decoder — Receive power amplifier drives 300Ω — 4.096 MHz serial PCM data (max) n Programmable Functions: — Transmit gain: 25.4 dB range, 0.1 dB steps — Receive gain: 25.4 dB range, 0.1 dB steps — Hybrid balance cancellation filter — Time-slot assignment; up to 64 slots/frame — 2 port assignment (TP3070) — 6 interface latches (TP3070) — A or µ-law — Analog loopback — Digital loopback n Direct interface to solid-state SLICs n Simplifies transformer SLIC; single winding secondary n Standard serial control interface n 80 mW operating power (typ) n 1.5 mW standby power (typ) n Designed for CCITT and LSSGR applications n TTL and CMOS compatible digital interfaces n Extended temperature versions available for −40˚C to +85˚C (TP3070V-X) Note:See also AN-614, COMBO II application guide. COMBO ® and TRI-STATE® are registered trademarks of National Semiconductor Corporation. April 1994 TP3070, TP3071, TP3070-X COMBO II Programmable PCM CODEC/Filter © 1999 National Semiconductor Corporation DS008635 www.national.com

VCC +5V ±5% power supply. VBB −5V ±5% power supply. GND Ground. All analog and digital signals are referenced to this pin. FS X Transmit Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the transmit time slot assigned to this device (non-delayed data timing mode), or the start of the transmit frame (delayed data timing mode using the internal time-slot assignment counter). DS008635-1 FIGURE 1. DS008635-4 Order Number TP3070V (0˚C to +70˚C) Order Number TP3070V-X (−40˚C to +85˚C) See NS Package Number V28A DS008635-2 Order Number TP3071J See NS Package Number J20A Order Number TP3071N See NS Package Number N20A www.national.com 2

Pin Descriptions(Continued) Pin Description FS R Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to this input to define the start of the receive time slot assigned to this device (non-delayed data timing mode), or the start of the receive frame (delayed data timing mode using the internal time-slot assignment counter). BCLK Bit clock input used to shift PCM data into and out of the D R and DX pins. BCLK may vary from 64 kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK. MCLK Master clock input used by the switched capacitor filters and the encoder and decoder sequencing logic. Must be 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK. VF XI The Transmit analog high-impedance input. Voice frequency signals present on this input are encoded as an A-law or µ-law PCM bit stream and shifted out on the selected D X pin. VF R O The Receive analog power amplifier output, capable of driving load impedances as low as 300Ω (depending on the peak overload level required). PCM data received on the assigned D R pin is decoded and appears at this output as voice frequency signals. D X0 D X1 D X1 is available on the TP3070 only; DX0i s available on all devices. These Transmit Data TRI-STATE ® outputs remain in the high impedance state except during the assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted out on the rising edges of BCLK. TS TS X1 TS X1 is available on the TP3070 only; TSX0i s available on all devices. Normally these open-drain outputs are floating in a high impedance state except when a time-slot is active on one of the D X outputs, when the appropriate TSX output pulls low to enable a backplane line-driver. D R 0 D R 1 D R 1 is available on the TP3070 only; DR 0i s available on all devices. These receive data inputs are inactive except during the assigned receive time slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK. CCLK Control Clock input. This clock shifts serial control information into or out from CI/O or CI and CO when the CS input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. Pin Description CI/O This is the Control Data I/O pin which is provided on the TP3071. Serial control information is shifted to or read from COMBO II on this pin when CS is low. The direction of the data is determined by the current instruction as defined in Table 1. CI This is a separate Control Input, available only on the TP3070. It can be connected to CO if required. CO This is a separate Control Output, available only on the TP3070. It can be connected to CI if required. CS Chip Select input. When this pin is low, control information can be written to or read from COMBO II via the CI/O pin (or CI and CO). IL5–IL0 IL5 through IL0 are available on the TP3070. IL4 through IL0 are available on the TP3071. Each Interface Latch I/O pin may be individually programmed as an input or an output determined by the state of the corresponding bit in the Latch Direction Register (LDR). For pins configured as inputs, the logic state sensed on each input is latched into the Interface Latch Register (ILR) whenever control data is written to COMBO II, while CS is low, and the information is shifted out on the CO (or CI/O) pin. When configured as outputs, control data written into the ILR appears at the corresponding IL pins. MR This logic input must be pulled low for normal operation of COMBO II. When pulled momentarily high (at least 1 µsec.), all programmable registers in the device are reset to the states specified under “Power-On Initialization”. NC No Connection. Do not connect to this pin. Do not route traces through this pin. Functional Description POWER-ON INITIALIZATION When power is first applied, power-on reset circuitry initial- izes the COMBO II and puts it into the power-down state. The gain control registers for the transmit and receive gain sections are programmed to OFF (00000000), the hybrid balance circuit is turned off, the power amp is disabled and the device is in the non-delayed timing mode. The Latch Di- rection Register (LDR) is pre-set with all IL pins programmed as inputs, placing the SLIC interface pins in a high imped- ance state. The CI/O pin is set as an input ready for the first control byte of the initialization sequence. Other initial states in the Control Register are indicated in Section 2.0. A reset to these same initial conditions may also be forced by driving the MR pin momentarily high. This may be done ei- ther when powered-up or down. For normal operation this pin must be pulled low. If not used, MR should be hard-wired to ground. The desired modes for all programmable functions may be initialized via the control port prior to a Power-up command. www.national.com3

Table 1. It is recommended that the impedance TRI-STATE condition. an internal auto-zero circuit. the selected time slot on eight rising edges of BCLK. load to±3.8V or a 15 kΩ load to±4.0V at peak overload. ning of the 8-bit transmit and receive time-slots respectively. time-slot in a frame is identified by the appropriate FS input. mined by the internal Time-Slot Assignment counters. data out from the PCM register on the rising edges of BCLK. are selectable on the TP3070 only, see Section 6.

TABLE 1. Programmable Register Instructions Note 1:Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI, CO or CI/O pin. X= don’t care. Note 3:Other register address codes are invalid and should not be used. struction; and bit 0 is not used. pins of many devices to be multiplexed together. byte count are reset and register contents are not affected.

1.0 POWER-UP/DOWN CONTROL

single byte instruction, bit one (1) must be reset to a 0. ond FSX pulse after power-up.

2.0 CONTROL REGISTER INSTRUCTION

TABLE 2. Control Register Byte 2 Functions

0 X Select µ-255 law (Note 4)

0 Delayed Data Timing

1 Non-Delayed Data

1 X Digital Loopback

0 Power Amp Enabled in PDN

1 Power Amp Disabled in

2.1 Master Clock Frequency Selection

ization to select the correct internal divider.

2.2 Coding Law Selection

coding or A-law coding, with or without even bit inversion.

2.3 Analog Loopback

that overload levels are not exceeded anywhere in the loop.

2.4 Digital Loopback

Table 2. This

3.0 INTERFACE LATCH DIRECTIONS

TABLE 3. Byte 2 Functions of Latch Direction Register

0 Input

1 Output

Off-Hook detect output of a SLIC. All bits of the ILR, i.e. read back in the 2nd byte of a READ from the ILR. followed immediately by the Latch Direction Register. TABLE 4. Interface Latch Data Bit Order

TABLE 5. Coding Law Conventions Note 5:The MSB is always the first PCM bit shifted in or out of COMBO II. TABLE 6. Time-Slot and Port Assignment Instruction Note 6:The “PS” bit MUST always be set to 0 for the TP3071.

5.0 TIME-SLOT ASSIGNMENT

puts, DX0/1, as appropriate, to be enabled or disabled.

6.0 PORT SELECTION

ports cannot be active at the same time. fore the “PS” bit MUST always be set to 0 for these devices. mit and receive time-slot and port assignment instructions.

7.0 TRANSMIT GAIN INSTRUCTION BYTE 2

AN-614 for more information on this subject. TABLE 7. Byte 2 of Transmit Gain Instruction

00000000 N o Output (Note 8)

codes representing idle noise.

8.0 RECEIVE GAIN INSTRUCTION BYTE 2

Table 8. Note the following restrictions on output drive capa- TABLE 8. Byte 2 of Receive Gain Instruction

00000000 N o Output (Low Z to GND)

9.0 HYBRID BALANCE FILTER

to higher audio frequency signals. should be de-selected to bypass it. mid and high-band frequencies, typically 1 kHz to 3.4 kHz.

9.1 PROGRAMMING THE FILTER

path be modeled and the hybrid balance filter programmed. conversion back to analog by a PCM CODEC/Filter.

FIGURE 3. Typical Application with Monolithic SLIC

Absolute Maximum Ratings(Note 9) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V CC to GND 7V Voltage at VFXIV CC + 0.5V to VBB − 0.5V Voltage at any Digital Input VCC + 0.5V to GND − 0.5V Storage Temperature Range −65˚C to + 150˚C VBB to GND −7V Current at VFR 0 ±100 mA Current at any Digital Output ±50 mA Lead Temperature (Soldering, 10 sec.) 300˚C

Electrical Characteristics

Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACES V IL Input Low Voltage All Digital Inputs (DC Meas.) (Note 10) 0.7 V VIH Input High Voltage All Digital Inputs (DC Meas.) (Note 10) 2.0 V VOL Output Low Voltage D X0, DX1, TSX0, TSX1 and CO, IL = 3.2 mA, 0.4 V All Other Digital Outputs, IL = 1m A VOH Output High Voltage D X0, DX1 and CO, IL = −3.2 mA, 2.4 V All Other Digital Outputs (except TSX), IL = −1 mA All Digital Outputs, IL = −100 µA V CC − 0.5 V IIL Input Low Current Any Digital Input, GND< VIN < VIL −10 10 µA IIH Input High Current Any Digital Input except MR, VIH < VIN < VCC −10 10 µA MR Only −10 100 µA IOZ Output Current in D X0, DX1, TSX0, TSX1, CO and CI/O (as an Output) High Impedance IL5–IL0 When Selected as Inputs −10 10 µA State (TRI-STATE) GND < VOUT < VCC −40˚C to +85˚C (TP3070-X) −30 30 µA ANALOG INTERFACES I VFXI Input Current, VFXI −3.3V < VF XI< 3.3V −10.0 10.0 µA R VFXI Input Resistance −3.3V < VF XI< 3.3V 390 620 k Ω VOS X Input Offset Voltage Transmit Gain= 0 dB 200 mV Applied at VFXI Transmit Gain = 25.4 dB 10 mV RL VFRO Load Resistance Receive Gain = 0 dB 15k Receive Gain= −0.5 dB 600 Ω Receive Gain= −1.2 dB 300 CL VFRO Load Capacitance RL VFRO ≥ 300Ω 200 pF CL VFRO from VFR Ot oG N D RO VFRO Output Resistance Steady Zero PCM Code Applied to 1.0 3.0 Ω D R 0o rDR 1 VOS R Output Offset Alternating ± Zero PCM Code Applied to −200 200 mV Voltage at VFRO D R 0o rDR 1, Maximum Receive Gain POWER DISSIPATION I CC 0 Power Down Current CCLK, CI/O, CI, CO, = 0.4V, CS= 2.4V Interface Latches Set as Outputs with No Load, 0.1 0.6 mA All Other Inputs Active, Power Amp Disabled IBB 0 Power Down Current As Above −0.1 −0.3 mA −40˚C to +85˚C (TP3070-X) −0.4 mA ICC 1 Power Up Current CCLK, CI/O, CI, CO = 0.4V, CS= 2.4V No Load on Power Amp 8.0 11.0 mA Interface Latches Set as Outputs with No Load −40˚C to +85˚C (TP3070-X) 13.0 mA www.national.com11

Electrical Characteristics(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units POWER DISSIPATION I BB 1 Power Up Current As Above −8.0 −11.0 mA −40˚C to +85˚C (TP3070-X) −13.0 mA ICC 2 Power Down Current Power Amp Enabled 2.0 3.0 mA −40˚C to +85˚C (TP3070-X) 4.0 mA IBB 2 Power Down Current Power Amp Enabled −2.0 −3.0 mA −40˚C to +85˚C (TP3070-X) −4.0 mA Note 9:“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Note 10:See definitions and timing conventions section. Timing Specifications Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ;V BB = −5V ±5% ;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units MASTER CLOCK TIMING f MCLK Frequency of MCLK Selection of Frequency is 512 kHz Programmable (SeeTable 5) 1536 kHz 1544 kHz 2048 kHz 4096 kHz t WMH Period of MCLK High Measured from V IH to VIH (Note 11) 80 ns tWML Period of MCLK Low Measured from V IL to VIL (Note 11) 80 ns tRM Rise Time of MCLK Measured from V IL to VIH 30 ns tFM Fall Time of MCLK Measured from V IH to VIL 30 ns tHBM HOLD Time, BCLK LOW TP3070 Only 50 ns to MCLK HIGH tWFL Period of FSX or FSR Low Measured from V IL to VIL 1 MCLK Period PCM INTERFACE TIMING f BCLK Frequency of BCLK May Vary from 64 kHz to 4096 kHz 64 4096 kHz in 8 kHz Increments tWBH Period of BCLK High Measured from V IH to VIH 80 ns tWBL Period of BCLK Low Measured from V IL to VIL 80 ns tRB Rise Time of BCLK Measured from V IL to VIH 30 ns tFB Fall Time of BCLK Measured from V IH to VIL 30 ns tHBF Hold Time, BCLK Low 30 ns to FSX/R High or Low tSFB Setup Time, FSX/R 30 ns High to BCLK Low tDBD Delay Time, BCLK High Load = 100 pF Plus 2 LSTTL Loads 80 ns to Data Valid −40˚C to +85˚C (TP3070-X) 90 ns www.national.com 12

Timing Specifications(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ;V BB = −5V ±5% ;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units PCM INTERFACE TIMING t DBZ Delay Time, BCLK Low to DX0/1 D X0/1 Disabled is measured at VOL or VOH according toFigure 4or Figure 5 Disabled if FSX Low, FSX Low to D X0/1 disabled if 8th BCLK 15 80 ns Low, or BCLK High to DX0/1 Disabled if FSX High −40˚C to +85˚C (TP3070-X) 15 100 ns tDBT Delay Time, BCLK High to TSX Low if FSX High, or FSX High to TS X Low if BCLK High (Non Delayed Mode); BCLK High to TS X Low (Delayed Data Mode) Load = 100 pF Plus 2 LSTTL Loads 60 ns tZBT TRI-STATE Time, BCLK Low to TS X High if FSX Low, FSX Low to TSX High if 8th BCLK Low, or BCLK High to TSX High if FSX High 15 60 ns tDFD Delay Time, FSX/R Load = 100 pF Plus 2 LSTTL Loads, High to Data Valid Applies if FS X/R Rises Later than 80 ns BCLK Rising Edge in Non-Delayed Data Mode Only −40˚C to +85˚C (TP3070-X) 90 ns t SDB Setup Time, DR 0/1 30 ns Valid to BCLK Low tHBD Hold Time, BCLK 15 ns Low to DR 0/1 Invalid −40˚C to +85˚C (TP3070-X) 15 ns SERIAL CONTROL PORT TIMING f CCLK Frequency of CCLK 2048 kHz tWCH Period of CCLK High Measured from V IH to VIH 160 ns tWCL Period of CCLK Low Measured from V IL to VIL 160 ns tRC Rise Time of CCLK Measured from V IL to VIH 50 ns tFC Fall Time of CCLK Measured from V IH to VIL 50 ns tHCS Hold Time, CCLK Low CCLK1 10 ns to CS Low tHSC Hold Time, CCLK CCLK 8 100 ns Low to CS High tSSC Setup Time, CS 60 ns Transition to CCLK Low tSSCO Setup Time, CS 50 ns Transition to CCLK High tSDC Setup Time, CI (CI/O) 50 ns Data In to CCLK Low tHCD Hold Time, CCLK 50 ns Low to CI/O Invalid t DCD Delay Time, CCLK High Load = 100 pF plus 2 LSTTL Loads 80 ns to CI/O Data Out Valid −40˚C to +85˚C (TP3070-X) 100 ns www.national.com13

All timing parameters are measured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Note 11:Applies only to MCLK Frequencies≥ 1.536 MHz. At 512 kHz a 50:50±2% Duty Cycle must be used. FIGURE 4. Non Delayed Data Timing Mode

FIGURE 5. Delayed Data Timing Mode

FIGURE 6. Control Port Timing

Transmission Characteristics Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f= 1015.625 Hz, VFXI= 0 dBm0, DR 0o rDR 1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de- sign and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE Absolute Levels The Maximum 0 dBm0 Levels are: VF XI 1.619 Vrms VF R O (15 kΩ Load) 1.964 Vrms The Minimum 0 dBm0 Levels are: VF XI 87.0 mVrms VF R O (Any Load≥ 300Ω ) 105.0 mVrms Overload Levels are 3.17 dBm0 (µLaw) and 3.14 dBm0 (A-Law) G XA Transmit Gain Transmit Gain Programmed for Maximum Absolute Accuracy 0 dBm0 Test Level. (All 1’s in gain register) Measure Deviation of Digital Code from Ideal 0 dBm0 PCM Code at D X0/1. TA = 25˚C −0.15 0.15 dB G XAG Transmit Gain T A = 25˚C, VCC = 5V, VBB = 5V Variation with Programmed Gain from 0 dB to 19 dB Programmed Gain (0 dBm0 Levels of 1.619 Vrms to 0.182 Vrms) −0.1 0.1 dB Programmed Gain from 19.1 dB to 25.4 dB (0 dBm0 Levels of 0.180 Vrms to 0.087 Vrms) −0.3 0.3 dB Note: ±0.1 dB min/max is available as a selected part. G XAF Transmit Gain Relative to 1015.625 Hz, (Note 15) Variation with Minimum Gain < G X < Maximum Gain Frequency f = 60 Hz −26 dB f= 200 Hz −1.8 −0.1 dB f= 300 Hz to 3000 Hz −0.15 0.15 dB f= 3400 Hz −0.7 0.0 dB f= 4000 Hz −14 dB f≥ 4600 Hz. Measure Response −32 dB at Alias Frequency from 0 kHz to 4 kHz. G X = 0 dB, VFXI= 1.619 Vrms Relative to 1015.625 Hz f= 62.5 Hz −24.9 dB f= 203.125 Hz −1.7 −0.1 dB f= 343.75 Hz −0.15 0.15 dB f= 515.625 Hz −0.15 0.15 dB f= 2140.625 Hz −0.15 0.15 dB f= 3156.25 Hz −0.15 0.15 dB f= 3406.250 Hz −0.74 0.0 dB f= 3984.375 Hz −13.5 dB Relative to 1062.5 Hz (Note 15) f= 5250 Hz, Measure 2750 Hz −32 dB f= 11750 Hz, Measure 3750 Hz −32 dB f= 49750 Hz, Measure 1750 Hz −32 dB www.national.com17

Transmission Characteristics(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f= 1015.625 Hz, VFXI= 0 dBm0, DR 0o rDR 1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de- sign and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE G XAT Transmit Gain Measured Relative to G XA ,V CC = 5V, Variation with V BB = −5V, −0.1 0.1 dB Temperature Minimum gain < G X < Maximum Gain G XAL Transmit Gain Sinusoidal Test Method. Variation with Signal Reference Level = 0 dBm0. Level VF XI= −40 dBm0 to +3 dBm0 −0.2 0.2 dB VF XI= −50 dBm0 to −40 dBm0 −0.4 0.4 dB VF XI= −55 dBm0 to −50 dBm0 −1.2 1.2 dB G RA Receive Gain Receive Gain Programmed for Maximum Absolute Accuracy 0 dBm0 Test Level (All 1’s in Gain Register). Apply 0 dBm0 PCM Code to D R 0o rDR 1. Measure VFR O. TA = 25˚C −0.15 0.15 dB G RAG Receive Gain T A = 25˚C, VCC = 5V, VBB = −5V Variation with Programmed Gain from 0 dB to 19 dB Programmed Gain (0 dBm0 Levels of 1.964 Vrms to 0.220 Vrms) −0.1 0.1 dB Programmed Gain from 19.1 dB to 25.4 dB (0 dBm0 Levels of 0.218 Vrms to 0.105 Vrms) −0.3 0.3 dB Note: ±0.1 dB min/max is available as a selected part. G RAT Receive Gain Measured Relative to G RA . Variation with Temperature VCC = 5V, VBB = −5V. −0.1 0.1 dB Minimum Gain < G R < Maximum Gain G RAF Receive Gain Relative to 1015.625 Hz, (Note 15) Variation with Frequency D R 0o rDR 1 = 0 dBm0 code. Minimum Gain < G R < Maximum Gain f= 200 Hz −0.25 0.15 dB f= 300 Hz to 3000 Hz −0.15 0.15 dB f= 3400 Hz −0.7 0.0 dB f= 4000 Hz −14 dB G R = 0 dB, DR 0 = 0 dBm0 Code, G X = 0 dB (Note 15) f= 296.875 Hz −0.15 0.15 dB f= 1875.00 Hz −0.15 0.15 dB f= 2906.25 Hz −0.15 0.15 dB f= 2984.375 Hz −0.15 0.15 dB f= 3406.250 Hz −0.74 0.0 dB f= 3984.375 Hz −13.5 dB www.national.com 18

Transmission Characteristics(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f= 1015.625 Hz, VFXI= 0 dBm0, DR 0o rDR 1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de- sign and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE G RAL Receive Gain Sinusoidal Test Method. Variation with Signal Reference Level = 0 dBm0. Level D R 0 = −40 dBm0 to +3 dBm0 −0.2 0.2 dB D R 0 = −50 dBm0 to −40 dBm0 −0.4 0.4 dB D R 0 = −55 dBm0 to − 50 dBm0 −1.2 1.2 dB D R 0 = 3.1 dBm0 R L = 600Ω ,G R = −0.5 dB −0.2 0.2 dB R L = 300Ω ,G R = −1.2 dB −0.2 0.2 dB ENVELOPE DELAY DISTORTION WITH FREQUENCY D XA Tx Delay, Absolute f = 1600 Hz 315 µs D XR Tx Delay, Relative to DXA f= 500–600 Hz 220 µs f= 600–800 Hz 145 µs f= 800–1000 Hz 75 µs f= 1000–1600 Hz 40 µs f= 1600–2600 Hz 75 µs f= 2600–2800 Hz 105 µs f= 2800–3000 Hz 155 µs D RA Rx Delay, Absolute f = 1600 Hz 200 µs D RR Rx Delay, Relative to DRA f= 500–1000 Hz −40 µs f= 1000–1600 Hz −30 µs f= 1600–2600 Hz 90 µs f= 2600–2800 Hz 125 µs f= 2800–3000 Hz 175 µs NOISE N XC Transmit Noise, C Message (Note 12) 12 15 dBrnC0 Weighted, µ-law Selected All ‘1’s in Gain Register N XP Transmit Noise, P Message (Note 12) −74 −67 dBm0p Weighted, A-law Selected All ‘1’s in Gain Register N RC Receive Noise, C Message PCM Code is Alternating Positive 8 11 dBrnC0 Weighted, µ-law Selected and Negative Zero N RP Receive Noise, P Message PCM Code Equals Positive Zero −82 −79 dBm0p Weighted, A-law Selected N RS Noise, Single Frequency f = 0 kHz to 100 kHz, Loop Around −53 dBm0 Measurement, VFXI= 0 Vrms PPSR X Positive Power Supply V CC = 5.0 VDC + 100 mVrms Rejection, Transmit f = 0 kHz–4 kHz (Note 13) 36 dBC f= 4 kHz–50 kHz 30 dBC NPSR X Negative Power Supply V BB = −5.0 VDC + 100 mVrms Rejection, Transmit f = 0 kHz–4 kHz (Note 13) 36 dBC f= 4 kHz–50 kHz 30 dBC www.national.com19

Transmission Characteristics(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f= 1015.625 Hz, VFXI= 0 dBm0, DR 0o rDR 1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de- sign and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units NOISE PPSR R Positive Power Supply PCM Code Equals Positive Zero Rejection, Receive V CC = 5.0 VDC + 100 mVrms Measure VFR O f= 0 Hz–4000 Hz 36 dBC f= 4 kHz–25 kHz 40 dB f= 25 kHz–50 kHz 36 dB NPSR R Negative Power Supply PCM Code Equals Positive Zero Rejection, Receive V BB = −5.0 VDC + 100 mVrms Measure VFR O f= 0 Hz–4000 Hz 36 dBC f= 4 kHz–25kHz 40 dB f= 25 kHz–50 kHz 36 dB SOS Spurious Out-of-Band 0 dBm0, 300 Hz to 3400 Hz Input PCM Signals at the Channel Code Applied at D R 0 (or DR 1) Output 4600 Hz–7600 Hz −30 dB

7600 Hz–8400 Hz −40 dB

8400 Hz–50,000 Hz −30 dB

X Signal to Total Distortion Sinusoidal Test Method STD R Transmit or Receive Level = 3.0 dBm0 33 dBC Half-Channel, µ-law Selected= 0 dBm0 to − 30 dBm0 36 dBC = −40 dBm0 30 dBC = −45 dBm0 25 dBC STD RL Signal to Total Distortion Sinusoidal Test Method Receive with Level = +3.1 dBm0 Resistive Load R L = 600Ω ,G R = −0.5 dB 33 dBC R L = 300Ω ,G R = −1.2 dB 33 dBC SFD X Single Frequency −46 dB Distortion, Transmit SFD R Single Frequency −46 dB Distortion, Receive IMD Intermodulation Distortion Transmit or Receive Two Frequencies in the Range −41 dB

300 Hz–3400 Hz

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Transmission Characteristics(Continued) Unless otherwise noted, limits printed inBOLD characters are guaranteed for VCC = +5V ±5% ,V BB = −5V ±5% ;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at TA = 25˚C. f= 1015.625 Hz, VFXI= 0 dBm0, DR 0o rDR 1 = 0 dBm0 PCM code. Transmit and receive gains programmed for maximum 0 dBm0 test levels (0 dB gain), hybrid balance filter disabled. All other limits are assured by correlation with other production tests and/or product de- sign and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units CROSSTALK CT X-R Transmit to Receive Crosstalk, 0 dBm0 Transmit Level f= 300 Hz–3400 Hz −90 −75 dB D R = Idle Code CT R-X Receive to Transmit Crosstalk, 0 dBm0 Receive Level f= 300 Hz–3400 Hz −90 −70 dB (Note 13) Note 12:Measured by grounded input at VFXI. Note 13:PPSR X, NPSRX, and CTR–X are measured with a −50 dBm0 activation signal applied to VFXI. Note 14:A signal is Valid if it is above VIHor below VILand Invalid if it is between VILand VIH. For the purposes of this specification the following conditions apply: a) All input signals are defined as: VIL = 0.4V, VIH = 2.7V, tR < 10 ns, tF < 10 ns. b) tR is measured from VILto VIH.tF is measured from VIH to VIL. c) Delay Times are measured from the input signal Valid to the output signal Valid. d) Setup Times are measured from the data input Valid to the clock input Invalid. e) Hold Times are measured from the clock signal Valid to the data input Invalid. f) Pulse widths are measured from V ILto VILor from VIH to VIH. Note 15:A multi-tone test technique is used. www.national.com21

Definitions and Timing Conventions DEFINITIONS VIH VIH is the D.C. input level above which an input level is guaranteed to appear as a logical one. This parameter is to be measured by performing a functional test at reduced clock speeds and nomi- nal timing, (i.e., not minimum setup and hold times or output strobes), with the high level of all driving signals set to V IH and maximum supply voltages applied to the device. V IL VIL is the D.C. input level below which an input level is guaranteed to appear as a logical zero to the device. This param- eter is measured in the same manner as V IH but with all driving signal low levels set to VILand minimum supply voltages applied to the device. VOH VOH is the minimum D.C. output level to which an output placed in a logical one state will converge when loaded at the maximum specified load current. V OL VOL is the maximum D.C. output level to which an output placed in a logical zero state will converge when loaded at the maximum specified load current. Threshold Region The threshold region is the range of in- put voltages between V IL and VIH. Valid Signal A signal is Valid if it is in one of the valid logic states. (i.e., above VIH or below VIL). In timing specifications, a signal is deemed valid at the instant it enters a valid state. Invalid signal A signal is invalid if it is not in a valid logic state, i.e., when it is in the thresh- old region between V ILand VIH. In timing specifications, a signal is deemed In- valid at the instant it enters the threshold region. TIMING CONVENTIONS For the purposes of this timing specification the following conventions apply. Input Signals All input signals may be characterized as: V L = 0.4V, VH = 2.4V, tR < 10 ns, tF< 10 ns. Period The period of the clock signal is desig- nated as tPxx where xx represents the mnemonic of the clock signal being specified. Rise Time Rise times are designated as t Ryy, where yy represents a mnemonic of the signal whose rise time is being specified. t Ryy is measured from VIL to VIH. Fall Time Fall times are designated as tFyy, where yy represents a mnemonic of the signal whose fall time is being specified. t Fyy is measured from VIH to VIL. Pulse Width High The high pulse width width is designated as tWzzH , where zz represents the mne- monic of the input or output signal whose pulse width is being specified. High pulse widths are measured from V IH to VIH. Pulse Width Low The low pulse width is designated as tWzzL , where zz represents the mne- monic of the input or output signal whose pulse width is being specified. Low pulse widths are measured from V IL to VIL. Setup Time Setup times are designated as t Swwxx , where ww represents the mnemonic of the input signal whose setup time is be- ing specified relative to a clock or strobe input represented by mnemonic xx. Setup times are measured from the ww Valid to xx Invalid. Hold Time Hold times are designated as T Hwwxx , where ww represents the mnemonic of the input signal whose hold time is being specified relative to a clock or strobe in- put represented by the mnemonic xx. Hold times are measured from xx Valid to ww Invalid. Delay Time Delay times are designated as T Dxxyy[ IHIL], where xx represents the mnemonic of the input reference signal and yy represents the mnemonic of the output signal whose timing is being specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the high going or low going transition of the output signal. Maximum delay times are measured from xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This parameter is tested under the load conditions specified in the Conditions column of the Timing Specifications sec- tion of this datasheet. www.national.com 22

Physical Dimensionsinches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number TP3071J Ceramic Dual-In-Line Package (J) Order Number TP3070J www.national.com 24

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number TP3071N www.national.com25

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Plastic Leaded Chip Carrier (V) Order Number TP3070V or TP3070V-X TP3070, TP3071, TP3070-X COMBO II Programmable PCM CODEC/Filter National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.