TP3067N

TP3064 NSC | Alldatasheet

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Y Complete CODEC and filtering system including: Ð Transmit high-pass and low-pass filtering Ð Receive low-pass filter with sin x/x correction Ð Active RC noise filters Ð m-law or A-law compatible COder and DECoder Ð Internal precision voltage reference Ð Serial I/O interface Ð Internal auto-zero circuitry Ð Receive push-pull power amplifiers Y m-lawÐTP3064 Y A-lawÐTP3067 Y Designed for D3/D4 and CCITT applications Y g5V operation Y Low operating powerÐtypically 70 mW Y Power-down standby modeÐtypically 3 mW Y Automatic power-down Y TTL or CMOS compatible digital interfaces Y Maximizes line interface card circuit density Block Diagram TL/H/5070–1 FIGURE 1 C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/H/5070–2 Top View Plastic Chip Carrier TL/H/5070–6 Top View Order Number TP3064J or TP3067J See NS Package J20A Order Number TP3064WM or TP3067WM See NS Package M20B Order Number TP3064N or TP3067N See NS Package N20A Order Number TP3064V or TP3067V See NS Package V20A Pin Description Symbol Function VPOa The non-inverted output of the receive power amplifier. GNDA Analog ground. All signals are referenced to this pin. VPOb The inverted output of the receive power amplifier. VPI Inverting input to the receive power amplifier. VF RO Analog output of the receive filter. VCC Positive power supply pin. V CCea 5Vg5%. FSR Receive frame sync pulse which enables BCLKR to shift PCM data into D R.F S R is an 8 kHz pulse train. See Figures 2 and 3 for timing details. DR Receive data input. PCM data is shifted into DR following the FS R leading edge. BCLKR/ The bit clock which shifts data into D R after the FS R leading edge. May vary from 64 kHzCLKSEL to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLK X is used for both transmit and receive directions (see Table I). MCLKR/ Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May bePDN asynchronous with MCLK X, but should be synchronous with MCLK X for best performance. When MCLK R is connected continuously low, MCLK X is selected for all internal timing. When MCLK R is connected continuously high, the device is powered down. Symbol Function MCLK X Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLK R. Best performance is realized from synchronous operation. BCLK X The bit clock which shifts out the PCM data on D X. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLK X. DX The TRI-STATE É PCM data output which is enabled by FS X. FSX Transmit frame sync pulse input which enables BCLK X to shift out the PCM data on DX.F S X is an 8 kHz pulse train, see Figures 2 and 3 for timing details. TSX Open drain output which pulses low during the encoder time slot. ANLB Analog Loopback control input. Must be set to logic ‘0’ for normal operation. When pulled to logic ‘1’, the transmit filter input is disconnected from the output of the transmit preamplifier and connected to the VPO a output of the receive power amplifier. GSX Analog output of the transmit input amplifier. Used to externally set gain. VFXIb Inverting input of the transmit input amplifier. VFXIa Non-inverting input of the transmit input amplifier. VBB Negative power supply pin. V BBeb5Vg5%.

When power is first applied, power-on reset circuitry initializ- es the COMBO TM and places it into a power-down state. All non-essential circuits are deactivated and the D X,V F RO, VPOb and VPO a outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLK R/PDN pin and FSX and/or FS R pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLK R/PDN pin high; the alternative is to hold both FS X and FS R inputs continuously lowÐthe device will power-down approximately 2 ms after the last FS X or FS R pulse. Power-up will occur on the first FSX or FS R pulse. The TRI-STATE PCM data output, D X, will remain in the high impedance state until the second FS X pulse. SYNCHRONOUS OPERATION For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive di- rections. In this mode, a clock must be applied to MCLK X and the MCLK R/PDN pin can be used as a power-down control. A low level on MCLK R/PDN powers up the device and a high level powers down the device. In either case, MCLK X will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be ap- plied to BCLK X and the BCLK R/CLKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. With a fixed level on the BCLK R/CLKSEL pin, BLCK X will be selected as the bit clock for both the transmit and receive directions. Table I indicates the frequencies of operation which can be selected, depending on the state of BCLK CLKSEL. In this synchronous mode, the bit clock, BCLK X, may be from 64 kHz to 2.048 MHz, but must be synchro- nous with MCLK Each FS X pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled D X output on the positive edge of BCLK X. After 8 bit clock periods, the TRI-STATE D X output is returned to a high impedance state. With an FS R pulse, PCM data is latched via the D R input on the negative edge of BCLK X (or BCLKR if running). FS X and FS R must be synchronous with MCLKX/R. TABLE I. Selection of Master Clock Frequencies Master Clock BCLKR/CLKSEL Frequency Selected TP3067 TP3064 Clocked 2.048 MHz 1.536 MHz or

1.544 MHz

0 1.536 MHz or 2.048 MHz 1 2.048 MHz 1.536 MHz or For asynchronous operation, separate transmit and receive clocks may be applied. MCLK X and MCLK R must be 2.048 MHz for the TP3067, or 1.536 MHZ, 1.544 MHz for the TP3064, and need not be synchronous. For best transmis- sion performance, however, MCLK R should be synchronous with MCLK X, which is easily achieved by applying only static logic levels to the MCLK R/PDN pin. This will automatically connect MCLK X to all internal MCLK R functions (see Pin Description). For 1.544 MHz operation, the device automati- cally compensates for the 193rd clock pulse each frame. FS X starts each encoding cycle and must be synchronous with MCLK X and BCLK X.F S R starts each decoding cycle and must be synchronous with BCLK R. BCLK R must be a clock, the logic levels shown in Table I are not valid in asyn- chronous mode. BCLK X and BCLK R may operate from 64 kHz to 2.048 MHz. SHORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sync pulse (the same as the TP3020/21 CODECs) or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FS X and FSR, must be one bit clock period long, with timing relation- ships specified in Figure 2 . With FS X high during a falling edge of BCLK X, the next rising edge of BCLK X enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the D X output. With FS R high during a falling edge of BCLK R (BCLKX in synchronous mode), the next falling edge of BCLK R latches in the sign bit. The following seven falling edges latch in the seven remaining bits. All devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode. LONG FRAME SYNC OPERATION To use the long (TP5116A/56 CODECs) frame mode, both the frame sync pulses, FS X and FS R, must be three or more bit clock periods long, with timing relationships specified in Figure 3 . Based on the transmit frame sync, FS X, the COM- BO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The D X TRI- STATE output buffer is enabled with the rising edge of FS X or the rising edge of BCLK X, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLK X rising edges clock out the remaining seven bits. The DX output is disabled by the falling BCLK X edge following the eighth rising edge, or by FS X going low, whichever comes later. A rising edge on the receive frame sync pulse, FS R, will cause the PCM data at D R to be latched in on the next eight falling edges of BCLK R(BCLKX in synchronous mode). All devices may utilize the long frame sync pulse in synchronous or asynchronous mode. TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4 . The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be real- ized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-ca- pacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to m-law (TP3064) or A-law (TP3067) coding conventions. A preci- sion voltage reference is trimmed in manufacturing to pro- vide an input overload (t MAX) of nominally 2.5V peak (see

Functional Description (Continued) table of Transmission Characteristics). The FS X frame sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through D X at the next FS X pulse. The total encoding delay will be ap- proximately 165 ms (due to the transmit filter) plus 125 ms (due to encoding delay), which totals 290 ms. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3067) or m-law (TP3064) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter with its output at VF RO. The receive section is unity-gain, but gain can be added by using the power amplifiers. Upon the occurrence of FS R, the data at the D R input is clocked in on the falling edge of the next eight BCLK R (BCLKX) peri- ods. At the end of the decoder time slot, the decoding cycle begins, and 10 ms later the decoder DAC output is updated. The total decoder delay is E10 ms (decoder update) plus 110 ms (filter delay) plus 62.5 ms( (/2 frame), which gives approximately 180 ms. RECEIVE POWER AMPLIFIERS Two inverting mode power amplifiers are provided for direct- ly driving a matched line interface transformer. The gain of the first power amplifier can be adjusted to boost the g2.5V peak output signal from the receive filter up to g3.3V peak into an unbalanced 300 X load, or g4.0V into an unbal- anced 15 k X load. The second power amplifier is internally connected in unity-gain inverting mode to give 6 dB of signal gain for balanced loads. Maximum power transfer to a 600 X subscriber line termina- tion is obtained by differentially driving a balanced trans- former with a S2:1 turns ratio, as shown in Figure 4 . A total peak power of 15.6 dBm can be delivered to the load plus termination. ENCODING FORMAT AT D X OUTPUT TP3064 TP3067 m-Law A-Law (Includes Even Bit Inversion) VIN ea Full-Scale 1 000000010101010 VIN e 0 V 1 111111111010101 Ð0 111111101010101 VIN eb Full-Scale 0 000000000101010

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. V CC to GNDA 7V VBB to GNDA b7V Voltage at any Analog Input or Output V CCa0.3V to V BBb0.3V Voltage at any Digital Input or Output V CCa0.3V to GNDA b0.3V Operating Temperature Range b25§Ct o a125§C Storage Temperature Range b65§Ct o a150§C Lead Temp. (Soldering, 10 sec.) 300 §C ESD (Human Body Model) J 1000V ESD (Human Body Model) N 1500V Latch-Up Immunity 100 mA on Any Pin Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e a5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V CC ea 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units POWER DISSIPATION (ALL DEVICES) ICC0 Power-Down Current (Note) 0.5 1.5 mA IBB0 Power-Down Current (Note) 0.05 0.3 mA ICC1 Active Current VPI e0V; VF RO, VPO a and VPO b unloaded 7.0 10.0 mA IBB1 Active Current VPI e0V; VF RO, VPO a and VPO b unloaded 7.0 10.0 mA DIGITAL INTERFACE VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.2 V VOL Output Low Voltage D X,I Le3.2 mA 0.4 V TSX,I Le3.2 mA, Open Drain 0.4 V VOH Output High Voltage D X,I Heb3.2 mA 2.4 V IIL Input Low Current GNDA sVINsVIL, All Digital Inputs b10 10 mA IIH Input High Current V IHsVINsVCC b10 10 mA IOZ Output Current in High Impedance D X, GNDA sVOsVCC b10 10 mA State (TRI-STATE) Note: ICC0 and I BB0 are measured after first achieving a power-up state.

Electrical Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC ea 5.0Vg5%, V BB eb 5.0Vg5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V CC e a5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES) IIXA Input Leakage Current b2.5VsVsa2.5V, VF XIa or VF XIb b200 200 nA RIXA Input Resistance b2.5VsVsa2.5V, VF XIa or VF XIb 10 M X ROXA Output Resistance Closed Loop, Unity Gain 1 3 X RLXA Load Resistance GS X 10 k X CLXA Load Capacitance GS X 50 pF VOXA Output Dynamic Range GS X,R Lt10 k X b2.8 a2.8 V AVXA Voltage Gain VF XIa to GS X 5000 V/V FUXA Unity-Gain Bandwidth 1 2 MHz VOSXA Offset Voltage b20 20 mV VCMXA Common-Mode Voltage CMRRXA l 60 dB b2.5 2.5 V CMRRXA Common-Mode Rejection Ratio DC Test 60 dB PSRRXA Power Supply Rejection Ratio DC Test 60 dB ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES) RORF Output Resistance Pin VF RO1 3 X RLRF Load Resistance VF ROeg2.5V 10 k X CLRF Load Capacitance Connect from VF RO to GNDA 25 pF VOSRO Output DC Offset Voltage Measure from VF RO to GNDA b200 200 mV ANALOG INTERFACE WITH POWER AMPLIFIERS (ALL DEVICES) IPI Input Leakage Current b1.0VsVPIs1.0V b100 100 nA RIPI Input Resistance b1.0VsVPIs1.0V 10 M X VIOS Input Offset Voltage b25 25 mV ROP Output Resistance Inverting Unity-Gain at 1 X VPOa or VPO b FC Unity-Gain Bandwidth Open Loop (VPO b) 400 kHz CLP Load Capacitance 100 pF GAPa Gain from VPO b to VPO a RLe600X VPOa to VPO b b1 V/V Level at VPO be1.77 Vrms PSRRP Power Supply Rejection of VPO b Connected to VPI VCC or V BB 0 kHz b4 kHz 60 dB 4 kHz b50 kHz 36 dB RLP Load Resistance Connect from VPO a to VPO b 600 X

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC ea 5.0V g5%, V BB eb 5.0V g5%, T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals are referenced to GNDA. Typicals specified at V CC e See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units 1/tPM Frequency of Master Clock 1.536 MHz MCLKX and MCLK R 2.048 MHz tRM Rise Time of Master Clock MCLK X and MCLK R 50 ns tFM Fall Time of Master Clock MCLK X and MCLK R 50 ns tPB Period Bit of Clock 485 488 15725 ns tRB Rise Time of Bit Clock BCLK X and BCLK R 50 ns tFB Fall Time of Bit Clock BCLK X and BCLK R 50 ns tWMH Width of Master Clock High MCLK X and MCLK R 160 ns tWML Width of Master Clock Low MCLK X and MCLK R 160 ns tSBFM Set-Up Time from BCLK X High 100 ns to MCLK X Falling Edge tSFFM Set-Up Time from FS X High Long Frame Only 100 ns to MCLK X Falling Edge tWBH Width of Bit Clock High 160 ns tWBL Width of Bit Clock Low 160 ns tHBFL Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync tHBFS Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync tSFB Set-Up Time for Frame Sync Long Frame Only 80 ns to Bit Clock Low tDBD Delay Time from BCLK X High Load e150 pF plus 2 LSTTL Loads 0 180 ns to Data Valid tDBTS Delay Time to TS X Low Load e150 pF plus 2 LSTTL Loads 140 ns tDZC Delay Time from BCLK X Low to 50 165 ns Data Output Disabled tDZF Delay Time to Valid Data from C Le0 pF to 150 pF 20 165 ns FSX or BCLK X, Whichever Comes Later tSDB Set-Up Time from D R Valid to 50 ns BCLKR/X Low tHBD Hold Time from BCLK R/X Low to 50 ns DR Invalid tSF Set-Up Time from FS X/R to Short Frame Sync Pulse (1 Bit Clock 50 ns BCLKX/R Low Period Long) tHF Hold Time from BCLK X/R Low Short Frame Sync Pulse (1 Bit Clock 100 ns to FS X/R Low Period Long) tHBFI Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns Bit Clock Low to Frame Sync Clock Periods Long) (FS X or FS R) tWFL Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns Sync Pulse (Low Level)

FIGURE 2. Short Frame Sync Timing

FIGURE 3. Long Frame Sync Timing

Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC ea 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, V IN e 0 dbm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V CC ea 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE Absolute Levels Nominal 0 dBm0 Level is 4 dBm (Definition of (600 X) nominal gain) 0 dBm0 1.2276 Vrms tMAX Virtual Decision Value Defined Max Transmit Overload Level per CCITT Rec. G711 TP3064 (3.17 dBm0) 2.501 V PK TP3067 (3.14 dBm0) 2.492 V PK GXA Transmit Gain, Absolute T Ae25§C, V CCe5V, V BBeb5V b0.15 0.15 dB GXR Transmit Gain, Relative to G XA fe16 Hz b40 dB fe50 Hz b30 dB fe60 Hz b26 dB fe200 Hz b1.8 b0.1 dB fe300 Hz-3000 Hz b0.15 0.15 dB fe3300 Hz b0.35 0.05 dB fe3400 Hz b0.7 0 dB fe4000 Hz b14 dB fe4600 Hz and Up, Measure b32 dB Response from 0 Hz to 4000 Hz with Temperature with Supply Voltage GXRL Transmit Gain Variations with Sinusoidal Test Method Level Reference Level eb10 dBm0 VFXIa eb40 dBm0 to a3 dBm0 b0.2 0.2 dB VFXIa eb50 dBm0 to b40 dBm0 b0.4 0.4 dB VFXIa eb55 dBm0 to b50 dBm0 b1.2 1.2 dB GRA Receive Gain, Absolute T Ae25§C, V CCe5V, V BBeb5V b0.15 0.15 dB InputeDigital Code Sequence for 0 dBm0 Signal GRR Receive Gain, Relative to G RA fe0 Hz to 3000 Hz b0.15 0.15 dB fe3300 Hz b0.35 0.05 dB fe3400 Hz b0.7 0 dB fe4000 Hz b14 dB with Temperature with Supply Voltage GRRL Receive Gain Variations with Sinusoidal Test Method; Reference Level Input PCM Code Corresponds to an Ideally Encoded b 10 dBm0 Signal PCM Level eb40 dBm0 to a3 dBm0 b0.2 0.2 dB PCM Level eb50 dBm0 to b40 dBm0 b0.4 0.4 dB PCM Level eb55 dBm0 to b50 dBm0 b1.2 1.2 dB VRO Receive Filter Output at VF ROR L e10 k X b2.5 2.5 V

Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC ea 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, V IN e 0 dbm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V CC ea 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units ENVELOPE DELAY DISTORTION WITH FREQUENCY DXA Transmit Delay, Absolute f e1600 Hz 290 315 ms DXR Transmit Delay, Relative to D XA fe500 Hz b600 Hz 195 220 ms fe600 Hz b800 Hz 120 145 ms fe800 Hz b1000 Hz 50 75 ms fe1000 Hz b1600 Hz 20 40 ms fe1600 Hz b2600 Hz 55 75 ms fe2600 Hz b2800 Hz 80 105 ms fe2800 Hz b3000 Hz 130 155 ms DRA Receive Delay, Absolute f e1600 Hz 180 200 ms DRR Receive Delay, Relative to D RA fe500 Hz b1000 Hz b40 b25 ms fe1000 Hz b1600 Hz b30 b20 ms fe1600 Hz b2600 Hz 70 90 ms fe2600 Hz b2800 Hz 100 125 ms fe2800 Hz b3000 Hz 145 175 ms NOISE NXC Transmit Noise, C Message TP3064 (Note 1) 12 15 dBrnC0 Weighted NXP Transmit Noise, Psophometric TP3067 (Note 1) b74 b67 dBm0p Weighted NRC Receive Noise, C Message PCM Code Equals Alternating Weighted Positive and Negative Zero TP3064 8 11 dBrnCO NRP Receive Noise, Psophometric PCM Code Equals Positive Weighted Zero TP3067 b82 b79 dBm0p NRS Noise, Single Frequency f e0 kHz to 100 kHz, Loop Around b53 dBm0 Measurement, VF XIa e0 Vrms PPSRX Positive Power Supply Rejection, V CCe5.0 V DCa100 mVrms Transmit f e0 kHz b50 kHz (Note 2) 40 dBC NPSRX Negative Power Supply Rejection, V BBeb5.0 V DCa 100 mVrms Transmit f e0 kHz b50 kHz (Note 2) 40 dBC PPSRR Positive Power Supply Rejection, PCM Code Equals Positive Zero Receive V CCe5.0 V DCa100 mVrms Measure VF RO fe0H z b4000 Hz 38 dBC fe4 kHz b50 kHz 25 dB NPSRR Negative Power Supply Rejection, PCM Code Equals Positive Zero Receive V BBeb5.0 V DCa100 mVrms Measure VF RO fe0H z b4000 Hz 40 dBC fe4 kHz b25 kHz 40 dB fe25 kHz b50 kHz 36 dB SOS Spurious Out-of-Band Signals 0 dBm0, 300 Hz b3400 Hz Input at the Channel Output PCM Code Applied at DR Measure Individual Image Signals at VF RO

4600 Hz–7600 Hz b32 dB

7600 Hz–8400 Hz b40 dB

8400 Hz–100,000 Hz b32 dB

Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC ea 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, V IN e 0 dbm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V CC ea 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units DISTORTION STDX, Signal to Total Distortion Sinusoidal Test Method (Note 3) STDR Transmit or Receive Level e3.0 dBm0 33 dBC Half-Channel e0 dBm0 to b30 dBm0 36 dBC eb40 dBm0 XMT 29 dBC RCV 30 dBC eb55 dBm0 XMT 14 dBC RCV 15 dBC SFDX Single Frequency Distortion, b46 dB Transmit SFDR Single Frequency Distortion, b46 dB Receive IMD Intermodulation Distortion Loop Around Measurement, b41 dB VFXIa eb4 dBm0 to b21 dBm0, Two Frequencies in the Range 300 Hz b3400 Hz CROSSTALK CTX-R Transmit to Receive Crosstalk f e300 Hz b3000 Hz DReQuiet PCM Code b90 b75 dB CTR-X Receive to Transmit Crosstalk f e300 Hz b3000 Hz, VF XIe0V b90 b70 dB (Note 2) POWER AMPLIFIERS VOPA Maximum 0 dBm0 Level Balanced Load, R L Connected Between (Better than g0.1 dB Linearity over VPO a and VPO b. the Range b10 dBm0 to a3 dBm0) R Le600X 3.3 Vrms RLe1200X 3.5 Vrms S/DP Signal/Distortion R Le600X 50 dB Note 1: Measured by extrapolation from the distortion test result at b50 dBm0. Note 2: PPSRX, NPSR X, and CT RbX are measured with a b50 dBm0 activation signal applied to VF XIa. Note 3: TP3064 is measured using C message weighted filter. TP3067 is measured using psophometric weighted filter.

While the pins of the TP3060 family are well protected against electrical misuse, it is recommended that the stan- dard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a ‘‘hot’’ socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 mF supply decou- pling capacitors should be connected from this common ground point to V CC and V BB, as close to the device as possible. For best performance, the ground point of each CODEC/ FILTER on a card should be connected to a common card ground in ‘‘STAR’’ formation, rather than via a ground bus. This common ground point should be decoupled to V CC and VBB with 10 mF capacitors. Note: See Application Note 370 for further details Typical Asynchronous Application TL/H/5070–5 Note 1: Transmit gain e 20 c log R1 a R2 R2 J ,(R1 a R2) t 10 k X Note 2: Receive gain e 20 c log 2 c R3 R4 J ,R4 t 10 k X FIGURE 4

Definitions and Timing Conventions DEFINITIONS VIH VIH is the d.c. input level above which an input level is guaranteed to appear as a logical one. This parameter is to be measured by performing a functional test at reduced clock speeds and nominal timing, (i.e. not minimum setup and hold times or output strobes), with the high level of all driving signals set to V IH and maximum supply voltages applied to the device V IL VIL is the d.c. input level below which an input level is guaranteed to appear as a logical zero to the device. This parameter is measured in the same manner as V IH but with all driving signal low levels set to V IL and minimum supply voltages applied to the device. V OH VOH is the minimum d.c. output level to which an output placed in a logical one state will converge when loaded at the maximum specified load current. V OL VOL is the maximum d.c. output level to which an output placed in a logical zero state will converge when loaded at the maximum specified load current. Threshold Region The threshold region is the range of input voltages between V IL and V IH. Valid Signal A signal is Valid if it is in one of the valid logic states, (i.e. above V IH or below V IL). In timing specifiations, a signal is deemed valid at the instant it enters a valid state. Invalid Signal A signal is Invalid if it is not in a valid logic state, i.e. when it is in in the threshold region between V IL and V IH. In timing specifications, a signal is deemed Invalid at the instant it enters the threshold region. TIMING CONVENTIONS For the purposes of this timing specification, the following conventions apply: Input Signals All input signals may be characterized as: V L e 0.4V, V H e 2.4V, t R k 10 ns, tF k 10 ns. Period The period of clock signal is designated as t Pxx where xx represents the mnemonic of the clock signal being specified. Rise Time Rise times are designated as t Ryy, where yy represents a mnemonic of the signal whose rise time is being specified. t Ryy is measured from V IL to VIH. Fall Time Fall times are designated as t Fyy, where yy represents a mnemonic of the signal whose fall time is being specified. t Fyy is measured from V IH to VIL. Pulse Width High The high pulse width is designated as tWzzH, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. High pulse widths are measured from V IH to V IH. Pulse Width Low The low pulse width is designated as tWzzL, where zz represents the mnemonic of the input or output signal whose pulse width is being specified. Low pulse widths are measured from V IL to V IL. Setup Time Setup times are designated as t Swwxx, where ww represents the mnemonic of the input signal whose setup time is being specified relative to a clock or strobe input represented by mnemonic xx. Setup times are measured from the ww Valid to xx Invalid. Hold Time Hold times are designated as t Hxxww, where ww represents the mnemonic of the input signal whose hold time is being specified relative to a clock or strobe input represented by mnemonic xx. Hold times are measured from xx Valid to ww Invalid. Delay Time Delay times are designated as t Dxxyy Hi to Low, where xx represents the mnemonic of the input reference signal and yy represents the mnemonic of the output signal whose timing is being specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the high going or low going transition of the output signal. Maximum delay times are measured from xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This parameter is tested under the load conditions specified in the Conditions column of the Timing Specifications section of this data sheet.

Physical Dimensions inches (millimeters) Cavity Dual-In-Line Package (J) Order Number TP3064J or TP3067J Molded Small Outline Package (WM) Order Number TP3064WM or TP3067WM

Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number TP3064N or TP3067N

TP3064, TP3067 ‘‘Enhanced’’ Serial Interface CMOS CODEC/Filter COMBO Physical Dimensions inches (millimeters) (Continued) Lit. Ý 113975 Plastic Chip Carrier (V) Order Number TP3064V or TP3067V LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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