TP3064ADW

TP3064A TI | Alldatasheet

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TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Complete PCM Codec and Filtering Systems Include: – Transmit High-Pass and Low-Pass Filtering – Receive Low-Pass Filter With (sin x)/x Correction – Active RC Noise Filters – µ-Law or A-Law Compatible Coder and Decoder – Internal Precision Voltage Reference – Serial I/O Interface – Internal Autozero Circuitry /C0068µ-Law – TP3064B and TP13064B /C0068A-Law – TP3067B and TP13067B /C0068± 5-V Operation /C0068Low Operating Power...7 0 m W T y p /C0068Power-Down Standby Mod e...3 m W T y p /C0068Automatic Power Down /C0068TTL- or CMOS-Compatible Digital Interface /C0068Maximizes Line Interface Card Circuit Density /C0068Improved Versions of National Semiconductor TP3064, TP3067, TP3064-X, TP3067-X

description

The TP3064A, TP3067A, TP13064A, and TP13067A are comprised of a single-chip PCM codec (pulse-code-modulated encoder and de- coder) and PCM line filter. These devices provide all the functions required to interface a full-duplex (2-wire) voice telephone circuit with a TDM (time-division-multiplexed) system. These de- vices are pin-for-pin compatible with the National Semiconductor TP3064A and TP3067A, respec- tively. Primary applications include:

• Line interface for digital transmission and switching of T1 carrier, PABX, and central office telephone systems
• Subscriber line concentrators
• Digital-encryption systems
• Digital voice-band data-storage systems
• Digital signal processing These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive frame-sync pulses. The TP3064A, TP3067A, TP13064A, and TP13067A provide the band-pass filtering of the analog signals prior to encoding and after decoding of voice and call progress tones. The TP3067A and TP13067A contain patented circuitry to achieve low transmit channel idle noise and are not recommended for applications in which the composite signals on the transmit side are below –55 dBm0. The TP3064A and TP3067A are characterized for operation from 0°C to 70°C. The TP13064A and TP13067A are characterized for operation from –40°C to 85°C. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the CMOS gates. Copyright  1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. VPO+ ANLG GND VPO– VPI VFRO VCC FSR DR BCLKR/CLKSEL MCLKR/PDN VBB VFXI+ VFXI– GSX ANLG LOOP TSX FSX DX BCLKX MCLKX DW OR N PACKAGE (TOP VIEW)

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996

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3VPO– VFXI+ 19 R118VFXI– Analog Input Switched- Capacitor Low-Pass Filter VPO+ 1 R R

4 VPI

5 VFRO

–5 V5 V

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME NO. ANLG GND 2 Analog ground. All signals are referenced to ANLG GND. ANLG LOOP 16 Analog loopback control input. Must be set to logic low for normal operation. When pulled to logic high, the transmit filter input is disconnected from the output of the transmit preamplifier and connected to VPO+ of the receive power amplifier. BCLKR/CLKSEL 9 The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately, can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode. BCLKX is used for both transmit and receive directions (see Table 1). BCLKX 12 The bit clock that shifts out the PCM data on DX. BCLKX can vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX. DR 8 Receive data input. PCM data is shifted into DR following the FSR leading edge. DX 13 The 3-state PCM data output that is enabled by FSX. FSR 7 Receive frame sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see Figures 1 and 2 for timing details). FSX 14 Transmit frame sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see Figures 1 and 2 for timing details). GSX 17 Analog output of the transmit input amplifier. GSX is used to externally set gain. MCLKR/PDN 10 Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should be synchronous for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down. MCLKX 11 Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR TSX 15 Open-drain output that pulses low during the encoder time slot VBB 20 Negative power supply. VBB = –5 V ± 5% VCC 6 Positive power supply. VCC = 5 V ± 5% VFRO 5 Analog output of the receive filter VFXI+ 19 Noninverting input of the transmit input amplifier VFXI– 18 Inverting input of the transmit input amplifier VPI 4 Inverting input to the receive power amplifier. Also powers down both amplifiers when connected to VBB VPO+ 1 The noninverted output of the receive power amplifier VPO– 3 The inverted output of the receive power amplifier

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DW 1025 mW 8.2 mW/°C 656 mW 533 mW N 1150 mW 9.2 mW/°C 736 mW 598 mW recommended operating conditions (see Note 2) MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V Supply voltage, VBB –4.75 –5 –5.25 V High-level input voltage, VIH 2.2 V Low-level input voltage, VIL 0.6 V Common-mode input voltage range, VICR‡ ± 2.5 V Load resistance at GSX, RL 10 kΩ Load capacitance at GSX, CL 50 pF O perating free air temperature TA TP3064A, TP3067A 0 70 °COperating free-air temperature, TA TP13064A, TP13067A –40 85 ‡ Measure with CMRR > 60 dB. NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current PARAMETER TEST CONDITIONS TP306xA TP1306xA UNITPARAMETER TEST CONDITIONS MIN TYP † MAX MIN TYP † MAX UNIT ICC Supply current from VCC Power down No load 0.5 1 0.5 1.2 mAICC Supply current from VCC Active No load 6 10 6 11 mA IBB Supply current from VBB Power down No load 0.5 1 0.5 1.2 mAIBB Supply current from VBB Active No load 6 10 6 11 mA † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. electrical characteristics at VCC = 5 V ± 5%, VBB = –5 V ± 5%, GND at 0 V, TA = 25°C (unless otherwise noted) digital interface PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level output voltage DX IH = –3.2 mA 2.4 V VOL Low level output voltage DX IL = 3.2 mA 0.4 VVOL Low-level output voltage TSX IL = 3.2 mA, Drain open 0.4 V IIH High-level input current VI = VIH to VCC ± 10 µA IIL Low-level input current All digital inputs VI = GND to VIL ± 10 µA IOZ Output current in high-impedance state DX VO = GND to VCC ± 10 µA analog interface with transmit amplifier input PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT II Input current VFXI+ or VFXI– VI = –2.5 V to 2.5 V ± 200 nA ri Input resistance VFXI+ or VFXI– VI = –2.5 V to 2.5 V 10 M Ω ro Output resistance Closed loop, Unit gain 1 3 Ω Output dynamic range GSX R L ≥ 10 kΩ ± 2.8 V AV Open-loop voltage amplification VFXI+ to GSX 5000 BI Unity-gain bandwidth GSX 1 2 MHz VIO Input offset voltage VFXI+ or VFXI– ± 20 mV CMRR Common-mode rejection ratio 60 dB kSVR Supply-voltage rejection ratio 60 dB † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. analog interface with receive filter PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Output resistance VFRO 1 3 Ω Load resistance VFRO = ± 2.5 V 600 Ω Load capacitance VFRO to GND 500 pF Output dc offset voltage VFRO to GND ± 200 mV † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996

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analog interface with power amplifiers PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT II Input current VPI = –1 V to 1 V ± 100 nA ri Input resistance VPI = –1 V to 1 V 10 M Ω ro Output resistance VPO+ or VPO– Inverting unity gain 1 Ω AV Voltage amplification VPO– or VPO+ VPO– = 1.77 Vrms, R L = 600 Ω –1 BI Unity-gain bandwidth VPO– Open loop 400 kHz VIO Input offset voltage ± 25 mV kSVR Supply voltage rejection ratio of VCC or VBB VPO connected to VPI 0 kHz to 4 kHz 60 dBkSVR Supply-voltage rejection ratio of VCC or VBB VPO – connected to VPI 4 kHz to 50 kHz 36 dB R L Load resistance Connected from VPO+ to VPO– 600 Ω C L Load capacitance 100 pF † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics, over operating free-air temperature range VCC = 5 V ± 5%, VBB = –5 V ± 5%, GND at 0 V, VI = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity gain, noninverting (unless otherwise noted) timing requirements PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT fclock(M) Frequency of master clock MCLX and MCLKR Depends on the device used and BCLKX/CLKSEL 1.536 1.544 2.048 MHz fclock(B) Frequency of bit clock, transmit BCLKX 64 2.048 MHz tr1 Rise time of master clock MCLKX and MCLKR Measured from 20% to 80% 50 ns tf1 Fall time of master clock MCLKX and MCLKR Measured from 20% to 80% 50 ns tr2 Rise time of bit clock, transmit BCLKX Measured from 20% to 80% 50 ns tf2 Fall time of bit clock, transmit BCLKX Measured from 20% to 80% 50 ns tw1 Pulse duration, MCLKX and MCLKR high 160 ns tw2 Pulse duration, MCLKX and MCLKR low 160 ns tsu1 Setup time, BCLKX high (and FSX in long-frame sync mode) before MCLKX↓ First bit clock after the leading edge of FSX 100 ns tw3 Pulse duration, BCLKX and BCLKR high VIH = 2.2 V 160 ns tw4 Pulse duration, BCLKX and BCLKR low VIL = 0.6 V 160 ns th1 Hold time, frame sync low after bit clock low (long frame only) 0 ns th2 Hold time, BCLKX high after frame sync↑ (short frame only) 0 ns tsu2 Setup time, frame sync high before bit clock↓ (long frame only) 80 ns td1 Delay time, BCLKX high to data valid Load = 150 pF plus 2 LSTTL loads‡ 0 140 ns td2 Delay time, BCLKX high to TSX low Load = 150 pF plus 2 LSTTL loads‡ 140 ns td3 Delay time, BCLKX (or 8 clock FSX in long frame only) low to data output disabled 50 165 ns td4 Delay time, FSX or BCLKX high to data valid (long frame only) C L = 0 pF to 150 pF 20 165 ns tsu3 Setup time, DR valid before BCLKR↓ 50 ns th3 Hold time, DR valid after BCLKR or BCLKX↓ 50 ns tsu4 Setup time, FSR or FSX high before BCLKR or BCLKX ↓ Short-frame sync pulse (1- or 2-bit clock periods long) (see Note 3) 50 ns th4 Hold time, FSX or FSR high after BCLKX or BCLKR ↓ Short-frame sync pulse (1- or 2-bit clock periods long) (see Note 3) 100 ns th5 Hold time, frame sync high after bit clock↓ Long-frame sync pulse (from 3- to 8-bit clock periods long) 100 ns tw5 Pulse duration of the frame sync pulse (low level)64 kbps operating mode 160 ns † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. ‡ Nominal input value for an LSTTL load is 18 kΩ . NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996

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filter gains and tracking errors PARAMETER TEST CONDITIONS ‡ MIN TYP † MAX UNIT Maximum peak transmit TP3064A, TP13064A 3.17 dBm0 2.501 Voverload level TP3067A, TP13067A 3.14 dBm0 2.492 V Transmit filter gain, absolute (at 0 dBm0)TA = 25°C –0.15 0.15 dB f = 16 Hz –40 f = 50 Hz –30 f = 60 Hz –26 f = 200 Hz –1.8 –0.1 Transmit filter gain, relative to absolutef = 300 Hz to 3000 Hz –0.15 0.15 dB f = 3300 Hz –0.35 0.05 f = 3400 Hz –0.8 0 f = 4000 Hz –14 f ≥ 4600 Hz (measure response from 0 Hzto4000Hz) –32 Absolute transmit gain variation with temperature and supply voltage Relative to absolute transmit gain –0.1 0.1 dB Sinusoidal test method; Reference level = –10 dBm0 Transmit gain tracking error with level 3 dBm0 ≥ input level ≥ –40 dBm0 ± 0.2 dBTransmit gain tracking error with level –40 dBm0 > input level ≥ –50 dBm0 ± 0.4 dB –50 dBm0 > input level ≥ –55 dBm0 ± 0.8 Receive filter gain, absolute (at 0 dBm0)Input is digital code sequence for 0 dBm0 signal, TA = 25°C –0.15 0.15 dB f = 0 Hz to 3000 Hz, T A = 25°C –0.15 0.15 Receive filter gain relative to absolute f = 3300 Hz –0.35 0.05 dBReceive filter gain, relative to absolute f = 3400 Hz –0.8 0 dB f = 4000 Hz –14 Absolute receive gain variation with temperature and supply voltage TA = full range, See Note 4 –0.1 0.1 dB Sinusoidal test method; reference input PCM code corresponds to an ideally encoded –10 dBm0 signal Receive gain tracking error with level 3 dBm0 ≥ input level ≥ –40 dBm0 ± 0.2 dBgg –40 dBm0 > input level ≥ –50 dBm0 ± 0.4 –50 dBm0 > input level ≥ –55 dBm0 ± 0.8 Receive output drive voltage R L = 10 kΩ ± 2.5 V Transmit and receive gain tracking error with Pseudo-noise-test method; reference input PCM code corresponds to an ideally encoded –10 dBm0 signal Transmit and receive gain tracking error with level (A-law, CCITT C712) 3 dBm0 ≥ input level ≥ –40 dBm0 ± 0.25 dB –40 dBm0 > input level ≥ –50 dBm0 ± 0.3 –50 dBm0 > input level ≥ –55 dBm0 ± 0.45 † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. ‡ Absolute rms signal levels are defined as follows: VI = 1.2276 V = 0 dBm0 = 4 dBm at f = 1.02 kHz with RL = 600 Ω . NOTE 4: Full range for the TP3064A and TP3067A is 0°C to 70°C. Full range for the TP13064A and TP13067A is –40°C to 85°C.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 envelope delay distortion with frequency PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Transmit delay, absolute (at 0 dBm0) f = 1600 Hz 290 315 µs f = 500 Hz to 600 Hz 195 220 f = 600 Hz to 800 Hz 120 145 f = 800 Hz to 1000 Hz 50 75 Transmit filter gain, relative to absolutef = 1000 Hz to 1600 Hz 20 40 µs f = 1600 Hz to 2600 Hz 55 75 f = 2600 Hz to 2800 Hz 80 105 f = 2800 Hz to 3000 Hz 130 155 Receive delay, absolute (at 0 dBm0) f = 1600 Hz 180 200 µs f = 500 Hz to 1000 Hz –40 –25 f = 1000 Hz to 1600 Hz –30 –20 Receive delay, relative to absolute f = 1600 Hz to 2600 Hz 70 90 µs f = 2600 Hz to 2800 Hz 100 125 f = 2800 Hz to 3000 Hz 140 175 † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. noise PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Transmit noise, C-message weighted TP3064A, TP13064A VFXI = 0 V 9 14 dBrnC0 Transmit noise, psophometric weighted (see Note 5) TP3067A, TP13067A VFXI = 0 V –78 –75 dBm0p Receive noise, C-message weighted TP3064A, TP13064A PCM code equals alternating positive and negative zero 2 4 dBrnC0 Receive noise, psophometric weighted TP3067A, TP13067A PCM code equals positive zero –86 –83 dBm0p Noise, single frequency VFXI+ = 0 V, f = 0 kHz to 100 kHz, Loop-around measurement –53 dBm0 † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. NOTE 5: Measured by extrapolation from the distortion test result. This parameter is achieved through use of patented circuitry and is not recommended for applications in which the composite signals on the transmit side are below –55 dBm0.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996

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PARAMETER TEST CONDITIONS MIN MAX UNIT V 5 V 100 V f=0H zt o4k H z A-law 38 dB Positive power-supply rejection, transmitVCC = 5 V + 100 mVrms, VFXI+ = –50 dBm0 f = 0 H z to 4 kHz µ-law 38 dBC † VFXI+ = –50 dBm0 f = 4 kHz to 50 kHz 40 dB V 5 V 100 V f=0H zt o4k H z A-law 35 dB Negative power-supply rejection, transmitVBB = –5 V + 100 mVrms, VFXI+ =–50 dBm0 f = 0 H z to 4 kHz µ-law 35 dBC † VFXI+ = –50 dBm0 f = 4 kHz to 50 kHz 40 dB PCM d l iti f=0H zt o4k H z A-law 40 dB Positive power-supply rejection, receivePCM code equals positive zero, VCC =5V+1 0 0m V r m s f = 0 H z to 4 kHz µ-law 40 dBC † VCC = 5 V + 100 mVrms f = 4 kHz to 50 kHz 40 dB PCM d l iti f=0H zt o4k H z A-law 38 dB Negative power-supply rejection, receivePCM code equals positive zero, VBB = –5 V + 100 mVrms f = 0 H z to 4 kHz µ-law 38 dBC † VBB = –5 V + 100 mVrms f = 4 kHz to 50 kHz 40 dB Spurious out-of-band signals at the 0 dBm0, 300-Hz to 3400-Hz input applied to DR (measure individual image signals at VFRO) –30 dB S urious out of band signals at the channel output (VFRO) f = 4600 Hz to 7600 Hz –33 dB f = 7600 Hz to 100 kHz –40 dB † The unit dBC applies to C-message weighting. distortion PARAMETER TEST CONDITIONS MIN MAX UNIT Level = 3 dBm0 33 Level = 0 dBm0 to –30 dBm0 36 †Signal to distortion ratio transmit or receive half channel‡ Level = 40 dBm0 Transmit 29 dBC †Signal-to-distortion ratio, transmit or receive half-channel‡ Level = –40 dBm0 Receive 30 dBC † Level = 55 dBm0 Transmit 14 Level = –55 dBm0 Receive 15 Single-frequency distortion products, transmit –46 dB Single-frequency distortion products, receive –46 dB Intermodulation distortion Loop-around measurement, VFXI+ = –4 dBm0 to –21 dBm0, Two frequencies in the range of 300 Hz to 3400 Hz –41 dB Pseudo noise test method Level = –3 dBm0 33 Signal-to-distortion ratio, transmit half-channel (A-Law)Level = –6 dBm0 to –27 dBm0 36g, ( ) (CCITT G.714)§ Level = –34 dBm0 33.5 dB Level = –40 dBm0 28.5 Level = –55 dBm0 13.5 Level = –3 dBm0 33 Si l t di t ti ti i h lf h l (A l ) Level = –6 dBm0 to –27 dBm0 36 Signal-to-distortion ratio, receive half-channel (A-law) (CCITT G 714)§ Level = –34 dBm0 34.2 dB(CCITT G .714)§ Level = –40 dBm0 30 Level = –55 dBm0 15 † The unit dBC applies to C-message weighting. ‡ Sinusoidal test method (see Note 6) § Pseudo-noise test method NOTE 6: The TP13064A and TP3064A are measured using a C-message filter. The TP13067A and TP3067A are measured using a psophometric weighted filter.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 crosstalk PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Crosstalk, transmit to receive f = 300 Hz to 3000 Hz, DR at steady PCM code –90 –75 dB Crosstalk, receive to transmit (see Note 7)VFXI = 0 V, f = 300 Hz to 3000 Hz –90 –72 dB † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. NOTE 7: Receive-to-transmit crosstalk is measured with a –50 dBm0 activation signal applied to VFXI+. power amplifiers PARAMETER TEST CONDITIONS MIN MAX UNIT Balanced load, RL connected between VPO+ and VPO – Maximum 0 dBm0 rms level for better than ± 0.1 dB R L = 600 Ω 3.3 linearity over the range if –10 dBm0 to 3 dBm0R L = 1200 Ω 3.5 Vrms R L = 30 kΩ 4 Signal/distortion R L = 600 Ω 50 dB

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Figure 1. Short-Frame Sync Timing

Figure 2. Long-Frame Sync Timing

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996

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system reliability and design considerations TP306xA, TP1306xA system reliability and design considerations are described in the following paragraphs. latch-up Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device if supply current to the device is not limited. Even though the TP306xA and TP1306xA devices are heavily protected against latch-up, it is still possible to cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals. Latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied but before the ground is connected. This can happen if the device is hot-inserted into a card with the power applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted into a system with the power on. To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased Schottky diode (with a forward voltage drop of less than or equal to 0.4 V – 1N5711 or equivalent) between the power supply and GND (see Figure 3). If it is possible that a TP306xA- or TP1306xA-equipped card that has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground edge connector traces are longer than the power and signal traces so that the card ground is always the first to make contact. device power-up sequence Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following power-up sequence always be used: 1. Ensure that no signals are applied to the device before the power-up sequence is complete. 2. Connect GND. 3. Apply V BB (most negative voltage). 4. Apply VCC (most positive voltage). 5. Force a power down condition in the device. 6. Connect clocks. 7. Release the power down condition. 8. Apply FS synchronization pulses. 9. Apply the signal inputs. When powering down the device, this procedure should be followed in the reverse order.

Figure 3. Latch-Up Protection Diode Connection A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions. Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL. Table 1. Selection of Master-Clock Frequencies BCLKR, if running). FSX and FSR must be synchronous with MCLKX and MCLKR.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must be 2.048 MHz for the TP3064A and TP13064A, 1.536 MHz or 1.544 MHz for the TP3067A and TP13067A and need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This is easily achieved by applying only static logic levels to MCLKR/PDN. This connects MCLKX to all internal MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame. Each encoding cycle is started with FSX, and FSX must be synchronous with MCLKX and BCLKX. Each decoding cycle is started with FSR, and FSR must be synchronous with BCLKR. The logic levels shown in Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz. short-frame sync operation The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing relationships specified in Figure 1. With FSX high during a falling edge of BCKLX, the next rising edge of BCLKX enables the 3-state output buffer, DX, which outputs the sign bit. The remaining seven bits are clocked out on the following seven rising edges, and the next falling edge disables DX. With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the remaining bits. The short-frame sync pulse can be utilized in either the synchronous or asynchronous mode. long-frame sync operation Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing relationships, as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a short- or long-frame sync pulse is being used. For 64-kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The rising edge of FSX or BCLKX, which ever occurs later, enables the DX 3-state output buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever occurs later, disables DX. A rising edge on FSR, the receive frame sync pulse, causes the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync pulse may be used in either the synchronous or asynchronous mode.

voltage due to the filters or comparator is cancelled by sign bit integration (see Table 2). Table 2. Encoding Format at DX Output The receive section consists of an expanding DAC that drives a fifth-order low-pass filter clocked at 256 kHz. plus 62.5 µs (1/2 frame), or a total of approximately180 µs. amplifier is internally connected in the unity-gain inverting mode to give 6 dB of signal gain for balanced loads.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

While the pins of the TP1306xA and TP306xA families are well protected against electrical misuse, it is recommended that the standard CMOS practice be followed ensuring that ground is connected to the device before any other connections are made. In applications where the printed-circuit board can be plugged into a hot socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to ANLG GND. This minimizes the interaction of ground return currents flowing through a common bus impedance. V CC and VBB supplies should be decoupled by connecting 0.1-µF decoupling capacitors to this common point. These bypass capacitors must be connected as close as possible to VCC and VBB . For best performance, the ground point of each codec/filter on a card should be connected to a common card ground in star formation rather than via a ground bus. This common ground point should be decoupled to VCC and VBB with 10-µF capacitors.

TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 300 Ω R2 300 Ω 600 Ω –5 V5 V 0.1 µF 0.1 µF FSX DX ANLG LOOP TSX VPO+ GSX VFXI– VFXI+ VBBGNDVCC VPO– VPI VFRO NOTES: A. Transmit gain = 20 y logR1 + R2 (R1 + R2)≥ 10 kΩ B. Receive gain = 20 y log2 × R3 R4 ≥ 10 kΩ Figure 4. Typical Synchronous Application

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