TP3058

TP3058 NSC | Alldatasheet

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Technical content

a & GA National ¢ Semiconductor r=J . z TP3058, TP3059 Microprocessor Compatible COMBO® General Description The TP3058, TP3059 family consists of a p-law and A-law The TP3058 p-law and TP3059 A-law devices are pin com- monolithic PCM COMBO set utilizing the A/D and D/A con- _ patible parallel interface CODEC/filters for microprocessor version architecture shown in Figure 1 and a parallel 1/O —_ and digital signal processor systems. microprocessor bus interface. The devices are fabricated using National's advanced double poly microCMOS pro. Features cess. 1 Complete CODEC and filtering system including: The transmit section consists of an input gain adjust amplifi- — Transmit high pass and low pass filtering _ er, an active RC pre-flter, and a switched-capacitor band- © — Receive low pass filter with sin x/x correction pass filter that rejects signals below 200 Hz and above — Receive power amplifier 3400 Hz. A compressing coder samples the filtered signal — Active RC noise filters and encodes it in the 1-225 law or A-law PCM format. Auto- — 4-255 law COder and DECoder—TP3058 zero circuitry is included on-chip. The receive section con- — A-law COder and DECoder—TP3059 sists of an expanding decoder which reconstructs the ana- — Internal precision voltage reference log signal from the compressed p-law or A-law code, anda — Internal auto-zero circuitry low pass filter which corrects for the sin x/x response of the Meets or exceeds all LSSGR and CCITT specifications decoder output and rejects signals above 3400 Hz. The re- ™ Microprocessor interface independant of frame sync ceive output is a single-ended power amplifier capable of = Low operating power—typically 60 mW driving low impedance loads. § Power-down standby mode—typically 3 mW ™@ 2 loopback test modes Block Diagram Yeu ven r + 7 [ “a2 | | wz | 1 l 1 1 | noe | ' ™ surcnen sm y > a Ky

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. . vu Connection Diagram 8 Dual-In-Line Package 2 wy, g Vea] 1 22 VEY gs GNDA 4 2 21 VFyle 3 VFR0 “TS. 20 F GS, Voca—| 4 19 FS R15 tp3ose 185“ Veco wos OR 17 f= PCM/ CNTL par—j7 3089 igh ck 086 48 15} peo ves 9 14 pat 084110 13} vez GNOD J 11 12} DBS TuH/e833-2 Top View Order Number TP3058J or TP3059J See NS Package Number J22A Pin Descriptions Symbol Function Symbol Function Vep Negative power supply pin. CLK The clock input for the switched-capacitor fil- Vep = —5V 15% ters and CODEC. Clock frequency must be GNDA Analog ground. All analog signals are refer- 768 kHz, 772 kHz, 1.024 MHz or 1.28 MHz and enced to this pin. must be synchronous with the »C system VFO Analog output of the receive power amplifier. Glock. ; This output can drive a 6002 load to +2.5V. FS Frame sync input, which starts a new Encode . , and Decode cycle. Must occur at an 8 kHz rate Voca Positive power supply voltage pin for the ana- ‘ log circuitry. Vooa = SV +5%. Must be con. to meet CCITT and LSSGR specifications. nected to Vecp. R Input from the Microprocessor READ signal, , which enables the COMBO bus drivers. May be DB7 at 7 vo on the data bus. The PCM LSB. asynchronous with FS. 06 it 6 1/0 on the data bus: w Input from the Microprocessor WRITE signal, DBS Bit 5 I/O on the data bus which enables the COMBO bus receivers. May DB4 Bit 4 1/0 on the data bus. be asynchronous with FS. GNDD _ Digital ground. All digital signals are referenced PCM/ This contro! input determines whether the infor- to this pin. CNTL mation on the data bus is PCM data or control DB3 Bit 3 1/O on the data bus. data. OB2 Bit 2 1/O on the data bus. Veco Positive power supply pin for the bus drivers. Det Bit 1 1/0 on the data bus. Veep = 5V +5%. Must be connected to Voca. DBO Bit 0 1/0 on the data bus. This is the PCM sign GSx Analog output of the transmit input amplifier. bit. Used to externally set gain. VFI Inverting input of the transmit input amplifier. VFyIt Non-inverting input of the transmit input amplifi- er. 1-57

$| Functional Description a | POWER-UP MICROPROCESSOR READING THE BUS | When power is first applied, power-on reset circuitry initializ~ The microprocessor may read either the Control Register, to o es the COMBO and sets it in the power-down mode. All verify the status of the device, or the PCM Transmit Regis- £ non-essential circuits are deactivated and the data bus out- ter. Selection is again by means of the PCM/CNTL address F | _ puts, DB0-D87, and receive power amplifier output, VFRO, input. A CNTL READ may take place at any time without are in high impedance states. restriction, during either the powered-up or powered-down The TP3058 and TP3059 are powered-up via a command to state. A PCM READ cycle normally occurs once per frame, the contro! register (see Control Register Functions). This and may ocour any time in the frame except during the FS sets the device in the standby mode with all circuitry activat- falling edge. 60 bt ape am ecoding do not begin until PCM COMBO TIMING a chip selects occur. The CLK input signal provides timing for the encode and decode logic and the switched-capacitor filters. It must be |. Control Bit Functi TABLE |. Control Bit Functions one of the frequencies listed in Table | and must be correct- Control Bits [Function =— ly selected by control bits CO and C1. FS is a syne input which starts both the Encode and Decode cycles. It must be Co, C1 Select Clock Frequency an integer sub-multiple of CLK, and must occur at an 8 kHz co C1 Frequency rate to meet CCITT and LSSGR transmission specifications. o =X 1.024 MHz CONTROL REGISTER FUNCTIONS 100.768 MHz or 0.772 MHz Writing to the contro! register (see Table |) allows the user 1 u 1.28 MHz to set the various operating states of the TP3058 and C2,C3 Digital and Analog Loopback TP3059. The control register can also be read back via the c2 3 Mode data bus to verify the current operating mode of the device. 1 X digital loopback 1. CLK Select 0 1 analog loopback Since one of three distinct clock frequencies may be 0 0 normal used, the actual frequency must be known by the device for proper operation of the switched-capacitor filters. This C4 Power-Down/Power-Up is achieved by writing control register bits CO and C1, 1 = power-down normally in the same WRITE cycle that powers-up the 0 = power-up device, and before any PCM data transfers take place. cs TP3058—Don't care (Note 1) 2. Digital Lookback TP3059 In order to establish that a valid path has been selected ~ Not; through a network, it is sometimes desirable to be able to 3 = Notimplemented pe not use send data through the network to its destination, then = Ataw with even bit inversion loop it back through the network return path to the origi- Don't Care (Note 1) nating source where the data can be verified. This loop- Now 1 Those bi oF back function can be performed in the TP3058 and hai ts are always set to 1" when reading back the control TP059 by setting control register bit C2 to 1. With C2 . set, the PCM data in the receive register will be written DATA BUS NOMENCLATURE back onto the data bus during the next PCM WRITE cy- The order of the data bus is as follows: cle. In the digital loopback mode, the receive section is set to an idle channel condition in order to maintain a low Datatype | BO | ~—iB7_—i| impedance termination at VFRO. [rom | Sint 8. Analog Loopback | contrpata_| [_@ | In the analog loopback mode, the transmit filter input is Contoidata [coor switched from the gain adjust amplifier to the receive power amplifier output, forming a unity-gain loop from the MICROPROCESSOR WRITING THE BUS receive register back to the transmit register. This mode The microprocessor may write to either the Control Register is entered by setting control register bits C2 to 0 and C3 or PCM Receive Register by first setting up the PCM/CNTL to 1. The receive power amplifier continues to drive the address bit during a WRITE cycle. A CNTL WRITE may take load in this mode. place at any time without restriction, during either the pow- 4, Power-Down/Power-Up ered-up or powered-down state. The TP3058, TP3059 may be put in the power-down A PCM WRITE cycle normally occurs once per frame, and mode by setting control register bit C4 to 1. Conversely, may occur any time in the frame except during the FS falling settng bit C4 to 0 powers-up the device. edge. PCM data is held in a register and will not update the DAC until the next FS pulse starts a new decoding cycle. 1-58

3 Absolute Maximum Ratings

& If Military/Aerospace specified devices are required, Voltage at Any Analog o please contact the National Semiconductor Sales Input or Output Voc + 0.3V to Vag —0.3V Bg Office/Distributors for availability and specifications. Voltage at Any Digital 2 GNDD to GNDA +0.3V Input or Output Voc + 0.3V to GNDD—0.3V fe Voca or Vecp to GNDD or GNDA wv Operating Temperature Range — 25°C to + 125°C Vpp to GNDD or GNDA -7v Storage Temperature Range -65°C to + 150°C Lead Temp. (Soldering, 10 sec.) 300°C ESD rating is to be determined.

Electrical Characteristics

Unless otherwise noted: Voca = Vocp = 5.0V +5%, Vag = —5V +5%, GNDD = GNDA = OV, Ta = 0°C to 70°C; typical characteristics specified at nominal supply voltages, Ta = 25°C; all digital signals are referenced to GNDD, alll analog signals are referenced to GNDA. Limits printed in BOLD characters are guaranteed for Vcca = Vocp = 5.0V +5%, Vag = —5.0V +5%; Ta = 0°C to 70°C by correlation with 100% electrical testing at Ta = 25°C. All other limits are assured by correlation with other production tests and/or product design characterizations. symbol | _Parameter_— | Gonattions | win | Typ | Max | units DIGITAL INTERFACE Vin [Weputhighvortge Te PT Vor | OutputlowVottags | pao-pe7,=2sma | To |v Vou | Outputigh votage | 80-p87,qy=25ma |e [|v in [ tnputtowGurent | GNoD<vwsvu | 3 | | na in | InputHigh Curent ns Vvsvoc | = TT 8 Tn loz Output Current in High Impedance | DBO-DB7,GNDD < Vo < Vcc. Sacomsrreer mene | Pmomowonsvecver | a | |e | ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER RoxA | OutputResistancs, GSx | Glosedtoop,unity@ain || tf 3 | Axa | Load Resistance, esq | to OxXA | Lead Gapacitanceasx | 80 AyxA | VoltageGain | exit teas | seo | || VosxA | offsetvottage | ae | 20 | oy VowxA | Gommor-ModeVottage | GMRRXA> eos | = | | as |v CMAAXA |"CommonModeRejectonfatio | octet | eo TT a PsRAXA | PowerSupplyRejection Ratio | voTest | eo || a RECEIVE POWER AMPLIFIER RonF | OuiputResistanca vFgo [TCU 8 fl FURF | loadResistance | ven =tesv | oo (| | CAF [ LoadCapacitance | 80 or Vos,O [| Outpudcorisetvotage | 200 || 200 | mv POWER DISSIPATION loco | Power-OownGurent | Nokoagwnotor) | 8 | 4.8 | ma tao | Power-DownGurent | NotoadWotety || (005 | 8 | mA loot | Astive Curent | Notoad Tg | 0. | ma * loco and Iggo are measured after first achieving a power-up state. 1-60

Unless otherwise noted, Veca = Vocp = 5.0V +5%, Vag = —5.0V +5%, GNDA = OV, Ta = 0°C to 70°C; typical character- | istics specified at Veca = Vocp = 5.0V, Vag = —5.0V, Ta = 25°C; all signals are referenced to GNDA. Timing specifications 4 are measured at Voy = 2.0V and Vo, = 0.7V. Limits printed in BOLD characters are guaranteed for Voca = Vecp = 5.0V | 9 +5%, Vag = —5.0V +5%; Ta = O°C to 70°C by correlation with 100% electrical testing at Ta = 25°C. All other limits are | & assured by correlation with other production tests and/or product design characterizations. See Definitions and Timing Conven- 3 tions for test methods information. symbol [Parameter | Conatttons | win | max | Units wo | Peiodotciock | Teo won | WidthotGiockign TT pao fs two | Widthofoiocktow TT gos tre | FiseTimeotGiock | Tt 100 ps twa | HoldTime FStowioR | PoMAEADOny | 100 | | tsar | SetUpTima RLowioFS | poMAeADOnty | 100 || tuew | HoldTime, FStowtow | Pomwrireony | too | | tsar | Set-Up Tine. wiowioFS_ | _pemwrrreony | ao || ms wan | Wisthoretigh Ps toro | DetayTimo,AtoDatavaid |= t0opr | | ts tap | FloatDelw,AtowtodeHihz | | Tt ‘sow | SetUpTine DBtowiow J Ts fs tay | HoldTimawrowtops | Ts tspwa | SetupTime, Pow/ontitonorw [| ao | tors | PerodotFS quote) | ck = tzamie [70 | ns Timing Diagram twen tec tre t src tec thor ‘tors FS twrH EF 7 tw oe Ww aie, els FO/CHTL =m 4) ae i Se oa0-087 Gn oj—{_ oman} ‘oro TL/H/8833-4 1-61

a re #| Transmission Characteristics & | Unless otherwise specified: Ta=0°C to 70°C, Voca=Vccp=5V +5%, Vap= ~SV 5%, GNDD=GNDA=OV, f = 1.02 kHz, | Vin=0.d8mO, transmit input amplifier connected for unity-gain non-inverting. Limits printed in BOLD characters are guaranteed ry for Veca=Vocn=5.0V +5% and Vag= —5.0V +5%; Ta=0°C to 70°C by correlation with 100% testing at Ta = 25°C. All other 8 limits are assured by correlation with production tests and/or product design and characterization. a F |_symbot] Parameter Conations | in| typ | max | units AMPLITUDE RESPONSE Absolute Levels Nominal 0 dBm0 Level is 4 dBm (6002) 0 dBmo TP3058 1.2276 Vrms: TP3059 1.2276 Vrms ‘Max Maximum Overload Level TP3058 (+3.17 dBm0) 2.501 Vek TP3059 (+ 3.14 dBm0) 2.492 Vex Gxa Transmit Gain, Absolute Ta = 25°C, Voca = Veep = 5.0V, Vag = —5.0V @B Input at GSx = 0 dBm0 at 1020 Hz Gyr Transmit Gain, f= 16Hz —40 dB Relative to Gxa f = 50Hz —30 dB f = 60Hz —26 dB f = 200Hz -1.8 —0.1 dB f = 300 Hz-3000 Hz 0.15 0.15 dB f = 3300 Hz -0.35 0.1 dB f = 3400 Hz -0.7 ° dB f = 4000 Hz —14 dB f = 4600 Hz and Up, Measure -32 dB Response from 0 Hz to 4000 Hz Gxat | Absolute Transmit Gain Relative to Gxa, ‘i i dB Variation with Temperature Gxav Absolute Transmit Gain Relative to Gxa 6B Variation with Supply Voltage GxpL__| Transmit Gain Variation Sinusoidal Test Method with Level Reference Level = —10 dBm0 VFxI+ = —40 dBm0 to +3 dBm0 dB VFxl+ = —50 dBm0 to — 40 dBmo 0B VFxI+ = —55 dBm0 to —50 dBmO 0B Gra Receive Gain, Absolute Ta = 25°C, Voca = Veco = 5V, Vag = —5V Input = Digital Code Sequence for dB 0 dBm0 Signal at 1020 Hz Gar Receive Gain, f = 0 Hz to 3000 Hz —0.15 0.15 dB Relative to Gra f = 3300 Hz -0.35 0.05 dB f = 3400 Hz -0.7 ° dB f = 4000 Hz —14 dB Grat | Absolute Receive Gain Relative to Gag nan i dB Variation with Temperature | Grav Absolute Receive Gain Relative to Gna 4B Variation with Supply Voltage Gra Receive Gain Variation Sinusoidal Test Method; Reference Input PCM with Level Code Corresponds to an Ideally Encoded PCM Level = —40 dBm0 to +3 dBm0 dB = —50dBm0 to —40 dBmo dB = —55 dBm0 to —50 dBm0 dB Vao [Receive OutputDriveLevel [r= eon | 2 | os |v 1-62

. 3 uv Transmission Characteristics (continues) g Unless atherwise specified: Ta=0°C to 70°C, Voca=Voop=5V +5%, Vaa= —5V +5%,GNDD=GNDA=0V, f =1.02 kHz, | & Vin=0 dBm0, transmit input amplifier connected for unity-gain non-inverting, Limits printed in BOLD characters are guaranteed | “y for Voca=Vocp=5.0V +5% and Vag= —5.0V +5%; Ta = 0°C to 70°C by correlation with 100% testing at Ta = 26°C. Al | od other limits are assured by correlation with production tests and/or product design and characterization. s a Symbol Conditions [ win [ typ [ max [ units | © ENVELOPE DELAY DISTORTION WITH FREQUENCY Oxa__| Transmit Delay, Absolute [t= wore Tf a0 | ats [ns Dxr | Transmit Delay, Relative to Dxq f = 500 Hz-600 Hz 195 | 220 | us f = 600 Hz-800 Hz 120 145 BS f = 800 Hz-1000 Hz 50 75 BS f = 1000 Hz-1600 Hz 20 40 us f = 1600 Hz-2600 Hz 55 75 BS f = 2600 Hz-2800 Hz 80 105 BS f= 2800 Hz~3000 Hz 130 | 155 | ps Dra ___ | Receive Delay, Absolute f= 1600Hz |_| 100 | 200 | us Dra Receive Delay, Relative to Dra 1 = 500 Hz-1000 Hz —25 ps 4 = 1000 Hz~1600 Hz —20 BS f = 1600 Hz-2600 Hz 7 | 90 | ys f = 2600 Hz-2800 Hz 100 125 BS f = 2800 Hz-3000 Hz 145 175 BS NOISE Nxc___| Transmit Noise, C Message Weighted | TP3058, (Note 1) |__| 12 | 18 | aamco Nxp__| Transmit Noise, P Message Weighted | TP3059, (Note 1) |_| -74 | -68 | aamop Nac | Receive Noise, C Message Weighted | TP3058, PCM Code Equals Alternating ti 7" dBrnCo Positive and Negative Zero Nap __| Receive Noise, P Message Weighted _| 1P3059, PCM Code Equals Positive Zero |__| —82 | -79 | dBm0p Nas Noise, Single Frequency f = 0 kHz to 100 kHz, Loop Around mo Measurement, VFxi+ = OV PPSRx | Positive Power Supply Voca = Veco = 8.0 Vp¢ +100 mVrms asc Rejection, Transmit f = 0 kH2~50 kHz (Note 2) NPSRx | Negative Power Supply Vag = ~5.0 Vpg +100 mVrms Bc Rejection, Transmit {= 0 kH2-50 kHz (Note 2) PPSRa | Positive Power Supply PCM Code Equals Positive Zero for Rejection, Receive TP3058 and TP3059 Voo = 5.0 Vp +100 mVrms f = 0 Hz-4000 Hz 40 dBC {= 4 kHz-25 kHz 40 0B f = 25 kHz~50 kHz 36 dB NPSRR | Negative Power Supply POM Code Equals Positive Zero for Rejection, Receive P3058 and TP3059 Vag = —5.0 Voc +100 mVrms f= 02-4000 Hz dBC f = 4kHz-25 kHz dB f = 25 kHz-50 kHz dB SOS Spurious Out-of-Band Signals 0 dBm0, 300 Hz-3400 Hz Input Applied to at the Channel Output VFx|+, Measure Individual Image Signals at VFRO

4600 Hz-7600 Hz dB

7600 Hz~8400 Hz dB

8400 Hz-100,000 Hz 8

w $| Transmission Characteristics (continues) | <All Devices) Unless otherwise specified: Ta=0°C to 70°C, Voca=Voco=5V +5%, Vag= —5V £5%, GNDD= GNDA=OV, es | {= 1.02 kHz, Viy=0 dBm0, transmit input amplifier connected for unity-gain non-inverting. Limits printed in BOLD charactors rey are guaranteed for Voc=5.0V +5% and Vgg= —5.0V +5%; Ta=0°C to 70°C by correlation with 100% testing at Ta=25°C. $ | Allother limits are assured by correlation with production tests and/or product design and characterization. a F | symbor[ Parameter | Conattions | n | typ | max | unite DISTORTION STDx Signal to Total Distortion Sinusoidal Test Method (Note 3) STDR Transmit or Receive Level = 3.0 dBm0 33 dB Half-Channel = 0 dBm0 to —30 dBmo 36 dB = -40dBm0 = XMT 29 dB RCV 30 CT) = -55dBm0 = XMT 14 aB RCV 15 dB SFDx Single Frequency Distortion, , dB Transmit SFDR Single Frequency Distortion, dB Receive IMD Intermodulation Distortion VFxl+ = —4dBm0 to —21 dBmd, ae Two Frequencies in the Range

300 Hz-3400 Hz

CTx.R Transmit to Receive Crosstalk | f = 300 Hz-3000 Hz at0 dBmO 0 dBmo Transmit Level Transmission Level dB Steady PCM Receive Code CTp.x | Receive to Transmit Crosstalk | { = 300 H2-3000 Hz at OdBm0 Transmit Level 4B 0 dBm0 Receive Level (Note 2) Note 1: Measured by extrapolation from the distortion test result. At —50 d8m0 Note 2: CTp.x, PPSRx, and NPSRx are measured with a —50 dBm0 activation signal applied at VF xi*. Note 3: Using C message weighted filter. Note 4: Must be 125 ys to meet CCITT and LSSGR specifications. Encoding Format At Data Bus Output TP3059 Tpaose True A-Law, C5 = 0 is (Includes Even Bit Inversion) MSB LsB | MSB LsB Vn=+Ful-Scale | 1 0 0 0 0 0 0 Of 1 0 41 0 1 0 1 0 _ 1404 4 4 4 4 FP 4 4°04 0 4 0°45 Vin = ov o 444 4 41 4 tY/0 4°06 4 0 4 0 41 Vin= —FulkScale | 0 0 0 0 0 0 0 O}|O O 1 0 7 O 1 9 1-64

og . 7 uv Applications Information T Pad Attenuator 8 POWER SUPPLIES wo Pat mt 1 S While the pins of the TP3058/9 family are well protected a against electrical misuse, however, it is recommended that ' B the standard CMOS practice be followed, ensuring that n { 3 ground is connected to the device before any other connec- I o tions are made. In applications where the printed circuit | board may be plugged into a “hot” socket with power and | eae ES | clocks already present, an extra long ground pin in the con- nector should be used. GNDA and GNDD MUST be con- V nected together adjacent to each COMBO, not on the con- nector or backplane wiring. TUH/B893-5 All ground connections to each device should meet at a ri -21(§2*1) _ 2 973 (_N ‘common point as close as possible to the GNDA pin. This (ie = i) (e ~ i) minimizes the interaction of ground return currents flowing pe = 2ve7z3 (—N through a common bus impedance. 0.1 uF supply decou- ( = ) pling capacitors should be connected from this common Where: N= « [ POWEAIN ground point to Vega and Vep. POWER OUT For best performance, the ground point of each COMBO on and a card should be connected to a common card ground in s-2 star formation, rather than via a ground bus. This common 22 ground point should be decoupled to Voc and Vag with 10 Also: 2 = i2scZoc BF capacitors. Where Zgc = Impedance with short circuit termination The positive power supply to the bus drivers, Vocp, is pro- and Zoc = Impedance with open circuit termination vided on a separate pin from the positive supply for the a-Pad Attenuator COMBO circuits to minimize noise injection when driving the ___ bus. Voca and Vecp MUST be connected together close to so Rs 7 1 the COMBO at the point where the 0.1 .F decoupling ca- pacitor is connected. | layout techniques. I RECEIVE GAIN ADJUSTMENT | For applications where a TP3050 family CODEC/filter re- -----4 ceive output must drive a 6002 load, but a peak swing lower yy than +2.5V is required, the receive gain can be easily ad- justed by inserting a matched T-pad or 7-pad at the output TL/H/8833-6 as shown in Figure 4. Table Il lists the required resistor val- TZE (N21 ues for 6002 terminations. As these are generally non-stan- B= (“2 ) dard values, the equations can be used to compute the at- N2-1 tenuation of the closest practical set of resistors. It may be Ra = 21 (es ONS Fa ) necessary to use unequal values for the R1 or Ra arms of FIGURE 4. Receive Gain Adjustment the attenuators to achieve a precise attenuation. Generally for Matched Loads it is tolerable to allow a small deviation of the input imped- ance from nominal while still maintaining a good return loss. For example a 30 dB return loss against 6000 is obtained if the output impedance of the attenuator is in the range 2820. to 3192 {assuming a perfect transformer). 1-65

Interrupt to the processor, prompting it to generate a PCM READ and PCM WRITE cycle sometime during the next frame period.

1.28 MHz OR

FIGURE 5. Typical Application