TP3057WM

TP3054 NSC | Alldatasheet

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Y Complete CODEC and filtering system (COMBO) including: Ð Transmit high-pass and low-pass filtering Ð Receive low-pass filter with sin x/x correction Ð Active RC noise filters Ð m-law or A-law compatible COder and DECoder Ð Internal precision voltage reference Ð Serial I/O interface Ð Internal auto-zero circuitry Y m-law, 16-pinÐTP3054 Y A-law, 16-pinÐTP3057 Y Designed for D3/D4 and CCITT applications Y g5V operation Y Low operating powerÐtypically 50 mW Y Power-down standby modeÐtypically 3 mW Y Automatic power-down Y TTL or CMOS compatible digital interfaces Y Maximizes line interface card circuit density Y Dual-In-Line or surface mount packages Y See also AN-370, ‘‘Techniques for Designing with CODEC/Filter COMBO Circuits’’ Connection Diagrams Dual-In-Line Package TL/H/5510–1 Top View Order Number TP3054J or TP3057J See NS Package Number J16A Order Number TP3054N or TP3057N See NS Package Number N16A Order Number TP3054WM or TP3057WM See NS Package Number M16B Plastic Chip Carriers TL/H/5510–10 Top View Order Number TP3057V See NS Package Number V20A COMBOÉ and TRI-STATE É are registered trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M125/Printed in U. S. A.

FIGURE 1 TL/H/5510–2 Pin Description Symbol Function VBB Negative power supply pin. VBB eb 5V g5%. GNDA Analog ground. All signals are referenced to this pin. VFRO Analog output of the receive power ampli- fier. VCC Positive power supply pin. VCC ea 5V g5%. FSR Receive frame sync pulse which enables BCLKR to shift PCM data into D R.F S R is an 8 kHz pulse train. See Figures 2 and 3 for timing details. DR Receive data input. PCM data is shifted into D R following the FS R leading edge. BCLKR/CLKSEL The bit clock which shifts data into D R af- ter the FS R leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLK X is used for both transmit and re- ceive directions (see Table I). MCLKR/PDN Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLK X, but Symbol Function should be synchronous with MCLK X for best per- formance. When MCLK R is connected continu- ously low, MCLK X is selected for all internal tim- ing. When MCLK R is connected continuously high, the device is powered down. MCLKX Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLK R. Best performance is realized from synchronous operation. FSX Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on D X.F S X is an 8 kHz pulse train, see Figures 2 and 3 for timing details. BCLKX The bit clock which shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLK X. DX The TRI-STATE É PCM data output which is en- abled by FS X. TSX Open drain output which pulses low during the encoder time slot. GSX Analog output of the transmit input amplifier. Used to externally set gain. VFXIb Inverting input of the transmit input amplifier. VFXIa Non-inverting input of the transmit input amplifi- er.

When power is first applied, power-on reset circuitry initializ- es the COMBO and places it into a power-down state. All non-essential circuits are deactivated and the D X and VF RO outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLK R/PDN pin and FSX and/or FS R pulses must be pres- ent. Thus, 2 power-down control modes are available. The first is to pull the MCLK R/PDN pin high; the alternative is to hold both FS X and FS R inputs continuously lowÐthe device will power-down approximately 1 ms after the last FS X or FSR pulse. Power-up will occur on the first FS X or FS R pulse. The TRI-STATE PCM data output, D X, will remain in the high impedance state until the second FS X pulse. SYNCHRONOUS OPERATION For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive di- rections. In this mode, a clock must be applied to MCLK X and the MCLK R/PDN pin can be used as a power-down control. A low level on MCLK R/PDN powers up the device and a high level powers down the device. In either case, MCLK X will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be ap- plied to BCLK X and the BCLK R/CLKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. With a fixed level on the BCLK R/CLKSEL pin, BCLK X will be selected as the bit clock for both the transmit and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLK CLKSEL. In this synchronous mode, the bit clock, BCLK X, may be from 64 kHz to 2.048 MHz, but must be synchro- nous with MCLK Each FS X pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled D X output on the positive edge of BCLK X. After 8 bit clock periods, the TRI-STATE D X output is returned to a high impedance state. With an FS R pulse, PCM data is latched via the D R input on the negative edge of BCLK X (or BCLKR if running). FS X and FS R must be synchronous with MCLKX/R. TABLE I. Selection of Master Clock Frequencies BCLKR/CLKSEL Master Clock Frequency Selected TP3057 TP3054 Clocked 2.048 MHz 1.536 MHz or

1.544 MHz

0 1.536 MHz or 2.048 MHz 1 2.048 MHz 1.536 MHz or For asynchronous operation, separate transmit and receive clocks may be applied. MCLK X and MCLK R must be 2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the TP3054, and need not be synchronous. For best transmis- sion performance, however, MCLK R should be synchronous with MCLK X, which is easily achieved by applying only static logic levels to the MCLK R/PDN pin. This will automatically connect MCLK X to all internal MCLK R functions (see Pin Description). For 1.544 MHz operation, the device automati- cally compensates for the 193rd clock pulse each frame. FS X starts each encoding cycle and must be synchronous with MCLK X and BCLK X.F S R starts each decoding cycle and must be synchronous with BCLK R. BCLK R must be a clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLK X and BCLK R may operate from 64 kHz to 2.048 MHz. SHORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FS X and FS R, must be one bit clock period long, with timing relationships specified in Figure 2 . With FS X high during a falling edge of BCLK X, the next rising edge of BCLKX enables the D X TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge dis- ables the D X output. With FS R high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLK R latches in the sign bit. The following seven falling edges latch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode. LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FS X and FS R, must be three or more bit clock periods long, with timing relationships specified in Figure 3 . Based on the transmit frame sync, FS X, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a mini- mum of 160 ns. The D X TRI-STATE output buffer is enabled with the rising edge of FS X or the rising edge of BCLK X, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLK X rising edges clock out the remaining seven bits. The D X output is disabled by the falling BCLK X edge following the eighth rising edge, or by FSX going low, whichever comes later. A rising edge on the receive frame sync pulse, FS R, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLK R (BCLKX in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode. In applications where the LSB bit is used for signalling with FS R two bit clock periods long, the decoder will interpret the lost LSB as ‘‘ (/2’’ to minimize noise and distortion.

Functional Description (Continued) TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4 . The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be real- ized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-ca- pacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to m-law (TP3054) or A-law (TP3057) coding conventions. A preci- sion voltage reference is trimmed in manufacturing to pro- vide an input overload (t MAX) of nominally 2.5V peak (see table of Transmission Characteristics). The FS X frame sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through D X at the next FS X pulse. The total encoding delay will be ap- proximately 165 ms (due to the transmit filter) plus 125 ms (due to encoding delay), which totals 290 ms. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3057) or m-law (TP3054) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/ power amplifer capable of driving a 600 X load to a level of 7.2 dBm. The receive section is unity-gain. Upon the occur- rence of FS R, the data at the D R input is clocked in on the falling edge of the next eight BCLK R (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins, and 10 ms later the decoder DAC output is updated. The total decoder delay is E 10 ms (decoder update) plus 110 ms (filter delay) plus 62.5 ms( (/2 frame), which gives approximately 180 ms.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. V CC to GNDA 7V VBB to GNDA b7V Voltage at any Analog Input or Output V CCa0.3V to V BBb0.3V Voltage at any Digital Input or Output V CCa0.3V to GNDA b0.3V Operating Temperature Range b25§Ct o a 125§C Storage Temperature Range b65§Ct o a150§C Lead Temperature (Soldering, 10 seconds) 300 §C ESD (Human Body Model) 2000V Latch-Up Immunity e 100 mA on any Pin Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V CC e 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACE VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.2 V VOL Output Low Voltage D X,I Le3.2 mA 0.4 V SIGR,I Le1.0 mA 0.4 V TSX,I Le3.2 mA, Open Drain 0.4 V VOH Output High Voltage D X,I Heb3.2 mA 2.4 V SIGR,I Heb1.0 mA 2.4 V IIL Input Low Current GNDA sVINsVIL, All Digital Inputs b10 10 mA IIH Input High Current V IHsVINsVCC b10 10 mA IOZ Output Current in High Impedance D X, GNDA sVOsVCC b10 10 mA State (TRI-STATE) ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES) IIXA Input Leakage Current b2.5VsVsa2.5V, VF XIa or VF XIb b200 200 nA RIXA Input Resistance b2.5VsVsa2.5V, VF XIa or VF XIb 10 M X ROXA Output Resistance Closed Loop, Unity Gain 1 3 X RLXA Load Resistance GS X 10 k X CLXA Load Capacitance GS X 50 pF VOXA Output Dynamic Range GS X,R Lt10 k X b2.8 2.8 V AVXA Voltage Gain VF XIa to GS X 5000 V/V FUXA Unity Gain Bandwidth 1 2 MHz VOSXA Offset Voltage b20 20 mV VCMXA Common-Mode Voltage CMRRXA l 60 dB b2.5 2.5 V CMRRXA Common-Mode Rejection Ratio DC Test 60 dB PSRRXA Power Supply Rejection Ratio DC Test 60 dB ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES) RORF Output Resistance Pin VF RO1 3 X RLRF Load Resistance VF ROeg2.5V 600 X CLRF Load Capacitance 500 pF VOSRO Output DC Offset Voltage b200 200 mV POWER DISSIPATION (ALL DEVICES) ICC0 Power-Down Current No Load (Note) 0.5 1.5 mA IBB0 Power-Down Current No Load (Note) 0.05 0.3 mA ICC1 Power-Up Active Current No Load 5.0 9.0 mA IBB1 Power-Up Active Current No Load 5.0 9.0 mA Note: ICC0 and I BB0 are measured after first achieving a power-up state.

Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V CC e 5.0V, V BB eb 5.0V, T A e 25§C. All timing parameters are measured at V OH e 2.0V and V OL e 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units 1/tPM Frequency of Master Clocks Depends on the Device Used and the 1.536 MHz BCLKR/CLKSEL Pin. 1.544 MHz MCLKX and MCLK R 2.048 MHz tRM Rise Time of Master Clock MCLK X and MCLK R 50 ns tFM Fall Time of Master Clock MCLK X and MCLK R 50 ns tPB Period of Bit Clock 485 488 15725 ns tRB Rise Time of Bit Clock BCLK X and BCLK R 50 ns tFB Fall Time of Bit Clock BCLK X and BCLK R 50 ns tWMH Width of Master Clock High MCLK X and MCLK R 160 ns tWML Width of Master Clock Low MCLK X and MCLK R 160 ns tSBFM Set-Up Time from BCLK X High First Bit Clock after the Leading 100 ns to MCLK X Falling Edge Edge of FS X tSFFM Set-Up Time from FS X High Long Frame Only 100 ns to MCLK X Falling Edge tWBH Width of Bit Clock High V IHe2.2V 160 ns tWBL Width of Bit Clock Low V ILe0.6V 160 ns tHBFL Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync tHBFS Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync tSFB Set-Up Time from Frame Sync Long Frame Only 80 ns to Bit Clock Low tDBD Delay Time from BCLK X High Load e150 pF plus 2 LSTTL Loads 0 140 ns to Data Valid tDBTS Delay Time to TS X Low Load e150 pF plus 2 LSTTL Loads 140 ns tDZC Delay Time from BCLK X Low to C Le0 pF to 150 pF 50 165 ns Data Output Disabled tDZF Delay Time to Valid Data from C Le0 pF to 150 pF 20 165 ns FSX or BCLK X, Whichever Comes Later tSDB Set-Up Time from D R Valid to 50 ns BCLKR/X Low tHBD Hold Time from BCLK R/X Low to 50 ns DR Invalid tSF Set-Up Time from FS X/R to Short Frame Sync Pulse (1 Bit Clock 50 ns BCLKX/RLow Period Long) tHF Hold Time from BCLK X/R Low Short Frame Sync Pulse (1 Bit Clock 100 ns to FS X/R Low Period Long) tHBFl Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns Bit Clock Low to Frame Sync Clock Periods Long) (FS X or FS R) tWFL Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns Sync Pulse (Low Level)

FIGURE 2. Short Frame Sync Timing

FIGURE 3. Long Frame Sync Timing

Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, V IN e 0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V CC e 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE Absolute Levels Nominal 0 dBm0 Level is 4 dBm (Definition of Nominal Gain) (600 X) 0 dBm0 1.2276 Vrms tMAX Virtual Decision Valve Defined Max Overload Level Per CCITT Rec. G711 TP3054 (3.17 dBm0) 2.501 V PK TP3057 (3.14 dBm0) 2.492 V PK GXA Transmit Gain, Absolute T Ae25§C, V CCe5V, V BBeb5V Input at GS Xe0 dBm0 at 1020 Hz TP3054/57 b0.15 0.15 dB GXR Transmit Gain, Relative to G XA fe16 Hz b40 dB fe50 Hz b30 dB fe60 Hz b26 dB fe200 Hz b1.8 b0.1 dB fe300 Hz b3000 Hz b0.15 0.15 dB fe3300 Hz b0.35 0.05 dB fe3400 Hz b0.7 0 dB fe4000 Hz b14 dB fe4600 Hz and Up, Measure b32 dB Response from 0 Hz to 4000 Hz with Temperature with Supply Voltage GXRL Transmit Gain Variations with Sinusoidal Test Method Level Reference Level eb10 dBm0 VFXIa eb40 dBm0 to a3 dBm0 b0.2 0.2 dB VFXIa eb50 dBm0 to b40 dBm0 b0.4 0.4 dB VFXIa eb55 dBm0 to b50 dBm0 b1.2 1.2 dB GRA Receive Gain, Absolute T Ae25§C, V CCe5V, V BBeb5V InputeDigital Code Sequence for 0 dBm0 Signal at 1020 Hz TP3054/57 b0.15 0.15 dB GRR Receive Gain, Relative to G RA fe0 Hz to 3000 Hz b0.15 0.15 dB fe3300 Hz b0.35 0.05 dB fe3400 Hz b0.7 0 dB fe4000 Hz b14 dB with Temperature with Supply Voltage GRRL Receive Gain Variations with Sinusoidal Test Method; Reference Level Input PCM Code Corresponds to an Ideally Encoded PCM Level eb40 dBm0 to a3 dBm0 b0.2 0.2 dB eb50 dBm0 to b40 dBm0 b0.4 0.4 dB eb55 dBm0 to b50 dBm0 b1.2 1.2 dB VRO Receive Output Drive Level R Le600X b2.5 2.5 V

Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, V IN e 0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V CC e 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units ENVELOPE DELAY DISTORTION WITH FREQUENCY DXA Transmit Delay, Absolute f e1600 Hz 290 315 ms DXR Transmit Delay, Relative to D XA fe500 Hz–600 Hz 195 220 ms fe600 Hz–800 Hz 120 145 ms fe800 Hz–1000 Hz 50 75 ms fe1000 Hz–1600 Hz 20 40 ms fe1600 Hz–2600 Hz 55 75 ms fe2600 Hz–2800 Hz 80 105 ms fe2800 Hz–3000 Hz 130 155 ms DRA Receive Delay, Absolute f e1600 Hz 180 200 ms DRR Receive Delay, Relative to D RA fe500 Hz–1000 Hz b40 b25 ms fe1000 Hz–1600 Hz b30 b20 ms fe1600 Hz–2600 Hz 70 90 ms fe2600 Hz–2800 Hz 100 125 ms fe2800 Hz–3000 Hz 145 175 ms NOISE NXC Transmit Noise, C Message TP3054 12 15 dBrnC0 Weighted NXP Transmit Noise, P Message TP3057 b74 b67 dBm0p Weighted NRC Receive Noise, C Message PCM Code is Alternating Positive Weighted and Negative Zero Ð TP3054 8 11 dBrnC0 NRP Receive Noise, P Message PCM Code Equals Positive Weighted Zero Ð TP3057 b82 b79 dBm0p NRS Noise, Single Frequency f e0 kHz to 100 kHz, Loop Around b53 dBm0 Measurement, VF XIa e0 Vrms PPSRX Positive Power Supply Rejection, VF XIa eb 50 dBm0 Transmit V CCe5.0 V DCa100 mVrms fe0 kHz–50 kHz (Note 2) 40 dBC NPSRX Negative Power Supply Rejection, VF XIa eb 50 dBm0 Transmit V BBeb5.0 V DCa100 mVrms fe0 kHz–50 kHz (Note 2) 40 dBC PPSRR Positive Power Supply Rejection, PCM Code Equals Positive Zero Receive V CCe5.0 V DCa100 mVrms Measure VF R0 fe0 Hz–4000 Hz 40 dBC fe4 kHz–25 kHz 40 dB fe25 kHz–50 kHz 36 dB NPSRR Negative Power Supply Rejection, PCM Code Equals Positive Zero Receive V BBeb5.0 V DCa100 mVrms Measure VF R0 fe0 Hz–4000 Hz 40 dBC fe4 kHz–25 kHz 40 dB fe25 kHz–50 kHz 36 dB

Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, V IN e 0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at V CC e 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units SOS Spurious Out-of-Band Signals Loop Around Measurement, 0 dBm0, b30 dB at the Channel Output 300 Hz to 3400 Hz Input PCM Code Applied at D R.

4600 Hz–7600 Hz b30 dB

7600 Hz–8400 Hz b40 dB

8400 Hz–100,000 Hz b30 dB

STDX Signal to Total Distortion Sinusoidal Test Method (Note 3) STDR Transmit or Receive e3.0 dBm0Level 33 dBC Half-Channel e0 dBm0 to b30 dBm0 36 dBC XMTeb40 dBm0 29 dBC RCV 30 dBC XMTeb55 dBm0 14 dBC RCV 15 dBC SFDX Single Frequency Distortion, b46 dB Transmit SFDR Single Frequency Distortion, b46 dB Receive IMD Intermodulation Distortion Loop Around Measurement, b41 dB VFXa eb4 dBm0 to b21 dBm0, Two Frequencies in the Range

300 Hz–3400 Hz

CTX-R Transmit to Receive Crosstalk, f e300 Hz–3400 Hz 0 dBm0 Transmit Level D ReQuiet PCM Code b90 b75 dB CTR-X Receive to Transmit Crosstalk, f e300 Hz–3400 Hz, VF XIeMultitone b90 b70 dB 0 dBm0 Receive Level (Note 2) ENCODING FORMAT AT D X OUTPUT TP3054 TP3057 m-Law A-Law (Includes Even Bit Inversion) VIN (at GS X)ea Full-Scale 10000000 10101010 VIN (at GS X)e0V 11111111 11010101 Ð01111111 01010101 VIN (at GS X)ebFull-Scale 00000000 00101010 Note 1: Measured by extrapolation from the distortion test result at b50 dBm0. Note 2: PPSRX, NPSR X, and CT R-X are measured with a b50 dBm0 activation signal applied to VF XIa. Note 3: Devices are measured using C message weighted filter for m-Law and psophometric weighted filter for A-Law.

While the pins of the TP305X family are well protected against electrical misuse, it is recommended that the stan- dard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a ‘‘hot’’ socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 mF supply decou- pling capacitors should be connected from this common ground point to V CC and V BB, as close to the device as possible. For best performance, the ground point of each CODEC/ FILTER on a card should be connected to a common card ground in star formation, rather than via a ground bus. This common ground point should be decoupled to V CC and VBB with 10 mF capacitors. RECEIVE GAIN ADJUSTMENT For applications where a TP305X family CODEC/filter re- ceive output must drive a 600 X load, but a peak swing lower than g2.5V is required, the receive gain can be easily ad- justed by inserting a matched T-pad or q-pad at the output. Table II lists the required resistor values for 600 X termina- tions. As these are generally non-standard values, the equa- tions can be used to compute the attenuation of the closest practical set of resistors. It may be necessary to use un- equal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation. Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a good return loss. For example a 30 dB return loss against 600 X is obtained if the output imped- ance of the attenuator is in the range 282 X to 319 X (as- suming a perfect transformer). T-Pad Attenuator R1 e Z1 N2 a 1 N2 b 1 J b 20Z1.Z2 N N2 b 1 J R2 e 20Z1.Z2 N N2 b 1 J Where: N e POWER IN POWER OUT and S e Also: Z e 0ZSC # ZOC Where Z SC e impedance with short circuit termination and Z OC e impedance with open circuit termination q-Pad Attenuator TL/H/5510–5 R3 e Z1.Z2 2 # N2 b 1 N J R3 e Z1 N2 b 1 N2 b 2NS a 1 J Note: See Application Note 370 for further details.

Applications Information (Continued) TABLE II. Attentuator Tables for Z1 eZ2e300X (All Values in X) dB R1 R2 R3 R4 0.1 1.7 26k 3.5 52k 0.2 3.5 13k 6.9 26k 0.4 6.9 6.5k 13.8 13k 2 34.4 1.3k 70 2.6k 3 51.3 850 107 1.8k 4 68 650 144 1.3k 5 84 494 183 1.1k 6 100 402 224 900 7 115 380 269 785 8 379 284 317 698 9 143 244 370 630 10 156 211 427 527 11 168 184 490 535 12 180 161 550 500 13 190 142 635 473 14 200 125 720 450 15 210 110 816 430 16 218 98 924 413 18 233 77 1.17k 386 20 246 61 1.5k 366 Typical Synchronous Application TL/H/5510–6 Note 1: XMIT gain e20clog R1aR2 R2 J where (R1 aR2) l10 K X. FIGURE 4

Connection Diagrams (Continued) Plastic Chip Carrier TL/H/5510–7 Top View Order Number TP3057V See NS Package Number V20A

Physical Dimensions inches (millimeters) Cavity Dual-In-Line Package (J) Order Number TP3054J or TP3057J Molded Small Outline Package (WM) Order Number TP3054WM or TP3057WM

TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO Family Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number TP3054N or TP3057N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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