TP3054-X_15 TI1 | Alldatasheet

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TP3054-X,TP3057-X www.ti.com SNOSBY2C –MARCH 2005–REVISED APRIL 2013 ExtendedTemperatureSerialInterfaceCODEC/FilterCOMBO Family Check forSamples: TP3054-X,TP3057-X 1FEATURES DESCRIPTION The TP3054, TP3057 familyconsistsofμ-lawand A- 2• −40°C to+85°C Operation law monolithicPCM CODEC/filtersutilizingthe A/D• Complete CODEC and FilteringSystem and D/A conversionarchitectureshown inFigure3,(COMBO) Including: and a serialPCM interface.The devices are – TransmitHigh-Pass and Low-Pass Filtering fabricatedusing TI'sadvanced double-polyCMOS process(microCMOS).– Receive Low-Pass FilterwithSin x/x Correction The encode portionof each deviceconsistsof an inputgain adjustamplifier,an activeRC pre-filter– ActiveRC Noise Filters which eliminatesvery high frequencynoisepriorto– μ-Law or A-Law Compatible COder and enteringa switched-capacitorband-pass filterthatDECoder rejectssignalsbelow 200 Hz and above 3400 Hz. – InternalPrecisionVoltageReference Also included are auto-zero circuitryand a companding coder which samples the filteredsignal– SerialI/OInterface and encodes itin the companded μ-law or A-law– InternalAuto-ZeroCircuitry PCM format.The decode portionof each device

  • μ-Law,16-Pin-TP3054 consistsofan expandingdecoder,whichreconstructs theanalogsignalfromthecompanded μ-laworA-law• A-Law, 16-Pin-TP3057 code,a low-passfilterwhich correctsforthe sinx/x• Designed forD3/D4 and CCITT Spplications response of the decoder outputand rejectssignals• ±5V Operation above 3400 Hz followedby a single-endedpower
  • Low OperatingPower -Typically50 mW amplifiercapableofdrivinglowimpedance loads.The devices requiretwo 1.536 MHz, 1.544 MHz or• Power-Down Standby Mode -Typically3 mW 2.048MHz transmitand receivemasterclocks,which• Automatic Power-Down may be asynchronous;transmitand receive bit
  • TTL or CMOS Compatible DigitalInterfaces clocks,which may varyfrom 64 kHz to 2.048 MHz; and transmitand receiveframe sync pulses.The• Maximizes LineInterfaceCard CircuitDensity timingof the frame sync pulsesand PCM data is• Dual-In-Lineor PCC SurfaceMount Packages compatiblewithbothindustrystandardformats.
  • See alsoAN-370,“Techniques forDesigning withCODEC/FilterCOMBO Circuits” (SNLA136 ) Connection Diagram Figure1. PlasticChip Carriers(Top View) Figure2.Dual-In-LinePackage (Top View) Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

TP3054-X,TP3057-X SNOSBY2C –MARCH 2005–REVISED APRIL 2013 www.ti.com Block Diagram Figure3. PIN DESCRIPTIONS Symbol Function VBB Negativepower supplypin. VBB = −5V ±5%. GNDA Analogground.Allsignalsarereferencedtothispin. VF R O Analogoutputofthereceivepower amplifier. VCC Positivepower supplypin. VCC = +5V ±5%. ReceiveframesyncpulsewhichenablesBCLK R toshiftPCM dataintoD R .FS R isan 8 kHzFS R pulsetrain.See Figure4 and Figure5 fortimingdetails. D R Receivedatainput.PCM dataisshiftedintoD R followingtheFS R leadingedge. The bitclockwhichshiftsdataintoD R aftertheFS R leadingedge.May varyfrom64 kHz to receivedirections(seeTable1). MCLK X,butshouldbe synchronouswithMCLK X forbestperformance.When MCLK R isMCLK R /PDN connectedcontinuouslylow,MCLK X isselectedforallinternaltiming.When MCLK R isconnected continuouslyhigh,thedeviceispowered down. TransmitframesyncpulseinputwhichenablesBCLK X toshiftoutthePCM dataon D X.FS X isFS X an 8 kHz pulsetrain,see Figure4 and Figure5 fortimingdetails. The bitclockwhichshiftsoutthePCM dataon D X.May varyfrom64 kHz to2.048MHz, butmustBCLK X be synchronouswithMCLK X.

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TP3054-X,TP3057-X www.ti.com SNOSBY2C –MARCH 2005–REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Symbol Function D X The TRI-STATE PCM dataoutputwhichisenabledby FS X. TS X Open drainoutputwhichpulseslowduringtheencodertimeslot. GS X Analogoutputofthetransmitinputamplifier.Used toexternallysetgain. VF XI− Invertinginputofthetransmitinputamplifier. VF XI+ Non-invertinginputofthetransmitinputamplifier. FunctionalDescription POWER-UP When power isfirstapplied,power-on resetcircuitryinitializesthe COMBO and placesitintoa power-down state.Allnon-essentialcircuitsaredeactivatedand theD X and VF R O outputsareputinhighimpedance states. To power-upthedevice,a logicallow levelorclockmust be appliedtotheMCLK R /PDN pinand FS X and/orFS R pulsesmust be present.Thus,2 power-down controlmodes areavailable.The firstistopulltheMCLK R /PDN pin high;the alternativeis to hold both FS X and FS R inputscontinuouslylow— the device willpower-down approximately1 ms afterthelastFS X orFS R pulse.Power-up willoccuron thefirstFS X orFS R pulse.The TRI- STATE PCM dataoutput,D X,willremaininthehighimpedance stateuntilthesecond FS X pulse. SYNCHRONOUS OPERATION Forsynchronousoperation,thesame masterclockand bitclockshouldbe used forboththetransmitand receive directions.Inthismode, a clockmust be appliedtoMCLK X and theMCLK R /PDN pincan be used as a power- down control.A low levelon MCLK R /PDN powers up thedeviceand a highlevelpowers down thedevice.In eithercase,MCLK X willbe selectedas themasterclockforboththetransmitand receivecircuits.A bitclock must alsobe appliedtoBCLK X and theBCLK R /CLKSEL can be used toselecttheproperinternaldividerfora compensatesforthe193rdclockpulseeach frame. With a fixedlevelon theBCLK R /CLKSEL pin,BCLK X willbe selectedas thebitclockforboththetransmitand receivedirections.Table1 indicatesthefrequenciesofoperationwhichcan be selected,dependingon thestate ofBCLK R /CLKSEL. Inthissynchronousmode, thebitclock,BCLK X,may be from64 kHz to2.048MHz, butmust be synchronouswithMCLK X. Each FS X pulsebeginstheencodingcycleand thePCM datafromthepreviousencode cycleisshiftedoutofthe enabledD X outputon thepositiveedge ofBCLK X.After8 bitclockperiods,theTRI-STATE D X outputisreturned toa highimpedance state.With an FS R pulse,PCM dataislatchedviatheD R inputon thenegativeedge of BCLK X (orBCLK R ifrunning).FS X and FS R must be synchronouswithMCLK X/R. Table1.SelectionofMaster Clock Frequencies Master Clock BCLK R /CLKSEL Frequency Selected TP3057 TP3054 Clocked 2.048MHz 1.536MHz or1.544MHz 0 1.536MHz or1.544MHz 2.048MHz 1 2.048MHz 1.536MHz or1.544MHz Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TP3054-X TP3057-X

TP3054-X,TP3057-X SNOSBY2C –MARCH 2005–REVISED APRIL 2013 www.ti.com ASYNCHRONOUS OPERATION For asynchronousoperation,separatetransmitand receiveclocksmay be applied.MCLK X and MCLK R must be 2.048MHz fortheTP3057, or 1.536MHz, 1.544MHz fortheTP3054, and need notbe synchronous.For best transmissionperformance,however,MCLK R shouldbe synchronouswithMCLK X, which iseasilyachievedby applyingonlystaticlogiclevelsto the MCLK R /PDN pin.ThiswillautomaticallyconnectMCLK X to allinternal MCLK R functions(seePin Descriptionabove).For 1.544MHz operation,thedeviceautomaticallycompensates forthe193rdclockpulseeach frame.FS X startseach encodingcycleand must be synchronouswithMCLK X and BCLK X.FS R startseach decodingcycleand must be synchronouswithBCLK R .BCLK R must be a clock,thelogic levelsshown inTable1 are notvalidinasynchronousmode. BCLK X and BCLK R may operatefrom 64 kHz to 2.048MHz. SHORT FRAME SYNC OPERATION The COMBO can utilizeeithera shortframesyncpulseora longframesyncpulse.Upon power initialization,the deviceassumes a shortframemode. Inthismode, bothframesync pulses,FS X and FS R ,must be one bitclock periodlong,withtimingrelationshipsspecifiedinFigure4.WithFS X highduringa fallingedge ofBCLK X,thenext risingedge ofBCLK X enablestheD X TRI-STATE outputbuffer,whichwilloutputthesignbit.The followingseven risingedges clockouttheremainingseven bits,and thenextfallingedge disablestheD X output.WithFS R high duringa fallingedge ofBCLK R (BCLK X insynchronousmode),thenextfallingedge ofBCLK R latchesinthesign bit.The followingseven fallingedges latchinthe seven remainingbits.Allfourdevicesmay utilizethe short framesyncpulseinsynchronousorasynchronousoperatingmode. LONG FRAME SYNC OPERATION To use thelongframemode, boththeframesync pulses,FS X and FS R ,must be threeormore bitclockperiods long,withtimingrelationshipsspecifiedinFigure5. Based on the transmitframe sync,FS X, the COMBO will sense whethershortorlongframesync pulsesarebeingused.For 64 kHz operation,theframesync pulsemust be keptlow fora minimum of160 ns.The D X TRI-STATE outputbufferisenabledwiththerisingedge ofFS X or therisingedge ofBCLK X,whichevercomes later,and thefirstbitclockedoutisthesignbit.The followingseven BCLK X risingedges clockout the remainingseven bits.The D X outputisdisabledby the fallingBCLK X edge followingtheeighthrisingedge,orby FS X goinglow,whichevercomes later.A risingedge on thereceiveframe syncpulse,FS R ,willcause thePCM dataatD R tobe latchedinon thenexteightfallingedges ofBCLK R (BCLK X insynchronousmode). Allfourdevicesmay utilizethelongframe sync pulseinsynchronousor asynchronous mode. In applicationswhere the LSB bitisused forsignalling,withFS R two bitclockperiodslong,the decoder will interpretthelostLSB as “½ ”tominimizenoiseand distortion. TRANSMIT SECTION The transmitsectioninputis an operationalamplifierwithprovisionforgain adjustmentusing two external resistors,see Figure8. The low noiseand wide bandwidthallowgainsinexcess of 20 dB acrossthe audio passband tobe realized.The op amp drivesa unity-gainfilterconsistingofRC activepre-filter,followedby an eighthorderswitched-capacitorbandpass filterclockedat 256 kHz. The outputof thisfilterdirectlydrivesthe encodersample-and-holdcircuit.The A/D isofcompanding typeaccordingtoμ-law(TP3054)orA-law(TP3057) codingconventions.A precisionvoltagereferenceistrimmedinmanufacturingtoprovidean inputoverload(tMAX ) ofnominally2.5V peak (seeTransmissionCharacteristics).The FS X frame sync pulsecontrolsthesamplingof thefilteroutput,and thenthesuccessive-approximationencodingcyclebegins.The 8-bitcode isthenloadedinto a bufferand shiftedoutthroughD X atthenextFS X pulse.The totalencodingdelaywillbe approximately165 μs (duetothetransmitfilter)plus125 μs (duetoencodingdelay),whichtotals290 μs.Any offsetvoltagedue tothe filtersorcomparatoriscancelledby signbitintegration.

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TP3054-X,TP3057-X www.ti.com SNOSBY2C –MARCH 2005–REVISED APRIL 2013 RECEIVE SECTION The receivesectionconsistsofan expandingDAC which drivesa fifthorderswitched-capacitorlow pass filter clockedat256 kHz.The decoderisA-law(TP3057)orμ-law(TP3054)and the5thorderlow pass filtercorrects forthesinx/xattenuationdue tothe8 kHz sample/hold.The filteristhenfollowedby a 2nd orderRC activepost- filter/poweramplifiercapableofdrivinga 600Ω loadtoa levelof7.2dBm. The receivesectionisunity-gain.Upon theoccurrenceofFS R ,thedataattheD R inputisclockedinon thefallingedge ofthenexteightBCLK R (BCLK X) periods.At theend ofthedecodertimeslot,thedecodingcyclebegins,and 10 μs laterthedecoderDAC output isupdated.The totaldecoderdelayis∼10 μs (decoderupdate)plus110 μs (filterdelay)plus62.5μs (½ frame), whichgivesapproximately180 μs. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) VCC toGNDA 7V VBB toGNDA −7V Voltageatany AnalogInputorOutput VCC +0.3V toVBB −0.3V Voltageatany DigitalInputorOutput VCC +0.3V toGNDA −0.3V OperatingTemperatureRange −55°C to+ 125°C StorageTemperatureRange −65°C to+150°C Lead Temperature (Soldering,10 sec.) 300°C (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. ElectricalCharacteristics Unlessotherwisenoted,limitsprintedinBOLD charactersareensuredforVCC = +5.0V ±5%, VBB = −5.0V±5%; TA = −40°C to+85°C by correlationwith100% electricaltestingatTA = 25°C. Allotherlimitsareassuredby correlationwithother productiontestsand/orproductdesignand characterization.AllsignalsreferencedtoGNDA. TypicalsspecifiedatVCC = +5.0V,VBB = −5.0V,TA = 25°C. Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACE VIL InputLow Voltage 0.6 V VIH InputHighVoltage 2.2 V VOL D X,IL=3.2mA 0.4 V OutputLow Voltage SIGR ,IL=1.0mA 0.4 V TS X,IL=3.2mA, Open Drain 0.4 V VOH D X,IH =−3.2mA 2.4 V OutputHighVoltage SIGR ,IH =−1.0mA 2.4 V IIL InputLow Current GNDA ≤VIN≤VIL,AllDigitalInputs −10 10 μA IIH InputHighCurrent VIH≤VIN≤VCC −10 10 μA IOZ OutputCurrentinHighImpedance State D X,GNDA ≤VO ≤VCC −10 10 μA(TRI-STATE) ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES) IIXA InputLeakage Current −2.5V≤V≤+2.5V,VF XI+ orVF XI− −200 200 nA R IXA InputResistance −2.5V≤V≤+2.5V,VF XI+ orVF XI− 10 M Ω R O XA OutputResistance ClosedLoop,UnityGain 1 3 Ω R LXA Load Resistance GS X 10 kΩ C LXA Load Capacitance GS X 50 pF VO XA OutputDynamic Range GS X,R L ≥ 10 kΩ −2.8 2.8 V AVXA VoltageGain VF XI+ toGS X 5000 V/V Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TP3054-X TP3057-X

TP3054-X,TP3057-X SNOSBY2C –MARCH 2005–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) Unlessotherwisenoted,limitsprintedinBOLD charactersareensuredforVCC = +5.0V ±5%, VBB = −5.0V±5%; TA = −40°C to+85°C by correlationwith100% electricaltestingatTA = 25°C. Allotherlimitsareassuredby correlationwithother productiontestsand/orproductdesignand characterization.AllsignalsreferencedtoGNDA. TypicalsspecifiedatVCC = +5.0V,VBB = −5.0V,TA = 25°C. Symbol Parameter Conditions Min Typ Max Units FU XA UnityGain Bandwidth 1 2 MHz VOS XA OffsetVoltage −20 20 mV VCM XA Common-Mode Voltage CMRRXA > 60 dB −2.5 2.5 V CMRRXA Common-Mode RejectionRatio DC Test 60 dB PSRRXA Power SupplyRejectionRatio DC Test 60 dB ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES) R O RF OutputResistance PinVF R O 1 3 Ω R LRF Load Resistance VF R O= ±2.5V 600 Ω C LRF Load Capacitance 500 pF VOS R O OutputDC OffsetVoltage −200 200 mV POWER DISSIPATION (ALL DEVICES) ICC 0 Power-Down Current No Load(1) 0.65 2.0 mA IBB 0 Power-Down Current No Load(1) 0.01 0.33 mA ICC 1 Power-Up (Active)Current No Load 5.0 11.0 mA IBB 1 Power-Up (Active)Current No Load 5.0 11.0 mA (1) ICC0 and IBB0 aremeasured afterfirstachievinga power-upstate.

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TP3054-X,TP3057-X www.ti.com SNOSBY2C –MARCH 2005–REVISED APRIL 2013 Timing Specifications Unlessotherwisenoted,limitsprintedinBOLD charactersareensuredforVCC = +5.0V ±5%, VBB = −5.0V±5%; TA = −40°C to+85°C by correlationwith100% electricaltestingatTA = 25°C. Allotherlimitsareassuredby correlationwithother productiontestsand/orproductdesignand characterization.AllsignalsreferencedtoGNDA. TypicalsspecifiedatVCC = Conventionssectionfortestmethods information. Symbol Parameter Conditions Min Typ Max Units 1/tPM Depends on theDeviceUsed and the 1.536 MHz FrequencyofMasterClocks BCLK R /CLKSEL Pin. 1.544 MHz MCLK X and MCLK R 2.048 MHz tRM RiseTime ofMasterClock MCLK X and MCLK R 50 ns tFM FallTime ofMasterClock MCLK X and MCLK R 50 ns tPB PeriodofBitClock 485 488 15725 ns tRB RiseTime ofBitClock BCLK X and BCLK R 50 ns tFB FallTime ofBitClock BCLK X and BCLK R 50 ns tWMH WidthofMasterClockHigh MCLK X and MCLK R 160 ns tWML WidthofMasterClockLow MCLK X and MCLK R 160 ns tSBFM ShortFrame 100 nsSet-UpTime fromBCLK X High FirstBitClockaftertheLeadingEdge of toMCLK X FallingEdge FS X Long Frame 125 tSFFM SetupTime fromFS X Highto 100 nsLong Frame OnlyMCLK X FallingEdge tWBH WidthofBitClockHigh VIH=2.2V 160 ns tWBL WidthofBitClockLow VIL=0.6V 160 ns tHBFL HoldingTime fromBitClock Long Frame Only 0 nsLow toFrame Sync tHBFS HoldingTime fromBitClock ShortFrame Only 0 nsHightoFrame Sync tSFB Set-UpTime fromFrame Sync Long Frame Only 115 nstoBitClockLow tDBD DelayTime fromBCLK X High Load=150 pF plus2 LSTTL Loads 0 140 nstoData Valid tDBTS DelayTime toTS X Low Load=150 pF plus2 LSTTL Loads 140 ns tDZC DelayTime fromBCLK X Low to C L=0 pF to150 pF 50 165 nsData OutputDisabled tDZF DelayTime toValidData from FS X orBCLK X,Whichever C L=0 pF to150 pF 20 165 ns Comes Later tSDB Set-UpTime fromD R Validto 50 nsBCLK R/X Low tHBD HoldTime fromBCLK R/X Low to 50 ns D R Invalid tSF Set-UpTime fromFS X/R to ShortFrame Sync Pulse(1BitClockPeriodLong) 50 nsBCLK X/R Low tHF HoldTime fromBCLK X/R Low ShortFrame Sync Pulse(1BitClockPeriodLong) 100 nstoFS X/R Low tHBFl HoldTime from3rdPeriodof Long Frame Sync Pulse(from3 to8 BitClockPeriodsBitClockLow toFrame Sync 100 nsLong)(FSX orFS R ) tWFL Minimum WidthoftheFrame 64k Bit/sOperatingMode 160 nsSync Pulse(Low Level) Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TP3054-X TP3057-X

TP3054-X,TP3057-X SNOSBY2C –MARCH 2005–REVISED APRIL 2013 www.ti.com Timing Diagrams Figure4. ShortFrame Sync Timing

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TP3054-X,TP3057-X www.ti.com SNOSBY2C –MARCH 2005–REVISED APRIL 2013 Figure5. Long Frame Sync Timing Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TP3054-X TP3057-X

TP3054-X,TP3057-X SNOSBY2C –MARCH 2005–REVISED APRIL 2013 www.ti.com TransmissionCharacteristics Unlessotherwisenoted,limitsprintedinBOLD charactersareensuredforVCC = +5.0V ±5%, VBB = −5.0V±5%; TA = −40°C to+85°C by correlationwith100% electricaltestingatTA = 25°C. Allotherlimitsareassuredby correlationwithother productiontestsand/orproductdesignand characterization.GNDA = 0V,f= 1.02kHz,VIN = 0 dBm0, transmitinputamplifier connectedforunitygainnon inverting.TypicalsarespecifiedatVCC = +5.0V,VBB = −5.0V,TA = 25°C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE AbsoluteLevels Nominal0 dBm0 Levelis4 dBm 1.2276 Vrms(Definitionofnominalgain) (600Ω)0 dBm0 tMAX Max OverloadLevel TP3054 (3.17dBm0) 2.501 VPK TP3057 (3.14dBm0) 2.492 VPK G XA TA=25°C, VCC =5V, VBB =−5VTransmitGain,Absolute −0.15 0.15 dBInputatGS x=0 dBm0 at1020 Hz G XR f=16Hz −40 dB f=50Hz −30 dB f=60Hz −26 dB f=200Hz −1.8 −0.1 dB f=300Hz–3000 Hz −0.15 0.15 dB TransmitGain,RelativetoG XA f=3152Hz −0.15 0.20 dB f=3300Hz −0.35 0.1 dB f=3400Hz −0.7 0 dB f=4000Hz −14 dB f=4600Hz and Up, Measure −32 dB Response from0 Hz to4000 Hz G XAT AbsoluteTransmitGain Variationwith RelativetoG XA −0.15 0.15 dBTemperature G XAV AbsoluteTransmitGain Variationwith RelativetoG XA −0.05 0.05 dBSupplyVoltage G XRL SinusoidalTestMethod ReferenceLevel=−10 dBm0 TransmitGain VariationswithLevel VF XI+=−40 dBm0 to+3 dBm0 −0.2 0.2 dB VF XI+=−50 dBm0 to−40 dBm0 −0.4 0.4 dB VF XI+=−55 dBm0 to−50 dBm0 −1.2 1.2 dB G RA TA=25°C, VCC =5V, VBB =−5V ReceiveGain,Absolute Input=DigitalCode Sequence −0.20 0.20 dB for0 dBm0 Signalat1020 Hz G RR f=0Hz to3000 Hz −0.15 0.15 dB f=3300Hz −0.35 0.1 dB ReceiveGain,RelativetoG RA f=3400Hz −0.7 0 dB f=4000Hz −14 dB G RAT AbsoluteReceiveGain Variationwith RelativetoG RA −0.15 0.15 dBTemperature G RAV AbsoluteReceiveGain Variationwith RelativetoG RA −0.05 0.05 dBSupplyVoltage G RRL SinusoidalTestMethod;Reference InputPCM Code Correspondstoan IdeallyEncoded ReceiveGain VariationswithLevel PCM Level=−40 dBm0 to+3 dBm0 −0.2 0.2 dB PCM Level=−50 dBm0 to−40 dBm0 −0.4 0.4 dB PCM Level=−55 dBm0 to−50 dBm0 −1.2 1.2 dB VRO ReceiveOutputDriveLevel R L=600Ω −2.5 2.5 V

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TP3054-X,TP3057-X www.ti.com SNOSBY2C –MARCH 2005–REVISED APRIL 2013 TransmissionCharacteristics(continued) Unlessotherwisenoted,limitsprintedinBOLD charactersareensuredforVCC = +5.0V ±5%, VBB = −5.0V±5%; TA = −40°C to+85°C by correlationwith100% electricaltestingatTA = 25°C. Allotherlimitsareassuredby correlationwithother productiontestsand/orproductdesignand characterization.GNDA = 0V,f= 1.02kHz,VIN = 0 dBm0, transmitinputamplifier connectedforunitygainnon inverting.TypicalsarespecifiedatVCC = +5.0V,VBB = −5.0V,TA = 25°C. Symbol Parameter Conditions Min Typ Max Units ENVELOPE DELAY DISTORTION WITH FREQUENCY D XA TransmitDelay,Absolute f=1600Hz 290 315 μs D XR f=500Hz−600 Hz 195 220 μs f=600Hz−800 Hz 120 145 μs f=800Hz−1000 Hz 50 75 μs TransmitDelay,RelativetoD XA f=1000Hz−1600 Hz 20 40 μs f=1600Hz−2600 Hz 55 75 μs f=2600Hz−2800 Hz 80 105 μs f=2800Hz−3000 Hz 130 155 μs D RA ReceiveDelay,Absolute f=1600Hz 180 200 μs D RR f=500Hz−1000 Hz −40 −25 μs f=1000Hz−1600 Hz −30 −20 μs ReceiveDelay,RelativetoD RA f=1600Hz−2600 Hz 70 90 μs f=2600Hz−2800 Hz 100 125 μs f=2800Hz−3000 Hz 145 175 μs NOISE N XC TransmitNoise,C Message Weighted TP3054 (1) 12 16 dBrnC0 N XP TransmitNoise,P Message Weighted TP3057 (1) −74 −67 dBm0p N RC PCM Code isAlternatingPositiveandReceiveNoise,C Message Weighted 8 11 dBrnC0NegativeZero-TP3054 N RP ReceiveNoise,P Message Weighted TP3057 PCM Code EqualsPositiveZero −82 −79 dBm0p N RS f=0kHz to100 kHz,Loop AroundNoise,SingleFrequency −53 dBm0Measurement,VF XI+=0 Vrms PPSR X VCC =5.0VDC +100 mVrmsPositivePower SupplyRejection, 40 dBCTransmit f=0kHz−50 kHz (2) NPSR X VBB =−5.0VDC + 100 mVrmsNegativePower SupplyRejection, 40 dBCTransmit f=0kHz−50 kHz(2) PPSR R PCM Code EqualsPositiveZero VCC =5.0VDC +100 mVrms Measure VF R 0PositivePower SupplyRejection, Receive f=0Hz−4000 Hz 38 dBC f=4kHz−25 kHz 38 dB f=25kHz−50 kHz 35 dB NPSR R PCM Code EqualsPositiveZero VBB =−5.0VDC +100 mVrms Measure VF R 0NegativePower SupplyRejection, Receive f=0Hz−4000 Hz 38 dBC f=4kHz−25 kHz 38 dB f=25kHz−50 kHz 35 dB (1) Measured by extrapolationfromthedistortiontestresultat−50 dBm0. (2) PPSR X,NPSR X,and CT R –X aremeasured witha −50 dBm0 activationsignalappliedtoVF XI+. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TP3054-X TP3057-X

TP3054-X,TP3057-X SNOSBY2C –MARCH 2005–REVISED APRIL 2013 www.ti.com TransmissionCharacteristics(continued) Unlessotherwisenoted,limitsprintedinBOLD charactersareensuredforVCC = +5.0V ±5%, VBB = −5.0V±5%; TA = −40°C to+85°C by correlationwith100% electricaltestingatTA = 25°C. Allotherlimitsareassuredby correlationwithother productiontestsand/orproductdesignand characterization.GNDA = 0V,f= 1.02kHz,VIN = 0 dBm0, transmitinputamplifier connectedforunitygainnon inverting.TypicalsarespecifiedatVCC = +5.0V,VBB = −5.0V,TA = 25°C. Symbol Parameter Conditions Min Typ Max Units SOS Loop Around Measurement,0 dBm0, −30 dB

300 Hz to3400 Hz InputPCM Code

AppliedatD R .SpuriousOut-of-BandSignalsatthe ChannelOutput 4600 Hz–7600 Hz −30 dB

7600 Hz–8400 Hz −40 dB

8400 Hz–100,000Hz −30 dB

STD X, SinusoidalTestMethod(3) STD R Level=3.0dBm0 33 dBC =0 dBm0 to−30 dBm0 36 dBC SignaltoTotalDistortionTransmitor =−40 dBm0 XMT 28 dBCReceiveHalf-Channel RCV 29 dBC =−55 dBm0 XMT 13 dBC RCV 14 dBC SFD X SingleFrequencyDistortion,Transmit −43 dB SFD R SingleFrequencyDistortion,Receive −43 dB IMD Loop Around Measurement, VF XI+=−4 dBm0 to−21 dBm0, Two IntermodulationDistortion −41 dB FrequenciesintheRange

300 Hz−3400 Hz

CT X-R f=300Hz−3400 HzTransmittoReceiveCrosstalk,0 dBm0 −90 −70 dBTransmitLevel D R =QuietPCM Code (4) CT R-X ReceivetoTransmitCrosstalk,0 dBm0 f=300Hz−3400 Hz,VF XI=Multitone(5) −90 −70 dBReceiveLevel (3) TP3054/57 aremeasured usingC message weightedfilterforμ-lawand psophometricweightedfilterforA-law. (4) CT X–R @ 1.544MHz MCLK X freq.is−70 dB max. 50% ±5% BCLK X dutycycle. (5) PPSR X,NPSR X,and CT R –X aremeasured witha −50 dBm0 activationsignalappliedtoVF XI+.

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TP3054-X,TP3057-X www.ti.com SNOSBY2C –MARCH 2005–REVISED APRIL 2013 Encoding Format atD X Output TP3054 μ-Law TP3057 A-Law (IncludesEven BitInversion) VIN (atGS X)=+Full-Scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 VIN (atGS X)=0V 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 VIN (atGS X)=−Full-Scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 APPLICATIONS INFORMATION POWER SUPPLIES While the pinsof the TP3050 familyare wellprotectedagainstelectricalmisuse,itisrecommended thatthe standardCMOS practicebe followed,ensuringthatground is connected to the device beforeany other connectionsare made. Inapplicationswhere theprintedcircuitboard may be pluggedintoa “hot” socketwith power and clocksalreadypresent,an extralonggroundpinintheconnectorshouldbe used. Allground connectionstoeach deviceshouldmeet ata common pointas closeas possibletotheGNDA pin. This minimizesthe interactionof ground returncurrentsflowingthrougha common bus impedance.0.1 μF supplydecouplingcapacitorsshouldbe connectedfrom thiscommon ground pointtoVCC and VBB ,as closeto devicepinsas possible. For bestperformance,theground pointofeach CODEC/FILTER on a cardshouldbe connectedtoa common cardgroundinstarformation,ratherthanviaa groundbus. Thiscommon groundpointshouldbe decoupledtoVCC and VBB with10 μF capacitors. RECEIVE GAIN ADJUSTMENT For applicationswhere a TP3050 familyCODEC/filterreceiveoutputmust drivea 600Ω load,buta peak swing lowerthan±2.5V isrequired,thereceivegaincan be easilyadjustedby insertinga matched T-pad orπ-padat theoutput.Table2 liststherequiredresistorvaluesfor600Ω terminations.As thesearegenerallynon-standard values,theequationscan be used tocompute theattenuationoftheclosestpracticalsetofresistors.Itmay be necessaryto use unequalvaluesforthe R1 or R4 arms of the attenuatorsto achievea preciseattenuation. Generallyitistolerabletoallowa smalldeviationoftheinputimpedance from nominalwhilestillmaintaininga good returnloss.For example a 30 dB returnlossagainst600Ω isobtainedifthe outputimpedance of the attenuatorisintherange282Ω to319Ω (assuminga perfecttransformer). Figure6. T-Pad Attenuator Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TP3054-X TP3057-X

TP3054-X,TP3057-X SNOSBY2C –MARCH 2005–REVISED APRIL 2013 www.ti.com Note:See ApplicationNote 370 forfurtherdetails. Figure7. π-Pad Attenuator Table2.AttentuatorTablesforZ1=Z2=300 Ω (AllValues inΩ) dB R1 R2 R3 R4 0.1 1.7 26k 3.5 52k 0.2 3.5 13k 6.9 26k 0.4 6.9 6.5k 13.8 13k 2 34.4 1.3k 70 2.6k 3 51.3 850 107 1.8k 4 68 650 144 1.3k 5 84 494 183 1.1k 6 100 402 224 900 7 115 380 269 785 8 379 284 317 698 9 143 244 370 630 10 156 211 427 527 11 168 184 490 535 12 180 161 550 500 13 190 142 635 473 14 200 125 720 450 15 210 110 816 430 16 218 98 924 413 18 233 77 1.17k 386 20 246 61 1.5k 366

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TP3054-X,TP3057-X www.ti.com SNOSBY2C –MARCH 2005–REVISED APRIL 2013 TypicalSynchronous Application Figure8. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TP3054-X TP3057-X

TP3054-X,TP3057-X SNOSBY2C –MARCH 2005–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page

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www.ti.com 6-Sep-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TP3054WM-X NRND SOIC DW 16 45 TBD Call TI Call TI TP3054WM-X COMBO$R TP3054WM-X/63 NRND SOIC DW 16 1000 TBD Call TI Call TI TP3054WM-X COMBO$R TP3054WM-X/63SN NRND SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TP3054WM-X COMBO$R TP3054WM-X/NOPB NRND SOIC DW 16 45 Green (RoHS & no Sb/Br) CU SN Level-4-260C-72 HR TP3054WM-X COMBO$R (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 6-Sep-2015 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TP3054WM-X/63 SOIC DW 16 1000 367.0 367.0 38.0 TP3054WM-X/63SN SOIC DW 16 1000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 Pack Materials-Page 2

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