TP3057-X

TP3054-X NSC | Alldatasheet

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Technical content

Features

n −40˚C to +85˚C operation n Complete CODEC and filtering system (COMBO) including: — Transmit high-pass and low-pass filtering — Receive low-pass filter with sin x/x correction — Active RC noise filters — µ-law or A-law compatible COder and DECoder — Internal precision voltage reference — Serial I/O interface — Internal auto-zero circuitry n µ-law, 16-pin — TP3054 n A-law, 16-pin — TP3057 n Designed for D3/D4 and CCITT applications n ±5V operation n Low operating power — typically 50 mW n Power-down standby mode — typically 3 mW n Automatic power-down n TTL or CMOS compatible digital interfaces n Maximizes line interface card circuit density n Dual-In-Line or PCC surface mount packages n See also AN-370, “Techniques for Designing with CODEC/Filter COMBO Circuits” Connection Diagrams Plastic Chip Carriers 00867408 Top View Order Number TP3057V-X Dual-In-Line Package 00867401 Top View Order Number TP3054N-X Order Number TP3054WM-X COMBO® and TRI-STATE® are registered trademarks of National Semiconductor Corporation. March 2005 TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family © 2005 National Semiconductor Corporation DS008674 www.national.com

2.048 MHz, but must be synchronous

during the encoder time slot. amplifier. Used to externally set gain. present. Thus, 2 power-down control modes are available. in the high impedance state until the second FS X pulse. TABLE 1. Selection of Master Clock Frequencies

1.544 MHz

cally compensates for the 193rd clock pulse each frame. or asynchronous operating mode.

Functional Description (Continued) LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods long, with timing relationships specified in Figure 3. Based on the transmit frame sync, FS X, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The D X TRI-STATE output buffer is enabled with the rising edge of FS X or the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKX rising edges clock out the remaining seven bits. The D X output is disabled by the falling BCLKX edge following the eighth rising edge, or by FSX going low, whichever comes later. A rising edge on the receive frame sync pulse, FS R, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode. In applications where the LSB bit is used for signalling, with FS R two bit clock periods long, the decoder will interpret the lost LSB as “1⁄2” to minimize noise and distortion. TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to µ-law (TP3054) or A-law (TP3057) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload MAX) of nominally 2.5V peak (see table of Transmission Characteristics). The FS X frame sync pulse controls the sampling of the filter output, and then the successive- approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through D X at the next FSX pulse. The total encoding delay will be approximately 165 µs (due to the transmit filter) plus 125 µs (due to encod- ing delay), which totals 290 µs. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3057) or µ-law (TP3054) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/power amplifier capable of driving a 600 Ω load to a level of 7.2 dBm. The receive section is unity-gain. Upon the occurrence of FS R, the data at the D R input is clocked in on the falling edge of the next eight BCLKR (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins, and 10 µs later the decoder DAC output is updated. The total decoder delay is ∼10 µs (decoder update) plus 110 µs (filter delay) plus 62.5 µs ( 1⁄2 frame), which gives approximately 180 µs. TP3054-X, TP3057-X www.national.com 4

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V CC to GNDA 7V VBB to GNDA −7V Voltage at any Analog Input or Output V CC+0.3V to VBB−0.3V Voltage at any Digital Input or Output V CC+0.3V to GNDA−0.3V Operating Temperature Range −55˚C to + 125˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature (Soldering, 10 sec.) 300˚C

Electrical Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at T A = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V CC = +5.0V, VBB = −5.0V, T A = 25˚C. Symbol Parameter Conditions Min Typ Max Units DIGITAL INTERFACE V IL Input Low Voltage 0.6 V VIH Input High Voltage 2.2 V VOL Output Low Voltage D X,I L=3.2 mA 0.4 V SIGR,I L=1.0 mA 0.4 V TSX,I L=3.2 mA, Open Drain 0.4 V VOH Output High Voltage D X,I H=−3.2 mA 2.4 V SIGR,I H=−1.0 mA 2.4 V IIL Input Low Current GNDA ≤VIN≤VIL, All Digital Inputs −10 10 µA IIH Input High Current V IH≤VIN≤VCC −10 10 µA IOZ Output Current in High Impedance D X, GNDA≤VO≤VCC −10 10 µA State (TRI-STATE) ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES) I IXA Input Leakage Current −2.5V ≤V≤+2.5V, VFXI+ or VFXI− −200 200 nA RIXA Input Resistance −2.5V ≤V≤+2.5V, VFXI+ or VFXI− 10 M Ω ROXA Output Resistance Closed Loop, Unity Gain 1 3 Ω RLXA Load Resistance GS X 10 k Ω CLXA Load Capacitance GS X 50 pF VOXA Output Dynamic Range GS X,R L ≥ 10 kΩ −2.8 2.8 V AVXA Voltage Gain VF XI+ to GSX 5000 V/V FUXA Unity Gain Bandwidth 1 2 MHz VOSXA Offset Voltage −20 20 mV VCMXA Common-Mode Voltage CMRRXA > 60 dB −2.5 2.5 V CMRRXA Common-Mode Rejection Ratio DC Test 60 dB PSRRXA Power Supply Rejection Ratio DC Test 60 dB ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES) R ORF Output Resistance Pin VF RO1 3 Ω RLRF Load Resistance VF RO=±2.5V 600 Ω CLRF Load Capacitance 500 pF VOSRO Output DC Offset Voltage −200 200 mV POWER DISSIPATION (ALL DEVICES) I CC0 Power-Down Current No Load (Note 2) 0.65 2.0 mA IBB0 Power-Down Current No Load (Note 2) 0.01 0.33 mA ICC1 Power-Up (Active) Current No Load( –40˚C to 85˚C) 5.0 11.0 mA IBB1 Power-Up (Active) Current No Load ( –40˚C to 85˚C) 5.0 11.0 mA Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device i s functional, but do not guarantee specific performance limits. Note 2: ICC0 and IBB0 are measured after first achieving a power-up state. TP3054-X, TP3057-X www.national.com5

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at T A = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V CC = Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units 1/tPM Frequency of Master Clocks Depends on the Device Used and the 1.536 MHz BCLKR/CLKSEL Pin. 1.544 MHz MCLKX and MCLKR 2.048 MHz tRM Rise Time of Master Clock MCLK X and MCLKR 50 ns tFM Fall Time of Master Clock MCLK X and MCLKR 50 ns tPB Period of Bit Clock 485 488 15725 ns tRB Rise Time of Bit Clock BCLK X and BCLKR 50 ns tFB Fall Time of Bit Clock BCLK X and BCLKR 50 ns tWMH Width of Master Clock High MCLK X and MCLKR 160 ns tWML Width of Master Clock Low MCLK X and MCLKR 160 ns tSBFM Set-Up Time from BCLK X High First Bit Clock after Short Frame 100 ns to MCLKX Falling Edge the Leading Edge of FSX Long Frame 125 tSFFM Setup Time from FS X High to MCLKX Falling Edge Long Frame Only 100 ns tWBH Width of Bit Clock High V IH=2.2V 160 ns tWBL Width of Bit Clock Low V IL=0.6V 160 ns tHBFL Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync tHBFS Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync tSFB Set-Up Time from Frame Sync Long Frame Only 115 ns to Bit Clock Low tDBD Delay Time from BCLK X High Load=150 pF plus 2 LSTTL Loads 0 140 ns to Data Valid tDBTS Delay Time to TS X Low Load=150 pF plus 2 LSTTL Loads 140 ns tDZC Delay Time from BCLK X Low to C L=0 pF to 150 pF 50 165 ns Data Output Disabled tDZF Delay Time to Valid Data from C L=0 pF to 150 pF 20 165 ns FSX or BCLKX, Whichever Comes Later tSDB Set-Up Time from D R Valid to 50 ns BCLKR/X Low tHBD Hold Time from BCLK R/X Low to 50 ns DR Invalid tSF Set-Up Time from FS X/R to Short Frame Sync Pulse (1 Bit Clock 50 ns BCLKX/R Low Period Long) tHF Hold Time from BCLK X/R Low Short Frame Sync Pulse (1 Bit Clock 100 ns to FSX/R Low Period Long) tHBFl Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns Bit Clock Low to Frame Sync Clock Periods Long) (FS X or FSR) tWFL Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns Sync Pulse (Low Level) TP3054-X, TP3057-X www.national.com 6

FIGURE 2. Short Frame Sync Timing

FIGURE 3. Long Frame Sync Timing

Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at T A = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA = 0V , f = 1.02 kHz, V IN = 0 dBm0, transmit input amplifier connected for unity gain non inverting. Typicals are specified at V CC = +5.0V, VBB = −5.0V, T A = 25˚C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE Absolute Levels Nominal 0 dBm0 Level is 4 dBm (Definition of nominal gain) (600 Ω) 0 dBm0 1.2276 Vrms t MAX Max Overload Level TP3054 (3.17 dBm0) 2.501 V PK TP3057 (3.14 dBm0) 2.492 V PK GXA Transmit Gain, Absolute T A=25˚C, VCC=5V, VBB=−5V Input at GSx=0 dBm0 at 1020 Hz −0.15 0.15 dB GXR Transmit Gain, Relative to G XA f=16 Hz −40 dB f=50 Hz −30 dB f=60 Hz −26 dB f=200 Hz −1.8 −0.1 dB f=300 Hz–3000 Hz −0.15 0.15 dB f=3152 Hz −0.15 0.20 dB f=3300 Hz −0.35 0.1 dB f=3400 Hz −0.7 0 dB f=4000 Hz −14 dB f=4600 Hz and Up, Measure −32 dB Response from 0 Hz to 4000 Hz G with Temperature with Supply Voltage GXRL Transmit Gain Variations with Sinusoidal Test Method Level Reference Level=−10 dBm0 VF XI+=−40 dBm0 to +3 dBm0 −0.2 0.2 dB VFXI+=−50 dBm0 to −40 dBm0 −0.4 0.4 dB VFXI+=−55 dBm0 to −50 dBm0 −1.2 1.2 dB GRA Receive Gain, Absolute T A=25˚C, VCC=5V, VBB=−5V Input=Digital Code Sequence for 0 dBm0 Signal at 1020 Hz −0.20 0.20 dB G RR Receive Gain, Relative to G RA f=0 Hz to 3000 Hz −0.15 0.15 dB f=3300 Hz −0.35 0.1 dB f=3400 Hz −0.7 0 dB f=4000 Hz −14 dB with Temperature with Supply Voltage GRRL Receive Gain Variations with Sinusoidal Test Method; Reference Level Input PCM Code Corresponds to an Ideally Encoded PCM Level =−40 dBm0 to +3 dBm0 −0.2 0.2 dB PCM Level =−50 dBm0 to −40 dBm0 −0.4 0.4 dB PCM Level =−55 dBm0 to −50 dBm0 −1.2 1.2 dB TP3054-X, TP3057-X www.national.com9

Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at T A = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA = 0V , f = 1.02 kHz, V IN = 0 dBm0, transmit input amplifier connected for unity gain non inverting. Typicals are specified at V CC = +5.0V, VBB = −5.0V, T A = 25˚C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE V RO Receive Output Drive Level R L=600Ω −2.5 2.5 V ENVELOPE DELAY DISTORTION WITH FREQUENCY D XA Transmit Delay, Absolute f=1600 Hz 290 315 µs DXR Transmit Delay, Relative to D XA f=500 Hz−600 Hz 195 220 µs f=600 Hz−800 Hz 120 145 µs f=800 Hz−1000 Hz 50 75 µs f=1000 Hz−1600 Hz 20 40 µs f=1600 Hz−2600 Hz 55 75 µs f=2600 Hz−2800 Hz 80 105 µs f=2800 Hz−3000 Hz 130 155 µs D RA Receive Delay, Absolute f=1600 Hz 180 200 µs DRR Receive Delay, Relative to D RA f=500 Hz−1000 Hz −40 −25 µs f=1000 Hz−1600 Hz −30 −20 µs f=1600 Hz−2600 Hz 70 90 µs f=2600 Hz−2800 Hz 100 125 µs f=2800 Hz−3000 Hz 145 175 µs NOISE N XC Transmit Noise, C Message TP3054 12 16 dBrnC0 Weighted (Note 3) NXP Transmit Noise, P Message TP3057 −74 −67 dBm0p Weighted (Note 3) NRC Receive Noise, C Message PCM Code is Alternating Weighted Positive and Negative Zero — TP3054 8 11 dBrnC0 N RP Receive Noise, P Message TP3057 PCM Code Equals Positive Weighted Zero — −82 −79 dBm0p N RS Noise, Single Frequency f=0 kHz to 100 kHz, Loop Around −53 dBm0 Measurement, VFXI+=0 Vrms PPSRX Positive Power Supply Rejection, V CC=5.0 VDC+100 mVrms Transmit f=0 kHz−50 kHz (Note 4) 40 dBC NPSRX Negative Power Supply Rejection, V BB=−5.0 VDC+ 100 mVrms Transmit f=0 kHz−50 kHz (Note 4) 40 dBC PPSRR Positive Power Supply Rejection, PCM Code Equals Positive Zero Receive V CC=5.0 VDC+100 mVrms Measure VFR0 f=0 Hz−4000 Hz 38 dBC f=4 kHz−25 kHz 38 dB f=25 kHz−50 kHz 35 dB NPSRR Negative Power Supply Rejection, PCM Code Equals Positive Zero Receive V BB=−5.0 VDC+100 mVrms Measure VFR0 f=0 Hz−4000 Hz 38 dBC f=4 kHz−25 kHz 38 dB f=25 kHz−50 kHz 35 dB TP3054-X, TP3057-X www.national.com 10

Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at T A = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA = 0V , f = 1.02 kHz, V IN = 0 dBm0, transmit input amplifier connected for unity gain non inverting. Typicals are specified at V CC = +5.0V, VBB = −5.0V, T A = 25˚C. Symbol Parameter Conditions Min Typ Max Units NOISE SOS Spurious Out-of-Band Signals Loop Around Measurement, 0 dBm0, −30 dB at the Channel Output 300 Hz to 3400 Hz Input PCM Code Applied at D

4600 Hz–7600 Hz −30 dB

7600 Hz–8400 Hz −40 dB

8400 Hz–100,000 Hz −30 dB

X, Signal to Total Distortion Sinusoidal Test Method (Note 6) STDR Transmit or Receive Level=3.0 dBm0 33 dBC Half-Channel =0 dBm0 to −30 dBm0 36 dBC =−40 dBm0 XMT 28 dBC RCV 29 dBC =−55 dBm0 XMT 13 dBC RCV 14 dBC SFDX Single Frequency Distortion, −43 dB Transmit SFDR Single Frequency Distortion, −43 dB Receive IMD Intermodulation Distortion Loop Around Measurement, −41 dB VFXI+=−4 dBm0 to −21 dBm0, Two Frequencies in the Range

300 Hz−3400 Hz

X-R Transmit to Receive Crosstalk, f=300 Hz−3400 Hz −90 −70 dB 0 dBm0 Transmit Level D R=Quiet PCM Code (Note 6) CTR-X Receive to Transmit Crosstalk, f=300 Hz−3400 Hz, VF XI=Multitone −90 −70 dB 0 dBm0 Receive Level (Note 4) ENCODING FORMAT AT D X OUTPUT TP3054 TP3057 µ-Law A-Law (Includes Even Bit Inversion) VIN (at GSX)=+Full-Scale 10000000 10101010 VIN (at GSX)=0V 11111111 11010101 01111111 01010101 VIN (at GSX)=−Full-Scale 00000000 00101010 Note 3: Measured by extrapolation from the distortion test result at −50 dBm0. Note 4: PPSRX, NPSRX, and CTR–X are measured with a −50 dBm0 activation signal applied to VF XI+. Note 5: TP3054/57 are measured using C message weighted filter for µ-law and psophometric weighted filter for A-law. Note 6: CTX–R @ 1.544 MHz MCLKX freq. is −70 dB max. 50% ±5% BCLKX duty cycle. TP3054-X, TP3057-X www.national.com11

While the pins of the TP3050 family are well protected against electrical misuse, it is recommended that the stan- dard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a “hot” socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 µF supply decou- pling capacitors should be connected from this common ground point to V CC and V BB, as close to device pins as possible. For best performance, the ground point of each CODEC/ FILTER on a card should be connected to a common card ground in star formation, rather than via a ground bus. This common ground point should be decoupled to V CC and VBB with 10 µF capacitors. RECEIVE GAIN ADJUSTMENT For applications where a TP3050 family CODEC/filter re- ceive output must drive a 600Ω load, but a peak swing lower than ±2.5V is required, the receive gain can be easily ad- justed by inserting a matched T-pad or π-pad at the output. Table 2lists the required resistor values for 600 Ω termina- tions. As these are generally non-standard values, the equa- tions can be used to compute the attenuation of the closest practical set of resistors. It may be necessary to use unequal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation. Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a good return loss. For example a 30 dB return loss against 600Ω is obtained if the output impedance of the attenuator is in the range 282Ω to 319Ω (assuming a perfect transformer). T-Pad Attenuator 00867411 TP3054-X, TP3057-X www.national.com 12

Note: See Application Note 370 for further details. TABLE 2. Attentuator Tables for Z1=Z2=300Ω

Typical Synchronous Application 00867406 FIGURE 4. TP3054-X, TP3057-X www.national.com 14

Physical Dimensions inches (millimeters) unless otherwise noted Dual-In-Line Package (M) Order Number TP3054WM-X Molded Dual-In-Line Package (N) Order Number TP3054N-X TP3054-X, TP3057-X www.national.com15

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Cavity Dual-In-Line Package (V) Order Number TP3057V-X National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family