TP3056J

TP3051 NSC | Alldatasheet

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‘ 3 National S . oa Semiconductor 5 PY TP3051, TP3056 Parallel Interface 3 . a CODEC/Filter COMBO® General Description Features The TP3051, TP3056 family consists of a p-law and A-law ™ Complete CODEC and filtering system including: monolithic PCM CODEC/filter set utilizing the A/D and D/A = — Transmit high pass and low pass filtering conversion architecture shown in Figure 7 and a parallel |/O. — Receive low pass filter with sin x/x correction data bus interface. The devices are fabricated using Nation- — Receive power amplifier al's advanced double poly microCMOS process. — Active RC noise filters The transmit section consists of an input gain adjust amplifi- _ — #255 law COder and DECoder—TP3051 er, an active RC pre-filter, and a switched-capacitor band. — A*law COder and DECoder—TP3056 pass filter that rejects signals below 200 Hz and above — [ternal precision voltage reference 3400 Hz. A compressing coder samples the filtered signal _ — Internal auto-zero circuitry and encodes it in the 1-255 law or A-law PCM format. Auto- ™ Meets or exceeds all LSSGR and CCITT specifications zero circuitry is included on-chip. The receive section con- ™ +5V operation sists of an expanding decoder which reconstructs the ana- ™ Low operating power—typically 60 mW log signal from the compressed pelaw or A-law code, anda —m Power-down standby mode—typically 3 mW low pass filter which corrects for the sin x/x response of them High speed TRI-STATE® data bus decoder output and rejects signals above 3400 Hz. The re- m 2 loopback test modes ceive output is a single-ended power amplifier capable of driving low impedance loads. The TP3051 y-law and TP3056 A-law devices are pin compatible parallel interface COMBOs for bus-oriented systems. a Block Diagram ss Meu veo ' uto-zen0 1 | | | 1 jw 1 ann WAY > mea onoer om ae ! “ah ae Ni | Flee ce N | |e N ” N D H | N q | N | N | N ' Tc Lint J Lowi N i | anno N | | N \\

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8| Connection Diagrams - Dual-In-Line Package w Ves 1 2 Fal 3 O oo a GNDA 2 19 VFxI- VFRO 3 18} GSx Veca— 4 ith Veco ss TP3051 16>— PCM /CNTL OR 087 6 ‘TP3056 15) cuK ‘086 7 14 DBO 085 8 13) 081 DB4 9 12) DBZ GNOD 0 W 083 TuH 9894-3 Top View Order Number TP3051J or TP3056J | See NS Package Number J20A Pin Description Symbol Function Symbol Function Ve Negative power supply pin. Vag = —5V +5%. PCM/CNTL This control input determines whether the in- GNDA Analog ground. All analog signals are refer- formation on the data bus is PCM data or con- enced to this pin. tro! data. | VERO Analog output of the receive power amplifier. Veco Positive power supply pin for the bus drivers. | This output can drive a 6002 load to +2.5V. Veop = 5V +5%, Must be connected to Voca Positive power supply voltage pin for the ana- Voca log circuitry. Voga = 5V +5%. Must be con- GSx Analog output of the transmit input amplifier. nected to Veop. Used to externally set gain. cs Device chip select input which controls READ, VFyI— inverting input of the transmit input amplifier. WRITE and TRI-STATE® operations on the VEX! Non-inverting input of the transmit input amplifi- data bus. CS does not control the state of any er. analog functions. . on DB7 Bit 7 1/O on the data bus. The PCM LSB. Functional Description Be Bit 6 I/O on the data bus. CLOCK AND DATA BUS CONTROL DBS Bit 5 I/O on the data bus. The CLK input signal provides timing for the encode and DB4 Bit 4 1/0 on the data bus. decode logic and the switched-capacitor filters. It must be GNDD _Digital ground. Alll digital signals are referenced one of the frequencies listed in Table I and must be correct- to this pin. ly selected by control bits CO and C1. DB3 Bit 3 1/0 on the data bus. CLK also functions as a READ/WAITE control signal, with . the device reading the data bus on a positive half-clock cy- bB2 Bit 2 1/0 on the dats bus. cle and writing the bus on a negative half-clock cycle, as Bi Bit 11/0 on the data bus. shown in Figures 4a and 4b. Bit 01 . This DB0 Bit 1/0 on the data bus. This is the PCM sign POWER-UP ; ; stor fil When power is first applied, power-on reset circuitry initializ- CLK lock input for itched-capacitor fil- ine Gnd CODEC. Chock trenconen acer be es the COMBO and sets it in the power-down mode. All 768 kHz, 772 kHz, 1.024 MHz or 1.28 MHz and non-essential circuits are deactivated and the data bus out- must be synchronous with the system clock in- puts, DB0-DB7, and receive power amplifier output, VFRO, put, are in high impedance states. The TP3051, TP3056 is powered-up via a command to the control register (see Control Register Functions). This sets 1-20

Functional Description (continued) g the device in the standby mode with all circuitry activated, An internal transmit frame synchronization pulse is also a but encoding and decoding do not begin until PCM READ generated to start an encode cycle, and this must occur 4 and PCM WRITE chip selects occur. once per transmit frame; i.e., at an 8 kHz rate. oo] 'f PCM/CNTL is high during the CS falling transition, the Ss TABLE |. Controt Bit Functions control register data is written to the bus. This does not | 3 Controusits | Function | —_atact frame synchronization. C0, C1 Select Clock Frequency The receive register contents may also be written back to co C1 Frequen the bus, as described in the Digital Loopback section. requency Except during a WRITE cycle, the bus drivers are in TRI- 0 =X = 1.024MHz STATE mode. 1 0 0.768 MHz or 0.772 MHz 1 91 1.28MHz CONTROL REGISTER FUNCTIONS

7 Writing to the control register allows the user to set the

C2, C3 Digital and Analog Loopback various operating states of the TP3051 and TP3056. The C2 C3 Mode control register can also be read back via the data bus to 1 x digital loopback verify the current operating mode of the device. 0 1 analog loopback 1. CLK Select Qo 0 normal Since one of three distinct clock frequencies may be C4 Power-Down/Power-Up (Note 1) used, the actual frequency must be known by the device 1 = power-down for proper operation of the switched-capacitor fitters. This 0 = power-u is achieved by writing control register bits CO and C1, Power-up normally in the same WRITE cycle that powers-up the TP3051—Don''t care (Note 1) device, and before any PCM data transfers take place. TP3056 2. Digital Loopback 1 = Not implemented. Do not use. In order to establish that a valid path has been selected 0 = Adlaw with even bit inversion through a network, it is sometimes desirable to be able to send data through the network to its destination, then 8-67 __|_Don'tCare (Note 1) loop it back through the network return path to the origi- Note 1: These bits are always set to logical “1” when reading back the nating source where the data can be verified. This loop- control register. back function can be performed in the TP3051 or TP3056 DATA BUS NOMENCLATURE by setting control register bit C2 to 1. With C2 set, the The normal order for serial PCM transmission is sign bit fist, PCM data in the receive register will be written back onto ‘ ° , the data bus during the next PCM WRITE cycle. In the whereas the normal order for serial data is LSB first. The . k ‘ arallel data bus is det as follows: digital loopbac! Kk mode, the receive section is set to an idle p ed channel condition in order to maintain a low impedance [datatype | oso [oer pralog Loopback ata Type DBO u 3. Analog Loopback [ pm | Sign Bit In the analog loopback mode, the transmit filter input is Control Data switched from the gain adjust amplifier to the receive power amplifier output, forming a unity-gain loop from the READING THE BUS receive register back to the transmit register. This mode j , ‘ is entered by setting control register bits C2 to 0 and C3 1.CLK is low when CS goes tow, bus data is gated in during 's en ° u a the next positive half-clock cycle of CLK and latched on the Moa inane eee Power ampliior continues to drive the negative-going transition. If PCM/CNTL is low during the loa . falling CS transition, then the bus data is defined as PCM 4. Power-Down/Power-Up voice data, which is latched into the receive register. This The TP3051 or TP3056 may be put in the power-down also functions as an internal receive frame synchronization mode by setting control register bit C4 to 1. Conversely, pulse to start a decode cycle and must occur once per re- setting bit C4 to 0 powers-up the device. ceive frame, i.e., at an 8 kHz rate. ee TRANSMIT FILTER AND ENCODE SECTION 1 PCM/CNTL is high during the falling CS transition, the bus ‘The transmit section Input Is an operational amplifier with data is latched into the control register. This does not affect 'e transmit section input is an operatic mplifier wit frame synchronization: provision for gain adjustment using two external resistors, vyne! . see Figure 2. The low noise and wide bandwidth allow gains WRITING THE BUS in excess of 20 dB across the audio passband to be real- if CLK is high when TS goes low, at the next falling tran- ized. The op amp drives a unity-gain fitter consisting of a sition of CLK, the bus drivers are enabled and either the 2nd order RC active pre-filter, followed by an 8th order PCM transmit data or the contents of the control register are switched-capacitor bandpass filter clocked at 256 kHz. The gated onto the bus, depending on the level of PCM/CNTL output of this filter directly drives the encoder sample-and- at the CS transition. If PCM/CNTL is low during the CS fall- hold circuit. The A/D is of companding type according to ing transition, the transmit register data is written to the bus. 2-255 law (TP3051) or A-law (TP3056) coding schemes. A Precision voltage reference is trimmed in manufacturing 1-21

Absolute Maximum Ratings 3 |f Military/Aerospace specified devices are required, Voltage at Any Digital a Please contact the National Semiconductor Sales Input or Output Voc + 0.3V to GNDD—0.3V uy Office/Distributors for availability and specifications. Operating Temperature Range ~25°C to +125°C 2 GNDD to GNDA +0.3V Storage Temperature Range -65Cto+150C | Oo Veca of Veep to GNDD or GNDA " Lead Temp. (Soldering, 10 sec.) sore | & Vp to GNDD or GNDA -wv ESD (Human Body Model) 1000V Voltage at Any Analog Input or Output Voc +t 0.3V to Vgg—0.3V

Electrical Characteristics

Unless otherwise noted: Voca = Vecp = 5.0V +5%, Vag = —5V +5%, GNDD = GNDA = OV, Ta = OC to 70°C; typical characteristics specified at nominal supply voltages, Ta = 25°C; all digital signals are referenced to GNDD, all analog signals are referenced to GNDA. Limits printed in BOLD characters are guaranteed for Voca = Vecp = 5.0V +5% and Vep = —5.0V +5%; Ta = 0°C to 70°C by correlation with 100% Electrical testing at Ta = 25°C. All other limits are assured by correlation with other production test and/or product design and characteristics. symbol | ___Parameter_ | Gontions in| Typ | Max | Unite DIGITAL INTERFACE Yu___[ tnputtowvotage TC oe Vn | inputvinnvotags Pd ee | Vo. | OutputtowVotage | eo-Da7.y=2sma || ow |v Von | Oupatrighvotage | 080-087, m= -2sma—| aa] | __[~v m___[ inputowourent enoo svwsvu | 8 (| | | ma loz Output Current in High Impedance | DBO-DB7, GNDD < Vo < Voc [cccmsmnae re [eemaeeciesve | “a | Ts | m ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER XA | ‘nputLeakage Curent [2.6 eV +26V.viyit orvig | 200 | | 200 | nA AXA | tnputResistance | 2 sVs taavveytorved | to | [| wn RoxA | OutputResistance, & | Closedtoop.UniyGan | | a | 8 | FuxA__| Load Resistance, GS a CuxA | Load Capacitance, GS ee VoxA __[ Output dynamic Range,GSx [y= 10K | a | | ee | AvtA | VotageGan | vent toasx | soo | || wv Fuxa | uniy-Gaingandwith PEt | Ce Vosxa | osetvorige P| a0 | 80 | mv VeweA | CommonMede Vottage | OMARXA> 6008 | 28 | | as |v cmnnxa | Common-ModeRejecionRato | DG Test | eo | || a PSARXA | Powersupply ejecionRato | DG Test || | RECEIVE POWER AMPLIFIER CRF | LoadCapaciance Pd 8 vos,0_| ouputocorisetvotage | 200 | | 200 | mv POWER DISSIPATION lcco | PowerDownGurent | NoLoediNote) | (OS | 4.5 | mA lego | PowerDownGurent | Notoaaiwoten) || 005 | 0.8 | ma lcci | ActveGurent | Noted || 80 | 8.0 | ma Note 1: cco and Iggo are measured after first achieving a power-up state, 1-23

Transmission Characteristics 3 Unless otherwise specified: Ta = O°C to +70°C, Vaca = Voop = 5V +5%, Vag = —5V +5%, GNDD = GNDA=ov,t= | & 1.02 kHz, Vin = 0 dBmoO, transmit input amplifier connected for unity-gain non-inverting. Limits printed in BOLD characters are | guaranteed for Voca = Vocp = 5.0V +5% and Vag = —5.0V +5%; Ta = 0°C to 70°C by correlation with 100% electrical | 3g testing at Ta = 25°C. All other limits are assured by correlation with other production tests and/or product design and character- 8 istics. a a symbol[ Parameter | Conattione in| typ | Max | Unite AMPLITUDE RESPONSE Absolute Levels Nominal 0 dBm0 Level is 4 dBm (6002) 0 dBmo TP3051 1.2276 Vrms TP3056 1.2276 Vrms tMax Maximum Overload Level TP3051 (+3.17 dBmo0) 2.501 Vp ‘TP3056 (+3.14 dBm0) 2.492 Vek Gxa Transmit Gain, Absolute Ta = 25°C, Voca = Voop = 5.0V, Vee = —5.0V 3B Input at GSx = 0 dBm0 at 1020 Hz Gxr Transmit Gain, Relative toGxq | f = 16Hz -40 | dB f = SOHz —30 dB f = 60Hz -26/ dB f = 200Hz -1.8 0.1} dB f = 300 Hz-3000 Hz -0.15 0.15 | dB f = 3300 Hz —0.35 0.1 | dB f = 3400 Hz -0.7 ° dB f = 4000 Hz -14) dB f = 4600 Hz and Up, Measure Response -32 | oB from 0 Hz to 4000 Hz Gxat | Absolute Transmit Gain Variation | Relative to Gxq -o4 04 8 with Temperature . . Gxay__ | Absolute Transmit Gain Variation | Relative to Gxq 8 with Supply Voltage Gxp___ | Transmit Gain Variation with Sinusoidal Method Level Reference Level = ~10dBm0 VFxI+ = —40 dBm0 to +3 dBmo dB VFxI+ = —50dBm0 to -40 dBmo dB VFxI+ = —55 dBm0 to —50 dBmo dB Gra Receive Gain, Absolute Ta = 25°C, Voca = Voop = 5V, Vag = —5V Input = Digital Code Sequence for dB 0 dBm0 Signal at 1020 Hz Gra Receive Gain, Relative toGra | f = 0Hz to 3000 Hz -0.15 0.15 | dB f = 3300 Hz —0.35 | 0.05 | dB f = 3400 Hz -0.7 ° 6B f = 4000 Hz -14| 4B Grat Absolute Receive Gain Variation | Relative to Gap -04 0.4 dB with Temperature Grav _ | Absolute Receive Gain Variation | Relative to Gra 8 with Supply Voltage Grri | Receive Gain Variation with Sinusoidal Test Method; Reference Level Input PCM Code Corresponds to an Ideally Encoded — 10 dBm0 Signal PCM Level = —40 dBm0 to +3 dBm0 dB PCM Level = —50 dBm0 to —40 dBm0 dB PCM Level = —55 dBm0 to —50 dBmo dB “Varo __ | Receive Output Drive Level Ry = 6000. [-es | [es |v 1-25

o rey $| Transmission Characteristics (continues) FE | Unless otherwise specified: T, = 0°C to +70°C, Voca = Vocp = 5V +5%, Vag = —5V +5%, GNDD = GNDA = OV, f = =| 1.02 kHz, Viy = 0 dBm0, transmit input amplifier connected for unity-gain non-inverting. Limits printed in BOLD characters are tm | guaranteed for Voca = Vocp = 5.0V +5% and Vga = —5.0V +5%; Ta = 0°C to 70°C by correlation with 100% electrical $ testing at Ta = 25°C. All other limits are assured by correlation with other production tests and/or product design and character- a istics. Symbol [Parameter] Conditions| min | typ | Max | unite ENVELOPE DELAY DISTORTION WITH FREQUENCY Dxa Transmit Delay, Absolute t= 1600 Hz [| 290 | 315 | us Dxr Transmit Delay, Relative toDxa | f = 500 Hz-600 Hz 195 220 BS f = 600 Hz-800 Hz 120 145 BS 4 = 800 Hz-1000 Hz 50 75 ys 4 = 1000 Hz-1600 Hz 20 40 Bs f = 1600 Hz-2600 Hz 55 75 Bs f = 2600 H2-2800 Hz 80 105 us f = 2800 Hz~-3000 Hz 130 | 155 ps Dra Receive Delay, Absolute f= 1600 Hz |_| 180 | 200 | us Dar Receive Delay, Relative to Daa | f = 500 Hz-1000 Hz —40 | —25 ps = 1000 Hz-1600 Hz —30 | -20 us = 1600 Hz-2600 Hz 70 90 BS f = 2600 Hz-2800 Hz 100 | 125 Bs f = 2800 Hz-3000 Hz 145 | 175 Bs NOISE Nxc Transmit Noise, C Message TP3051, (Note 3) Weighted 12 dBrnCo Nxp Transmit Noise, P Message TP3056, VFxI+ = OV (Note 3) _ Weighted 74 dBm0p Nrc Receive Noise, C Message P3051, PCM Code Equals Alternating aBrnco Weighted Positive and Negative Zero Nap Receive Noise, P Message TP3056, PCM Code Equals Positive dBmo, Weighted Zero e Nrs Noise, Single Frequency f = 0 kHz to 100 kHz, Loop Around Bmo Measurement, VFyl+ = OV PPSRx | Positive Power Supply VExI+ = Ov, Rejection, Transmit Veca = Veco = 5.0 Vpc + 100 mVrms dBC f = 0 kHz-50 kHz (Note 4) NPSRx | Negative Power Supply VFyI+ = 0 Vims, Rejection, Transmit Vag = —5.0 Vpc +100 mvims dBc f = 0 kHz—50 kHz (Note 4) PPSRR | Positive Power Supply PCM Code Equals Positive Zero for Rejection, Receive TP3051 and TP3056 Voc = 5.0 Vpg + 100 mVrms = 0 Hz-4000 Hz 40 aBC f = 4kHz~25 kHz 40 dBc f = 25 kHz—50 kHz 36 dBc NPSRR | Negative Power Supply PCM Code Equals Positive Zero for Rejection, Receive TP3051 and TP3056 Vee = —5.0 Vpc +100 mVrms f = 0Hz~4000 Hz dBC f = 4 kHz-25 kHz Be f = 25 kHz—-50 kHz dBc sos Spurious Out-of-Band Signals 0 dBm0, 300 Hz-3400 Hz Input Applied to at the Channel Output VFI +, Measure Individual Image Signals at VFRO

4600 Hz-7600 Hz dB

7600 Hz~8400 Hz qB

8400 Hz—100,000 Hz dB

Transmission Characteristics (continued) S Unless otherwise specified: Ta = 0°C to + 70°C, Veca = Vocp = 5V +5%, Vag = —5V +5%,GNDD = GNDA=ov,f= | & 1.02 kHz, Vin = 0 dBmO, transmit input amplifier connected for unity-gain non-inverting. Limits printed in BOLD characters are | =, guaranteed for Voca = Vocp = 5.0V +5% and Vag = —5.0V +5%; Ta = O°C to 70°C by correlation with 100% electrical | = testing at Ta = 25°C. All other limits are assured by correlation with other production tests and/or product design and character. | & istics. a a symbol | Parameter Coneitions [ win | tye | Max | units DISTORTION STD x Signal to Total Distortion Sinusoidal Test Method (Note 5) STDR Transmit or Receive Level = 3.0 dBmo 0B Half-Channel = 0dBm0 to —30 dBmo dB = —40dBm0 XMT dB RCV dB = —55dBm0 = XMT B RCV dB SFDx Single Frequency Distortion, a8 Transmit SFDR Single Frequency Distortion, 4B Receive IMD Intermodulation Distortion VFxIl+ = —4dBm0 to —21 dBm0, Two Frequencies in the Range dB

300 Hz—3400 Hz

CTx-A Transmit to Receive Crosstalk f = 300 Hz-3400 Hz at 0 dBm0 Transmit 4B 0 dBm0 Transmit Level Level Steady PCM Receive Code CTr-x Receive to Transmit Crosstalk f = 300 Hz~3400 Hz at 0 dBmO 4B 0 dBm0 Receive Level (Note 2) Note 3: Measured by extrapolation from the distortion test result at —50 dB m0. Note 4: CTp_x, PPSRx, and NPSRx are measured with a —50 dBm0 activation signal applied at VFx!*. Note 5: Devices are measured using C message weighted filter for u-law and psophometric weighted filter for A-law, Encoding Format at Data Bus Output TP3056 Trans! True Adaw, C5 = 0 La (Includes Even Bit Inversion) MSB LSB MSB LSB Vin=+Full-Scale | 1 0 0 0 0 0 0 Of 4 0 41 0 41 01 0 Vin = +0V 1404 4 4 4 4 4/4 4 0 4 0 14°01 Vin = — OV Oo 41 1 4 4 4 4 4/0 4 0 4 0 141 01 Vin=— Full-Scale |0 0 0 0 0 0 0 O[0 0 1 01 01 0 1-27

al connected to the device before any other connections are 0.1 uF decoupling capacitor is connected. All ground connections to each device should meet at a Figure 5.) Table Il lists the required resistor values for 6002. 10 uF capacitors. (assuming a perfect transformer). V7 Note: See Application Note 370 for further details. FIGURE 5. T-Pad and 7-Pad Attenuator Models