TP3056B

TP3056B TI | Alldatasheet

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MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Complete PCM Codec and Filtering Systems Include: – Transmit High-Pass and Low-Pass Filtering – Receive Low-Pass Filter With (sin x)/x Correction – Active RC Noise Filters – m-Law and A-Law Compatible Coder and Decoder – Internal Precision Voltage Reference – Serial I/O Interface – Internal Autozero Circuitry /C0068m-Law/A-Law Operation Pin-Selectable /C0068± 5-V Operation /C0068Low Operating Power. . . 60 mW Typ /C0068Power-Down Mode ...5 m W T y p /C0068Automatic Power Down /C0068TTL- or CMOS-Compatible Digital Interface /C0068Maximizes Line Interface Card Circuit Density

description

The TP3056B monolithic serial interface combined PCM codec and filter device is comprised of a single-chip PCM codec (pulse code-modulated encoder and decoder) and analog filters. This device provides all the functions required to interface a full-duplex (2-wire) voice telephone circuit with a TDM (time-division-multiplexed) system. Primary applications include:

• Line interface for digital transmission and switching of T1/E1 carrier, PABX, and central office telephone systems
• Subscriber line concentrators
• Digital-encryption systems
• Digital voice-band data-storage systems
• Digital signal processing The TP3056B is designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion), and the appropriate filtering of analog signals in a PCM system. This device is intended to be used at the analog termination of a PCM line or trunk. It requires a master clock of 2.048 MHz, a transmit/receive data clock that is synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive frame-sync pulses. The TP3056B contains patented circuitry to achieve low transmit channel idle noise and is not recommended for applications in which the composite signals on the transmit side are below –55 dBm0. This device, available in 16-pin N PDIP (plastic dual-in-line package) and 16-pin DW SOIC (small outline IC) packages, is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright  1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. VBB ANLG GND VFRO VCC FSR DR ASEL PDN VFXI+ VFXI– GSX TSX FSX DX BCLK MCLK DW OR N PACKAGE (TOP VIEW)

MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998

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–5 V FSX 5 V 9 8 10 7 12 5 MCLK PDN BCLK ASEL FSR TSX Power Amplifier Timing and Control DR CLK Receive RegulatorS/H DAC RC Active Filter DX OE Transmit Regulator Voltage Reference S/H DAC Switched- Capacitor Band-Pass Filter RC Active Filter VFRO VFXI+ VFXI–Analog Input Switched- Capacitor Low-Pass Filter Analog Output Digital Output Digital Input

MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION ANLG GND 2 Analog ground. All signals are referenced to ANLG GND. ASEL 7 I A-law/m-law select. When ASEL is connected to VCC , A-law is selected. When ASEL is connected to GND or VBB , m-law is selected. BCLK 10 I Transmit/receive bit clock. BCLK shifts PCM data out on DX during transmit and shifts PCM data in through DR during receive. BCLK can vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLK. DR 6 I Receive data input. PCM data is shifted into DR at the trailing edge of the BCLK following the FSR leading edge. DX 11 O DX is the 3-state PCM data output that is enabled by FSX. Data is shifted out on the rising edge of BCLK. FSR 5 I Receive-frame sync pulse input. FSR enables BCLK to shift PCM data in DR. FSR is an 8-kHz pulse train (see Figures 1 and 2 for timing details). FSX 12 I Transmit-frame sync pulse. FSX enables BCLK to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see Figures 1 and 2 for timing details). GSX 14 O Analog output of the transmit input amplifier. GSX is used to set gain externally. MCLK 9 I Transmit/receive master clock. MCLK must be 2.048 MHz. PDN 8 I Power down. When PDN is connected high, the device is powered down. When PDN is connected low or left floating, the device is powered up. PDN is internally tied low. TSX 13 O Transmit channel time-slot strobe. TSX is an open-drain output that pulses low during the encoder time slot. VBB 1 Negative power supply. VBB = –5 V ± 5% VCC 4 Positive power supply. VCC = 5 V ± 5% VFRO 3 O Analog output of the receive channel power amplifier VFXI+ 16 I Noninverting input of the transmit input amplifier VFXI– 15 I Inverting input of the transmit input amplifier

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DW 1025 mW 8.2 mW/°C 656 mW 533 mW N 1150 mW 9.2 mW/°C 736 mW 598 mW recommended operating conditions (see Note 2) MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.25 V Supply voltage, VBB –4.75 –5 –5.25 V High-level input voltage, VIH 2.2 V Low-level input voltage, VIL 0.6 V Common-mode input voltage range, VICR‡ ± 2.5 V Load resistance, GSX, RL 10 kW Load capacitance, GSX, CL 50 pF Operating free-air temperature, TA 0 70 °C ‡ Measured with CMRR > 60 dB NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed. electrical characteristics over recommended ranges of supply voltage operating free-air temperature range, in A-law and m-law modes (unless otherwise noted) supply current PARAMETER TEST CONDITIONS TP3056B UNITPARAMETER TEST CONDITIONS MIN TYP § MAX UNIT ICC Supply current from VCC Power down No load 0.5 1 mAICC Supply current from VCC Operating No load 6 9 mA IBB Supply current from VBB Power down No load 0.5 1 mAIBB Supply current from VBB Operating No load 6 9 mA § All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C.

MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics at VCC = 5 V± 5%, VBB = –5 V ± 5%, GND at 0 V, TA = 25°C (unless otherwise noted) digital interface PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level output voltage DX IH = -3.2 mA 2.4 V VOL Low level output voltage DX IL = 3.2 mA 0.4 VVOL Low-level output voltage TSX IL = 3.2 mA, Drain open 0.4 V IIH High-level input current VI = VIH to VCC ± 10 mA IIL Low-level input current All digital inputsVI = GND to VIL ± 10 mA IOZ Output current in high-impedance state DX VO = GND to VCC ± 10 mA analog interface with transmit amplifier input PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VICR‡ Common-mode input voltage range ± 2.5 V II Input current VFXI+ or VFXI – VI = –2.5 V to 2.5 V ± 200 nA ri Input resistance VFXI+ or VFXI – VI = –2.5 V to 2.5 V 10 M W AV Open-loop voltage amplification VFXI+ to GSX 5000 BI Unity-gain bandwidth GSX 1 2 MHz VIO Input offset voltage VFXI+ or VFXI – ± 20 mV CMRR Common-mode rejection ratio 60 dB KSVR Supply-voltage rejection ratio 60 dB † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. ‡ Measured with CMRR > 60 dB. analog interface with receive amplifier output PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Receive output drive voltage R L = 10 kW ± 2.5 V Output resistance VFRO 1 3 W Load resistance VFRO = ± 2.5 V 600 W Load capacitance VFRO to GND 500 pF Output dc offset voltage VFRO to GND ± 200 mV † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C.

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operating characteristics, over operating free-air temperature range, VCC = 5 V ± 5%, VBB = –5 V± 5%, GND at 0 V, VI = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity gain, noninverting, in A-law and m-law modes, (unless otherwise noted) filter gains and tracking errors PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Maximum peak transmit m-law 3.17 dBm0 2.501 Voverload level A-law 3.14 dBm0 2.492 V Transmit filter gain, absolute‡ (at 0 dBm0) TA = 25°C – 0.15 0.15 dB f = 16 Hz –40 f = 50 Hz –30 f = 60 Hz –26 f = 200 Hz –1.8 –0.1 Transmit filter gain relative to absolute‡ f = 300 Hz to 3000 Hz –0.15 0.15 dBTransmit filter gain, relative to absolute‡ f = 3300 Hz –0.35 0.05 dB f = 3400 Hz –0.8 0 f = 4000 Hz –14 f ≥ 4600 Hz (measure response from 0 Hz to 4000 Hz) –32 Absolute‡ transmit gain variation with temperature and supply voltage relative to absolute transmit gain –0.1 0.1 dB 3 dBm0 ≥ input level ≥ –40 dBm0 ± 0.2 Transmit gain tracking error with level Sinusoidal test method, Reference level = –10 dBm0 –40 dBm0 > input level ≥ –50 dBm0 ± 0.4 dB –50 dBm0 > input level ≥ –55 dBm0 ± 0.8 Receive filter gain, absolute‡ (at 0 dBm0) Input is digital code sequence for 0-dBm0 signal, TA = 25°C –0.15 0.15 dB f = 0 Hz to 3000 Hz, TA = 25°c –0.15 0.15 Receive filter gain relative to absolute‡ f = 3300 Hz –0.35 0.05 dBReceive filter gain, relative to absolute‡ f = 3400 Hz –0.8 0 dB f = 4000 Hz –14 Absolute‡ receive gain variation with temperature and supply voltage TA = full range, See Note 3 –0.1 0.1 dB Sinusoidal test method; 3 dBm0 ≥ input level ≥ –40 dBm0 ± 0.2 Receive gain tracking error with level reference input PCM code corresponds to an ideally –40 dBm0 > input level ≥ –50 dBm0 ± 0.4 dB encoded –10 dBm0 signal –50 dBm0 > input level ≥ –55 dBm0 ± 0.8 Pseudo-noise test method; 3 dBm0 ≥ input level ≥ –40 dBm0 ± 0.25 Transmit and receive gain tracking error with level (A-law, CCITT G 712) Pseudo noise test method reference input PCM code corresponds to an ideally –40 dBm0 > input level ≥ –50 dBm0 ± 0.3 dB encoded –10 dBm0 signal –50 dBm0 > input level ≥ –55 dBm0 ± 0.45 † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. ‡ Absolute rms signal levels are defined as follows: VI = 1.2276 V = 0 dBm0 = 4 dBm at f = 1.02 kHz with RL = 600 W . NOTE 3: Full range for the TP3056B is 0°C to 70°C.

MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics, over operating free-air temperature range, VCC = 5 V ± 5%, VBB = –5 V± 5%, GND at 0 V, VI = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity gain, noninverting, in A-law and m-law modes, (unless otherwise noted) (continued) envelope delay distortion with frequency PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Transmit delay, absolute (at 0 dBm0) f = 1600 Hz 290 315 ms f = 500 Hz to 600 Hz 195 220 f = 600 Hz to 800 Hz 120 145 f = 800 Hz to 1000 Hz 50 75 Transmit delay, relative to absolute‡ f = 1000 Hz to 1600 Hz 20 40 ms f = 1600 Hz to 2600 Hz 55 75 f = 2600 Hz to 2800 Hz 80 105 f = 2800 Hz to 3000 Hz 130 155 Receive delay, absolute (at 0 dBm0) f = 1600 Hz 180 200 ms f = 500 Hz to 1000 Hz –40 –25 f = 1000 Hz to 1600 Hz –30 –20 Receive delay, relative to absolute‡ f = 1600 Hz to 2600 Hz 70 90 ms f = 2600 Hz to 2800 Hz 100 125 f = 2800 Hz to 3000 Hz 140 175 † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. ‡ Absolute rms signal levels are defined as follows: VI = 1.2276 V = 0 dBm0 = 4 dBm at f = 1.02 kHz with RL = 600 W . noise PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Transmit noise, C-message weighted m-law VFXI = 0 V 9 14 dBrnC0 Transmit noise, psophometric weighted (see Note 4)A-law VFXI = 0 V –78 –75 dBm0p Receive noise, C-message weighted m-law PCM code equals alternating positive and negative zero. 2 4 dBrnC0 Receive noise, psophometric weighted A-law PCM code equals positive zero. –86 –83 dBm0p Noise, single frequency VFXI+ = 0 V, f = 0 kHz to 100 kHz, Loop-around measurement –53 dBm0 † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. NOTE 4: Measured by extrapolation from the distortion test result. This parameter is achieved through use of patented circuitry and is not recommended for applications in which the composite signals on the transmit side are below –55 dBm0. crosstalk PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Crosstalk, transmit to receive f = 300 Hz to 3000 Hz,DR at steady PCM code –90 –75 dB Crosstalk, receive to transmit (see Note 5) VFXI = 0 V, f = 300 Hz to 3000 Hz –90 –75 dB † All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C. NOTE 5: Receive-to-transmit crosstalk is measured with a – 50 dBm0 activation signal applied at VFXI+. power amplifiers PARAMETER TEST CONDITIONS MIN MAX UNIT M i 0 dB 0 l l f b tt th ± 0 1 dB li it Bl d l d R td R L = 600 W 1.65 Maximum 0 dBm0 rms level for better than ± 0.1 dB linearity over the range if –10 dBm0 to 3 dBm0 Balanced load,RL, connected between VFRO and Gnd R L = 1200 W 1.75 Vover the range if –10 dBm0 to 3 dBm0 between VFRO and Gnd R L = 30 kW 2 Vrms Signal/distortion R L = 600 W 50 dB

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operating characteristics, over operating free-air temperature range, VCC = 5 V ± 5%, VBB = –5 V± 5%, GND at 0 V, VI = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity gain, noninverting, in A-law and m-law modes, (unless otherwise noted) (continued) power supply rejection PARAMETER TEST CONDITIONS MIN MAX UNIT V 5 V 100 V f=0H zt o4k H z A-law 38 dB Positive power-supply rejection, transmitVCC = 5 V + 100 mVrms, VFXI+ = –50 dBm0 f = 0 H z to 4 kHz m-law 38 dBC † VFXI+ = –50 dBm0 f = 4 kHz to 50 kHz 40 dB V 5 V 100 V f=0H zt o4k H z A-law 35 dB Negative power-supply rejection, transmitVBB = –5 V + 100 mVrms, VFXI+ = –50 dBm0 f = 0 H z to 4 kHz m-law 35 dBC † VFXI+ = –50 dBm0 f = 4 kHz to 50 kHz 40 dB PCM d l iti f=0H zt o4k H z A-law 40 dB Positive power-supply rejection, receivePCM code equals positive zero, VCC =5V+1 0 0m V r m s f = 0 H z to 4 kHz m-law 40 dBC † VCC = 5 V + 100 mVrms f = 4 kHz to 50 kHz 40 dB PCM d l iti f=0H zt o4k H z A-law 38 dB Negative power-supply rejection, receivePCM code equals positive zero, VBB = –5 V + 100 mVrms f = 0 H z to 4 kHz m-law 38 dBC † VBB = –5 V + 100 mVrms f = 4 kHz to 50 kHz 40 dB S 0 dBm0, 300-Hz to 3400-Hz input applied to DR (measure individual image signals at VFRO) –30 dB Spurious out-of-band signals at the channel output (VFRO) f = 4600 Hz to 7600 Hz –33 channel output (VFRO) f = 7600 Hz to 8400 Hz –40 dB f = 8400 Hz to 100kHz –40 † The unit dBC applies to C-message weighting.

MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics, over operating free-air temperature range, VCC = 5 V ± 5%, VBB = –5 V± 5%, GND at 0 V, VI = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity gain, noninverting, in A-law and m-law modes, (unless otherwise noted) (continued) distortion PARAMETER TEST CONDITIONS MIN MAX UNIT Level = 3 dBm0 33 Level = 0 dBm0 to -30 dBm0 36 †Signal to distortion ratio transmit or receive half channel‡ Level = 40 dBm0 Transmit 29 dBC †Signal-to-distortion ratio, transmit or receive half-channel‡ Level = –40 dBm0 Receive 30 dBC † Level = 55 dBm0 Transmit 14 Level = –55 dBm0 Receive 15 Single-frequency distortion products, transmit –46 dB Single-frequency distortion products, receive –46 dB Intermodulation distortion Loop-around measurement, VFXI+ = –4 dBm0 to –21 dBm0, Two frequencies in the range of 300 Hz to 3400 Hz –41 dB Level = –3 dBm0 33 Si l di i i i h lf h l (A l ) Level = –6 dBm0 to –27 dBm0 36 Signal-to-distortion ratio, transmit half-channel (A-law) (CCITT G 714)§ Level = –34 dBm0 33.5 dB(CCITT G .714)§ Level = –40 dBm0 28.5 Level = –55 dBm0 13.5 Level = –3 dBm0 33 Si l t di t ti ti i h lf h l (A l ) Level = –6 dBm0 to –27 dBm0 36 Signal-to-distortion ratio, receive half-channel (A-law) (CCITT G 714)§ Level = –34 dBm0 34.2 dB(CCITT G .714)§ Level = –40 dBm0 30 Level = –55 dBm0 15 † The unit dBC applies to C-message weighting. ‡ Sinusoidal test method (see Note 6) § Pseudo-noise test method NOTE 6: m-law measurements are made using a C-message weighted filter, and A-law measurements are made using a psophometric weighted filter.

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timing requirements over recommended ranges of operating conditions (see Figures 1 and 2) MIN NOM MAX UNIT fclock(M) Frequency of master clock MCLK 2.048 MHz fclock(B) Frequency of bit clock, transmit BCLK 64 2048 kHz tw1 Pulse duration, MCLK high 160 ns tw2 Pulse duration, MCLK low 160 ns tr1 Rise time of master clock (20% to 80%) MCLK 50 ns tf1 Fall time of master clock (80% to 20%) MCLK 50 ns tr2 Rise time of bit clock (20% to 80%), transmit BCLK 50 ns tf2 Fall time of bit clock (80% to 20%), transmit BCLK 50 ns tsu1 Setup time, BCLK high (and FSX in long-frame sync mode) before MCLK ↓ (first bit clock after the leading edge of FSX) 100 ns tw3 Pulse duration, BCLK high, VIH = 2.2 V 160 ns tw4 Pulse duration, BCLK low, VIL = 0.6 V 160 ns th1 Hold time, FSX or FSR low after BCLK low (long frame only) 0 ns th2 Hold time, BCLK high after FSX or FSR ↑ (short frame only) 0 ns tsu2 Setup time, FSX or FSR high before BCLK ↓ (long frame only) 80 ns tsu3 Setup time, DR valid before BCLK ↓ 50 ns th3 Hold time, DR valid after BCLK ↓ 50 ns tsu4 Setup time, FSX or FSR high before BCLK ↓, short-frame sync pulse (1 or 2 bit-clock periods long) (see Note 7) 50 ns th4 Hold time, FSX or FSR high after BCLK ↓, short-frame sync pulse (1 or 2 bit-clock periods long) (see Note 7) 100 ns th5 Hold time, FSX or FSR high after BCLK ↓, long-frame sync pulse (from 3 to 8 bit-clock periods long) 100 ns tw5 Minimum pulse duration of FSX or FSR (frame sync pulse — low level), 64-kbps operating mode160 ns NOTE 7: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high. switching characteristics over recommended ranges of operating conditions (see Figures 1 and 2) PARAMETER TEST CONDITIONS MIN MAX UNIT td1 Delay time, BCLK high to data valid at DX Load = 150 pF plus 2 LSTTL loads† 0 140 ns td2 Delay time, BCLK high to TSX low Load = 150 pF plus 2 LSTTL loads† 140 ns td3 Delay time, BCLK (or 8 clock FSX in long frame only) low to data output (DX) disabled 50 165 ns td4 Delay time, FSX or BCLK high to data valid at DX (long frame only) C L = 0 pF to 150 pF 20 165 ns † Nominal input value for an LSTTL load is 18 kW .

Figure 1. Short Frame Sync Timing

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Figure 2. Long Frame Sync Timing

TP3056B system reliability and design considerations are described in the following paragraphs. if supply current to the device is not limited. is mounted on a card that has an edge connector and the card is hot-inserted into a system with the power on. traces are longer than the power and signal traces so that the card ground is always the first to make contact. Figure 3. Latch-Up Protection Diode Connection

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system reliability and design considerations (continued) device power-up sequence Latch-up also can occur if a signal source is connected without the device being properly grounded. A signal applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following power-up sequence always be used: 1. Ensure that no signals are applied to the device before the power-up sequence is complete. 2. Connect GND. 3. Apply V BB (most negative voltage). 4. Apply VCC (most positive voltage). 5. Force a power down condition in the device. 6. Connect clocks. 7. Release the power down condition. 8. Apply FS synchronization pulses. 9. Apply the signal inputs. When powering down the device, this procedure should be followed in the reverse order. internal sequencing Power-on reset circuitry initializes the TP3056B device when power is first applied, placing it in the power-down mode. The DX and VFRO outputs go into the high-impedance state and all nonessential circuitry is disabled. A low level applied to the PDN terminal powers up the device and activates all internal circuits. The 3-state PCM data output, DX, remains in the high-impedance state until the arrival of the second FSX pulse. general operation A 2.048-MHz clock signal applied to MCLK serves as the master clock for both the receive and the transmit directions. BCLK must have a bit clock signal applied to it, which then serves as the bit clock for both the receive and the transmit directions. BCLK can be in the range from 64 kHz to 2.048 MHz, but must be synchronous with MCLK. The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the enabled DX output on the rising edge of BCLK. After eight bit-clock periods, the 3-state DX output is returned to the high-impedance state. With an FSR pulse, PCM data is latched in via DR on the falling edge of BCLK. FSX and FSR must be synchronous with MCLK.

MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION short-frame sync operation The device can operate with either a short-frame sync pulse or a long-frame sync pulse. On power up, the device automatically goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing relationships specified in Figure 1. With FSX high during a falling edge of BCLK, the next rising edge of BCLK enables the 3-state output buffer, outputting the sign bit at DX. The remaining seven bits are shifted out on the following seven rising edges, with the next falling edge disabling DX. With FSR high during a falling edge of BCLK, the next falling edge of BCLK latches in the sign bit. The following seven falling edges latch in the seven remaining bits. long-frame sync operation Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device determines whether a short- or long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a minimum of 160 ns. The rising edge of FSX or BCLK, whichever occurs later, enables the 3-state output buffer, outputting the sign bit at DX. The next seven rising edges of BCLK shift out the remaining seven bits. The falling edge of BCLK following the eighth rising edge, or FSX going low, whichever occurs later, disables DX. A rising edge on FSR, the receive-frame sync pulse, causes the PCM data at DR to be latched in on the next eight falling edges of BCLK. transmit section The transmit section consists of an input amplifier, filters, and an encoding ADC. The input is an operational amplifier with provision for gain adjustment using two external resistors. The low-noise and wide-bandwidth characteristics of these devices provide gains in excess of 20 dB across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter followed by an eighth-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter is routed to the encoder sample-and-hold circuit. The ADC is a compressing type and converts the analog signal to PCM data in accordance with m-law or A-law coding conventions, as selected. A precision voltage reference provides a nominal input overload voltage of 2.5 V peak. The sampling of the filter output is controlled by the FSX frame-sync pulse; then the successive-approximation encoding cycle begins. The resulting 8-bit code is loaded into a buffer and shifted out through DX at the next FSX pulse. The total encoding delay is approximately 290 ms. Any offset voltage due to the filters or comparator is cancelled by sign-bit integration. receive section The receive section is unity gain and consists of an expanding DAC, filters, and a power amplifier. Decoding is m-law or A-law (as selected by the ASEL terminal), and the decoded analog output signal is routed to the input of a fifth-order switched-capacitor low-pass filter. This filter is clocked at 256 kHz and corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold of the DAC. Next is a second-order RC active post-filter/power amplifier capable of driving an external 600-W load. When FSR goes high, the data at DR is stepped in on the falling edge of the next eight BCLK clocks. At the end of the decoder time slot, the decoding cycle begins and 10 ms later, the decoder DAC output is updated. The decoder delay is about 10 ms (decoder update) plus 110 ms (filter delay) plus 62.5 ms (1/2 frame), or a total of approximately 180 ms.

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APPLICATION INFORMATION

While the terminals of the TP3056B device is well protected against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed-circuit board can be plugged into a hot socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the device ANLG GND terminal. This minimizes the interaction of ground return currents flowing through a common bus impedance. V CC and VBB supplies should be decoupled by connecting 0.1-mF decoupling capacitors to this common point. These bypass capacitors must be connected as close as possible to the device VCC and VBB terminals. For best performance, the ground point of each codec/filter on a card should be connected to a common card ground in star formation rather than via a ground bus. This common ground point should be decoupled to VCC and VBB with 10-mF capacitors. Figure 4 shows a typical TP3056B application. (2.048 MHz) Data Out Digital Interface Analog Interface R2R1 From SLIC (Analog In) PDN

5 V, GND, or –5 V

(Analog Out) 5 V 0.1 mF 0.1 mF –5 V MCLK BCLK DX FSX GSX VFXI– VFXI+ PDN ASEL DR FSR VFRO VCC ANLG GND VBB NOTE A: Transmit gain = 20 log TP3056B /C0466R1 /C0041R2 R2 /C0467, (R1 /C0041R2 )/C011910 k/C0087 TSX 13 Figure 4. Typical Synchronous Application

MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

0.400 (10,15) 0.419 (10,65) 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) A 0.020 (0,51) 0.014 (0,35) 0.293 (7,45) 0.299 (7,59) 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) (15,24) (15,49) PINS ** 0.010 (0,25) NOM A MAX DIM A MIN Gage Plane 0.500 (12,70) (12,95) 0.510 (10,16) (10,41) 0.400 0.410 0.600 0.610 (17,78) 0.700 (18,03) 0.710 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°–8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013

MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER SLWS072A – MAY 1998 – REVISED AUGUST 1998

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

N (R-PDIP-T) PLASTIC DUAL-IN-LINE PACKAGE 0.975 (24,77) 0.940 (23,88) 0.920 0.850 0.775 0.745 (19,69) (18,92) 0.775 (19,69) (18,92) 0.745A MIN DIM A MAX PINS 0.310 (7,87) 0.290 (7,37) (23.37) (21.59) Seating Plane 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 0.070 (1,78) MAX A 0.035 (0,89) MAX 0.020 (0,51) MIN 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) MAX 0.125 (3,18) MIN 0.240 (6,10) 0.260 (6,60) M0.010 (0,25) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

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