TP3040AJ

TP3040 NSC | Alldatasheet

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Y Designed for D3/D4 and CCITT applications Y a5V, b5V power supplies Y Low power consumption: 45 mW (0 dBm0 into 600 X) 30 mW (power amps disabled) Y Power down mode: 0.5 mW Y 20 dB gain adjust range Y No external anti-aliasing components Y Sin x/x correction in receive filter Y 50/60 Hz rejection in transmit filter Y TTL and CMOS compatible logic Y All inputs protected against static discharge due to handling Block Diagram TL/H/6660–1 FIGURE 1 C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltages g7V Power Dissipation 1 W/Package Input Voltage g7V Voltage at Any Input or Output V CC a 0.3V to V BBV b 0.3V Output Short-Circuit Duration Continuous Operating Temperature Range b25§Ct o a125§C Storage Temperature b65§Ct o a150§C Lead Temperature (Soldering, 10 seconds) 300 §C ESD Rating to be determined VCC ea 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. Typicals specified at V digital ground, GNDD. Analog voltages measured with respect to analog ground, GNDA. Symbol Parameter Conditions Min Typ Max Units POWER DISSIPATION ICC0 VCC Standby Current V CC e 5.25V, V BB eb 5.25V, CLK0 and PWRI eb 5.25V (Note 6) 50 100 mAAll other pins at GND (0V) TP3040, TP3040A IBB0 VBB Standby Current V CC e 5.25V, V BB eb 5.25V, CLK0 and PWRI eb 5.25V (Note 6) 50 100 mAAll other pins at GND (0V) TP3040, TP3040A ICC1 VCC Operating Current PWRI e VBB, Power Amp Inactive 3.0 4.0 mA IBB1 VBB Operating Current PWRI e VBB, Power Amp Inactive 3.0 4.0 mA ICC2 VCC Operating Current (Note 1) 4.6 6.4 mA IBB2 VBB Operating Current (Note 1) 4.6 6.4 mA DIGITAL INTERFACE IINC Input Current, CLK V BB s VIN s VCC b10 10 mA IINP Input Current, PDN V BB s VIN s VCC b100 mA IIN0 Input Current, CLK0 V BB s VIN s VCC b 0.5V b10 b0.1 mA VIL Input Low Voltage, CLK, PDN 0 0.8 V VIH Input High Voltage, CLK, PDN 2.2 VCC V VIL0 Input Low Voltage, CLK0 V BB VBBa0.5 V VII0 Input Intermediate Voltage, CLK0 b0.8 0.8 V VIH0 Input High Voltage, CLK0 V CCb0.5 V CC V TRANSMIT INPUT OP AMP IBxI Input Leakage Current, VF xI b3.2V s VIN s a3.2V b100 100 nA RIxI Input Resistance, VF xIV BB s VFxI s VCC 10 M X VOSxI Input Offset Voltage, VF xI b2.5V s VIN s a2.5V b20 20 mV VCM Common-Mode Range, VF xI b2.5 2.5 V CMRR Common-Mode Rejection Ratio b2.5V s VIN s 2.5V 60 dB PSRR Power Supply Rejection of V CC or V BB 60 dB ROL Open Loop Output Resistance, GS x 1k X RL Minimum Load Resistance, GS x 10 k X CL Maximum Load Capacitance, GS x 100 pF VOxI Output Voltage Swing, GS x RL t 10k g2.5 V AVOL Open Loop Voltage Gain, GS x RL t 10k 5,000 V/V Fc Open Loop Unity Gain Bandwidth, GS x 2 MHz

Unless otherwise specified, T Ae25§C. All parameters are specified for a signal level of 0 dBm0 at 1 kHz. The 0 dBm0 level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter. Limits printed in BOLD characters are guaranteed for V CCea 5.0Vg5%, V BB eb 5.0Vg5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. Typicals specified at V CC ea 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units TRANSMIT FILTER (Transmit filter input op amp set to the non-inverting unity gain mode, with VF xIe1.09 Vrms unless otherwise noted.) RLx Minimum Load Resistance, VF xO b2.5VkVOUTk2.5V 3 k X b3.2VkVOUTk3.2V 10 k X CLx Load Capacitance, VF xO 100 pF ROx Output Resistance, VF xO1 3 X PSRR1 V CC Power Supply Rejection, VF xOf e1 kHz, VF xIae 0 Vrms 30 dB PSRR2 V BB Power Supply Rejection, VF xO Same as Above 35 dB GAx Absolute Gain f e1 kHz (TP3040A) 2.9 3.0 3.1 dB fe1 kHz (TP3040) 2.875 3.0 3.125 dB GRx Gain Relative to GA x Below 50 Hz b35 dB

50 Hz b41 b35 dB

60 Hz b35 b30 dB

200 Hz (TP3040A) b1.5 0 dB 200 Hz (TP3040) b1.5 0.05 dB 300 Hz to 3 kHz (TP3040A) b0.125 0.125 dB 300 Hz to 3 kHz (TP3040) b0.15 0.15 dB 3.3 kHz b0.35 0.03 dB 3.4 kHz b0.70 b0.1 dB 4.0 kHz b15 b14 dB 4.6 kHz and Above b32 dB DAx Absolute Delay at 1 kHz 250 ms DDx Differential Envelope Delay from 60 ms 1 kHz to 2.6 kHz DPx1 Single Frequency Distortion b48 dB Products DPx2 Distortion at Maximum Signal 0.16 Vrms, 1 kHz Signal Applied to b45 dB Level VF xIa, Gain e20 dB, R Le10k NCx1 Total C Message Noise at VF xO TP3040, TP3040A 2 5 dBrnc0 NCx2 Total C Message Noise at VF xO Gain Setting Op Amp at 20 dB, Non-Inverting (Note 3) 3 6 dBrnc0TAe0§Ct o7 0 §C TP3040, TP3040A GAxT Temperature Coefficient of 0.0004 dB/ §C 1 kHz Gain GAxS Supply Voltage Coefficient of V CCe5.0Vg5% 0.01 dB/V 1 kHz Gain V BBeb5.0Vg5% CTRX Crosstalk, Receive to Transmit Receive Filter Output e2.2 Vrms b70 dB 20 log VFxO VFRO VFxIae 0 Vrms, f e0.2 kHz to 3.4 kHz Measure VF xO GRxL Gaintracking Relative to GA x Output Level ea 3 dBm0 b0.1 0.1 dB a2 dBm0 to b40 dBm0 b0.05 0.05 dB b40 dBm0 to b55 dBm0 b0.1 0.1 dB

Unless otherwise specified, T Ae25§C. All parameters are specified for a signal level of 0 dBm0 at 1 kHz. The 0 dBm0 level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter. Limits printed in BOLD characters are guaranteed for V CCea 5.0Vg5%, V BB eb 5.0Vg5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. Typicals specified at V CC ea 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units RECEIVE FILTER (Unless otherwise noted, the receive filter is preceded by a sin x/x filter with an input signal level of 1.54 Vrms.) IBR Input Leakage Current, VF RI b3.2VsVINs3.2V b100 100 nA RIR Input Resistance, VF RI1 0 M X ROR Output Resistance, VF RO1 3 X CLR Load Capacitance, VF RO 100 pF RLR Load Resistance, VF RO1 0 k X PSRR3 Power Supply Rejection of V CC or VF RI Connected to GNDA 35 dB VBB,V F ROf e1 kHz VOSRO Output DC Offset, VF ROV F RI Connected to GNDA b200 200 mV fe1 kHz (TP3040) b0.125 0 0.125 dB GRR Gain Relative to Gain at 1 kHz Below 300 Hz 0.125 dB 300 Hz to 3.0 kHz (TP3040A) b0.125 0.125 dB 300 Hz to 3.0 kHz (TP3040) b0.15 0.15 dB 3.3 kHz b0.35 0.03 dB 3.4 kHz b0.7 b0.1 dB 4.0 kHz b14 dB 4.6 kHz and Above b32 dB DDR Differential Envelope Delay 1 kHz 100 ms to 2.6 kHz DPR1 Single Frequency Distortion f e1 kHz b48 dB Products DPR2 Distortion at Maximum Signal 2.2 Vrms Input to Sin x/x Filter, b45 dB Level f e1 kHz, R Le10k NCR Total C-Message Noise at VF RO TP3040, TP3040A 3 5 dBrnc0 GART Temperature Coefficient of 1 kHz 0.0004 dB/ §C Gain GARS Supply Voltage Coefficient of 0.01 dB/V 1 kHz Gain CTXR Crosstalk, Transmit to Receive Transmit Filter Output e2.2 Vrms b70 dB 20 log VFRO VFxO VFRIe0 Vrms, f e0.3 kHz to 3.4 kHz Measure VF RO GRRL Gaintracking Relative to GA R Output Level ea 3 dBm0 b0.1 0.1 dB a2 dBm0 to b40 dBm0 b0.05 0.05 dB b40 dBm0 to b55 dBm0 b0.1 0.1 dB (Note 5)

Unless otherwise specified, T A e 25§C. All parameters are specified for a signal level of 0 dBm0 at 1 kHz. The 0 dBm0 level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter. Limits printed in BOLD characters are guaranteed for V CC ea 5.0V g5%, V BB eb 5.0V g5%; T A e 0§Ct o7 0 §C by correlation with 100% electrical testing at T A e 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. Typicals specified at V CC ea 5.0V, V BB eb 5.0V, T A e 25§C. Symbol Parameter Conditions Min Typ Max Units RECEIVE OUTPUT POWER AMPLIFIER IBP Input Leakage Current, PWRI b3.2V s VIN s 3.2V 0.1 3 mA RIP Input Resistance, PWRI 10 M X ROP1 Output Resistance, PWRO a, PWRO b Amplifiers Active 1 X CLP Load Capacitance, PWRO a, PWRO b 500 pF GApa Gain, PWRI to PWRO a RLe600X Connected Between 1 V/V GApb Gain, PWRI to PWRO b PWROa and PWRO b, Input b1 V/V Levele0 dBm0 (Note 4) GRpL Gaintracking Relative to 0 dBm0 V e2.05 Vrms, R Le600X(Notes 4, 5) b0.1 0.1 dB Output Level, Including Receive Filter V e1.75 Vrms, R Le300X b0.1 0.1 dB S/Dp Signal/Distortion V e2.05 Vrms, R Le600X(Notes 4, 5) b45 dB Ve1.75 Vrms, R Le300X b45 dB VOSP Output DC Offset, PWRO a, PWRO b PWRI Connected to GNDA b50 50 mV PSRR5 Power Supply Rejection of V CC or V BB PWRI Connected to GNDA 45 dB Note 1: Maximum power consumption will depend on the load impedance connected to the power amplifier. This specification listed assumes 0 dBm is delivered to 600X connected from PWRO a to PWRO b. Note 2: Voltage input to receive filter at 0V, VF RO connected to PWRI, 600 X from PWRO a to PWRO b. Output measured from PWRO a to PWRO b. Note 3: The 0 dBm0 level for the filter is assumed to be 1.54 Vrms measured at the output of the XMT or RCV filter. Note 4: The 0 dBm0 level for the power amplifiers is load dependent. For R Le600X to GNDA, the 0 dBm0 level is 1.43 Vrms measured at the amplifier output. For RLe300X the 0 dBm0 level is 1.22 Vrms. Note 5: VFRO connected to PWRI, input signal applied to VF RI. Note 6: Previous revisions of the datasheet did not clearly indicate this specification requires power amps in powerdown (PWRI eb 5.25V). Typical Application TL/H/6660–2 Note 1: Transmit voltage gain eR1 aR2 c 02 (The filter itself introduce sa3d B gain), (R1 aR2 t10k) Note 2: Receive gain e R4 R3 aR4 (R3 aR4t10k) Note: In the configuration shown, the receive filter power amplifiers will drive a 600 X T to R termination to a maximum signal level of 8.5 dBm. An alternative arrangement, using a transformer winding ratio equivalent to 1.414:1 and 300 X resistor, R S, will provide a maximum signal level of 10.1 dBm across a 600 X termination impedance. FIGURE 2

TL/H/6660–3 Top View Order Number TP3040J or TP3040AJ See NS Package J16A or TP3040N or TP3040AN See NS Package N16A Plastic Lead Chip Carrier TL/H/6660–4 Order Number TP3040V or TP3040AV See NS Package V20A Description of Pin Functions Symbol Function VFxIa The non-inverting input to the transmit filter stage. VFxIb The inverting input to the transmit filter stage. GSx The output used for gain adjustments of the transmit filter. VFRO The low power receive filter output. This pin can directly drive the receive port of an electronic hy- brid. PWRI The input to the receive filter differential power amplifier. PWRO a The non-inverting output of the receive filter pow- er amplifier. This output can directly interface conventional transformer hybrids. PWRO b The inverting output of the receive filter power amplifier. This output can be used with PWRO a to differentially drive a transformer hybrid. VBB The negative power supply pin. Recommended input is b5V. VCC The positive power supply pin. The recommend- ed input is 5V. VFRI The input pin for the receive filter stage. Symbol Function GNDD Digital ground input pin. All digital signals are ref- erenced to this pin. CLK Master input clock. Input frequency can be se- lected as 2.048 MHz, 1.544 MHz or 1.536 MHz. PDN The input pin used to power down the TP3040/ TP3040A during idle periods. Logic 1 (V CC) input voltage causes a power down condition. An inter- nal pull-up is provided. CLK0 This input pin selects internal counters in accord- ance with the CLK input clock frequency: CLK Connect CLK0 to: 2048 kHz V CC 1544 kHz GNDD 1536 kHz V BB An internal pull-up is provided. GNDA Analog ground input pin. All analog signals are referenced to this pin. Not internally connected to GNDD. VF xO The output of the transmit filter stage.

The TP3040/TP3040A monolithic filter contains four main sections; Transmit Filter, Receive Filter, Receive Filter Pow- er Amplifier, and Frequency Divider/Select Logic ( Figure 1 ). A brief description of the circuit operation for each section is provided below. TRANSMIT FILTER The input stage of the transmit filter is a CMOS operational amplifier which provides an input resistance of greater than

10 M X, a voltage gain of greater than 5,000, low power

consumption (less than 3 mW), high power supply rejection, and is capable of driving a 10 k X load in parallel with up to 25 pF. The inputs and output of the amplifier are accessible for added flexibility. Non-inverting mode, inverting mode, or differential amplifier mode operation can be implemented with external resistors. It can also be connected to provide a gain of up to 20 dB without degrading the overall filter per- formance. The input stage is followed by a prefilter which is a two-pole RC active low pass filter designed to attenuate high fre- quency noise before the input signal enters the switched-ca- pacitor high pass and low pass filters. A high pass filter is provided to reject 200 Hz or lower noise which may exist in the signal path. The low pass portion of the switched-capacitor filter provides stopband attenuation which exceeds the D3 and D4 specifications as well as the CCITT G712 recommendations (Figure 3). The output stage of the transmit filter, the postfilter, is also a two-pole RC active low pass filter which attenuates clock frequency noise by at least 40 dB. The output of the trans- mit filter is capable of driving a g3.2V peak to peak signal i n t oa1 0k X load in parallel with up to 25 pF. RECEIVE FILTER The input stage of the receive filter is a prefilter which is similar to the transmit prefilter. The prefilter attenuates high frequency noise that may be present on the receive input signal. A switched capacitor low pass filter follows the prefil- ter to provide the necessary passband flatness, stopband rejection and sin x/x gain correction. A postfilter which is similar to the transmit postfilter follows the low pass stage. It attenuates clock frequency noise and provides a low output impedance capable of directly driving an electronic sub- scriber-line-interface circuit (Figure 3). RECEIVE FILTER POWER AMPLIFIERS Two power amplifiers are also provided to interface to trans- former coupled line circuits. These two amplifiers are driven by the output of the receive postfilter through gain setting resistors, R3, R4 ( Figure 2 ). The power amplifiers can be deactivated, when not required, by connecting the power amplifier input (pin 5) to the negative power supply V BB. This reduces the total filter power consumption by approxi- mately 10 mW–20 mW depending on output signal ampli- tude. POWER DOWN CONTROL A power down mode is also provided. A logic 1 power down command applied on the PDN pin (pin 13) will reduce the total filter power consumption to less than 1 mW. Connect PDN to GNDD for normal operation. FREQUENCY DIVIDER AND SELECT LOGIC CIRCUIT This circuit divides the external clock frequency down to the switching frequency of the low pass and high pass switched capacitor filters. The divider also contains a TTL-CMOS in- terface circuit which converts the external TTL clock level to the CMOS logic level required for the divider logic. This in- terface circuit can also be directly driven by CMOS logic. A frequency select circuit is provided to allow the filter to oper- ate with 2.048 MHz, 1.544 MHz or 1.536 MHz clock frequen- cies. By connecting the frequency select pin CLK0 (pin 14) to V CC, a 2.048 MHz clock input frequency is selected. Digi- tal ground selects 1.544 MHz and V BB selects 1.536 MHz. Applications Information GAIN ADJUST Figure 2 shows the signal path interconnections between the TP3040/TP3040A and the TP3020 signal-channel CO- DEC. The transmit RC coupling components have been chosen both for minimum passband droop and to present the correct impedance to the CODEC during sampling. Optimum noise and distortion performance will be obtained from the TP3040/TP3040A filter when operated with sys- tem peak overload voltages of g2.5V to g3.2V at VF xO and VF RO. When interfacing to a PCM CODEC with a peak overload voltage outside this range, further gain or attenua- tion may be required. BOARD LAYOUT Care must be taken in PCB layout to minimize power supply and ground noise. Analog ground (GNDA) of each filter should be connected to digital ground (GNDD) at a single point, which should be bypassed to both power supplies. Further power supply decoupling adjacent to each filter and CODEC is recommended. Ground loops should be avoided, both between GNDA and GNDD and between the GNDA traces of adjacent filters and CODECs.

Typical Performance Characteristics Transmit Filter Stage TL/H/6660–5 Receive Filter Stage TL/H/6660–6 FIGURE 3

Ceramic Dual-In-Line Package (J) Order Number TP3040J or TP3040AJ Molded Dual-In-Line Package (M) Order Number TP3040N or TP3040AN

TP3040, TP3040A PCM Monolithic Filter Physical Dimensions (Continued) Lit. Ý 113919 20-Lead Plastic Chip Carrier Order Number TP3040V or TP3040AV LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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