TP3021

TP3020 NSC | Alldatasheet

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z eo National 8 xy Semiconductor q o TP3020, TP3020-1, TP3021, TP3021-1 8 Monolithic CODECs a u oe General Description Features Ss The TP3020 and TP3021 are monolithic PCM CODECs im- Low operation power—45 mW typical = plemented with double-poly CMOS technology. The TP3020 m Low standby power—1 mW typical ES] is intended for y-law applications and contains logic for uz» m ~+5V operation o 'aw signaling insertion and extraction. The TP3021 is intend- @ TTL compatible digital interface Ss ed for A-law applications, 1 Time slot assignment or alternate fixed time slot modes | 7 Each device contains separate D/A and A/D circuitry, all m internal precision reference - necessary sample and hold capacitors, a precision voltage @ Internal sample and hold capacitors reference and internal auto-zero circuit. A serial control port ce Sache Internal auto-zero circuit allows an external controller to individually assign the PCM Tham au law coding with signat i input and output ports to one of up to 32 time slots or to TP3020—p-law coding with signaling capabilities place the CODEC into a power-down mode. Alternately, the ™ TP3021—A-law coding ; TP3020/TP3021 may be operated in a fixed time slot mode. ™ Synchronous or asynchronous operation Both devices are intended to be used with the TP3040 Monolithic PCM filter which provides the input anti-aliasing function for the encoder and smoothes the output of the decoder and corrects for the sin x/x distortion introduced by the decoder sample and hold output. SFE . Simplified Block Diagram Yor fi rs [area st V S COMPARATOR Coky a 5x H $6, (Tras omy) Lm panes mend rom H Ln ce Gq (TPoez8 OnLY) V ts ono aan TL/H/5690~1 1-3

| Connection Diagrams oO

3 Dual-In-Line Package Dual-In-Line Package

Fy so 24 cake “a ci, 2 23 Fd scr Of sea 2 2 og vty 2 Cay 2 Ea 2 x ; r a0 Vix Ve 8 we sey ac =! 1 ety oS esan — Bax ‘ 1s a man CLK a iG, 4 con, & A 1 w+ wii S ac Bq a op 2 uw a UO 7 fn LKR F " a 4 6 oN J 6 Vee ON Yeo vy Waa vEq = OS net Mt oy net 2 yy we 3 Pvc we tt Rig TUH/5538-3 TUHV5598-4 Top View Top View Order Number TP3020J or TP3020J-1 Order Number TP3021J or TP3021J-1 See NS Package Number J24A See NS Package Number J22A Description of Pin Functions Symbol Function Symbol Function sct Internally connected to GNDA. NC Unused $C2 Connects VFx to an external sample/hold capaci- Dx Serial PCM TRI-STATE® output from the encoder. tor if fitted for use with pin-compatible NMOS CO- During the encoder time slot, the PCM code for the DECGs. Ensures gain compatibility. previous sample of VF is shifted out, most signifi- VFx Analog input to the encoder. This signal will be cant bit first, on the rising edge of CLKx. sampled at the end of the encoder time slot and TSx Time slot output. This TTL compatible open-drain the resulting PCM code will be shifted out during output pulses low during the encoder time siot the subsequent encode time slot. May be used to enable external TRISTATE bus GND Analog and digital ground. All analog and digital drivers if highly capacitive loads must be driven. signals are referenced to this pin. Can be wire ANDed with other TSx outputs. SIGR Receive signaling bit output. During receive signal- Voc SV (+5%) Power Supply. ing frames the least significant (last) bit shifted into CLKa Master decoder clock input used to shift in the Dp is internally latched and appears at this out- PCM data on Dp and to operate the decoder se- put—SIGa will then remain valid until changed dur- quencer. May operate at 1.536 MH;, 1.544 MH; or ing a subsequent receive signaling frame or reset 2048 MHz. May be asynchronous with CLK or by a power-down command. CLKc. Da Serial PCM data input to the decoder. During the FSR Decoder frame sync pulse. Normally occurring at decoder time slot, PCM data is shifted into Dp, an B kHz rate, this pulse is nominally one CLKR most significant bit first, on the falling edge of cycle wide. Extending the width of FSR to two or CLKp. more cycles of CLKp signifies a receive signaling PDN TTL output level which goes high when the CO- frame. DEC is in the power-down mode. May be used to CLKx Master encoder clock input used to shift out the power-down other circuits associated with the PCM data on Dy and to operate the encoder se- PCM channel. quencer. May operate at 1.536 MHz, 1.544 MHz or VFa Analog output from the decoder. The decoder 2.048 MHz. May be asynchronous with CLKR or sample and hold amplifier is updated approximate- CLKe. ly 15 1S after the end of the decode time slot. FSx Encoder frame sync pulse. Normally occurring at an 8 kHz rate, this pulse is nominally one CLKx cycle wide. Extending the width of FSx to two or more cycles of CLK, signifies a transmit signaling frame, 1-4

5 . u Description of Pin Functions (continued) s ‘Symbol Function Symbol Function 8 SIGx Transmit signaling input. During a transmit signal- CLKe Control clock input used to shift serial contro! data 4 ing frame, the signal at SIG is shifted out of Dy in into Oo. CLK must pulse 8 times during a period | place of the least significant (last) bit of PCM data. of time less than or equal to one frame time, al- So Vas —5V (+5%) input. though the 8 pulses may overlap a frame bounda- 8 Dc _ Serial control data input. Serial data on De is shift- coke, need not be synchronous with CLK or | " " LK. Connecting CLK continuously high places ed into the CODEC on the falling edge of CLKe. in the TP9020/TPS21 ints the fired tine sotmon a the fixed time slot mode, Dg doubles as a power- ini ime si * 13 down input. s Absolute Maximum Ratings = Operating Temperature —25°C to + 125°C Voltage at Any Analog rx} Storage Temperature —65°C to + 150°C Input or Output Vep-0.3Vto Veo + 0.8V |B ‘ 2 Voc with Respect to GND wv Voltage at Any Digital cn Vee with Respect to GND -2v Input or Output GND—0.3V to Voc + 0.3V ESD rating is 1o be determined. Lead Temperature (Soldering, 10 seconds) 300°C Unless otherwise noted, limits printed in BOLD characters are guaranteed for Vcc = +5.0V +5%, Vag = —5.0V +5%; Ta = O°C to 70°C by correlation with 100% electrical testing at Ta = 25°C. All other limits are assured by correlation with other Production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at Voc = +5.0V, Vag = —5.0V and Ta = 25°C. symbol | Parameter Gonaitions [win [Typ | Max | Unite DIGITAL INTERFACE u [ putcurent — o<vancveg | = t0 TT t0 Ta Vu Input Low Voltage Po oe Tv Vin | tnputtignvotage JT ae |TV Vou Output Low Voltage Dy, lo = 4.0 mA 0.4 v SIGp, lo, =0.5 mA 0.4 v TS,, lov =3.2 mA, Open Drain 04 v PDN, IoL= 1.6 mA 0.4 v Vou Output High Voltage Dy, lon=6 MA v SIGR, lon=0.6 mA v ANALOG INTERFACE Zz VF, Input Impedance when Resistance in Series with kn Sampling Approximately 70 pF Zo Output impedance at VFa =3.1V<VFA<3.1V [ | » [| 2 | ao Vos Output Offset Voltage at VFR | Dp=PCM Zero Code (TP3020) mv oF Alternating + 1 Code (TP3021) tn AnaloginputBias Curent | vw=ov | on [| on [na mixer | DcBlocking Time Constant [| wo | Toms { cr DcBlockingGapacior | | os at Input Bias Resistor a DS) POWER DISSIPATION loco Standby Current, Voc a SY

1360 Standby Curent, Va OO

loot Operating curentvos | Ts | wo | ma laps Operating curentves | Tas | 0 | ma

pe . . | AC Electrical Characteristics & | _ Unless otherwise noted, the analog input is a 0 dBm0, 1.02 kHz sine wave. The digital input is a PCM bit stream generated by = passing a 0 dBm0, 1.02 kHz sine wave through an ideal encoder. All output levels are sin x/x corrected. Limits printed in BOLD as characters are guaranteed for Voc = +5V +5%, Vap = —5V +5%; Ta = 0°C to + 70°C by correlation with 100% electrical g testing at Ta = 25°C. All other limits are assured by correlation with other production tests and/or product design and character- 2 ization. All signals referenced to GND. Typicals specified at Vcc = +5V, Vag = —5V, Ta = 25°C. |“ symbor [Parameter [Conditions [in| Typ | Max | Units m Absolute Level The nominal 0 dBm0 levels for & the TP3020 and TP3021 are 3 1.520 Vrms and 1.525 Vrms a respectively. The resulting E nominal overload level is 3.096V os peak for both devices. All gain gs measurements for the encode a and decode portions of the & TP3020/TP3021 are based on these nominal levels after the necessary sin x/x corrections are made. Gra Receive Gain, Absolute T=285°C, Voc= 5V, Vap= —5V TP3020, TP3021 -0.125 dB TP3020-1, TP3021-1 —0.175 dB Grat ‘Absolute Receive Gain T=0°C to 70°C dB Variation with Temperature Grav ‘Absolute Receive Gain Voo=5V+5%, dB Variation with Supply Voltage | Vaa=—5V+5% Gx Transmit Gain, Absolute T=25°C, Voo=5V, Vap= —5V TP3020, TP3021 -0.325 —0.075 dB TP3020-1, TP3021-1 -0.375 - 0.025 dB Gyxat Absolute Transmit Gain T=0°C to 70°C 0.05 dB Variation with Temperature Gxav ‘Absolute Transmit Gain Voo=5V +5%, dB Variation with Supply Voltage | Vap=—5V +5% Grat Absolute Receive Gain CCITT Method 2 Relative Variation with Level to -10dBm0 0. dBm0 to 3 dBm0 -0.3 0.3 dB —40 dBm0 to 0 dBm0. -0.2 0.2 dB —50 dBm0 to —40 dBm0 -0.4 0.4 dB —55 dBm0 to —50 dBmO —1.0 1.0 dB Gxat Absolute Transmit Gain CCITT Method 2 Relative Variation with Level to —10 dBmo 0. dBm0 to 3 dBmO0 -0.3 os dB —40 dBm0 to 0 dBm -0.2 0.2 dB —50 dBm0 to —40 dBmO -0.4 0.4 dB —55 dBm0 to ~50 dBm0 -1.0 1.0 dB S/DR Receive Signal to Distortion Sinusoidal Test Method Input Ratio Level —30 dBm0 to 0 dBm0 35 dBc —40 dBm0 29 dBc —45d8m0 25 dBc S/D, Transmit Signal to Distortion Sinusoidal Test Method Input Ratio Level —30 dBm0 to 0 dBmO dBc —40 dBm0 dBc —45dBm0 dBc Nr Receive Idle Channel Noise | Dp=SteadyStatePCMCode | | | | dBc. Nx Transmit Idle Channel Noise TP3020, (No Signaling) dBrncO TP3021 (Note 1) dBn0p HOR Receive Harmonic Distortion | 2nd or 3rd Harmonic ee ee ee ee) HD, Transmit Harmonic Distortion | 2nd or 3rd Harmonic [| [| -a7 [ « PPSRx | Positive Power Supply Input Level= OV, Voc =5.0 Voc 4B Rejection, Transmit +300 mVrms, f= 1.02 kHz Note 1: Measured by extrapolation from the distortion test result at ~ 50 dBm0 level, 1-6

. sai 51 Unless otherwise noted, the analog input is a 0 dBm0, 1.02 kHz sine wave. The digital input is a PCM bit stream generated by 8 passing a 0 dBm0, 1.02 kHz sine wave through an ideal encoder. All output levels are sin x/x corrected. Limits printed in BOLD |“ characters are guaranteed for Vog = +5V +5%, Vag = —5V +5%; Ta = 0°C to +70°C by correlation with 100% electrical | =P testing at T, = 25°C. All other limits are assured by correlation with other production tests and/or product design and character | & ization. All signals referenced to GND. Typicals specified at Voc = +5V, Vag = —5V, Ta = 25°C. 8 Symbol [Parameter | Conditions | min [ typ [Max [units | = PPSRa | Positive Power Supply Dp= Steady PCM Code, a | od Rejection, Receive Voc=5.0 Vp¢ + 300 mVrms, Po F=1.02 kHz 8 NPSRx | Negative Power Supply Input Level = OV, Vag = —5.0 Voc a |= Rejection, Transmit + 300 mVrms, f= 1.02 kHz F| NPSRR Negative Power Supply Dp = Steady PCM Code, dB gs Rejection, Receive Vpp= —5.0 Voc + 300 mVrms, X f= = 1.02 kHz z CTxr Transmit to Receive Crosstalk | Dp =Steady PCM Code [| | -7s | « CTrx Receive to Transmit Crosstalk Transmit Input Level=0V P3020 -70 a8 P3021 =68(Note2) | dB Note 2: Theoretical worst-case for a perfectly zeroed encoder with alternating sign bit, due to the decoding law. Timing Specification uniess otherwise noted, limits printed in BOLD characters are guaranteed for Vog = +5V £5%, Vag = —5V +5%; Ta = 0°C to 70°C by correlation with 100% electrical testing at Ta = 25°C. All other limits are assured by correlation with other production tests and/or product design and characterization. All digital signals referenced to GND. Typicals specified at Voc = +5V, Vas = —5V, Ta = 25°C. All timing parameters are measured at Voy = 2.0V and VoL = 0.7V. Symbol | ___Parameter_—— | Conaitions | Min’ (| Typ | Max | Unite tec Period of Clock CLK, CLK, CLKx [ sass | | | os tac. tec Rise and Fall Time of Clock CLK, CLK, CLKx ee ee ee ee wor Width of Clock High CLKe, CLK, CLK [ses [Tots wou Width of Clock Low CLKo, CLK, CLKx [aes [Tons ta/D A/D Conversion Time From End of Encoder Time Time Slot to Completion of Slots Conversion tova D/A Conversion Time From End of Decoder Time Time Slot to Transition of VFR Slots tspc SetUpTime,Detocike | | too | Tt ‘woe HoldTime,Cikctooc | | too PTs tSFx SetupTimeFsxtocikx, [| too TEs tex HoldTime,Cukxtorsx | | too | ts tozx Delay Time to Enable Dx on CL=150 pF ns TS Entry topx Delay Time, CLkx to Dx = 150 pF re a toxz Delay Time, Dx to High CL=0 pF 165 ns Impedance State on TS Exit forse Delay to TSx Low OSC, < 150 pF [ 30 | | 16 | os {DTSH Delay to TS Off CL =0 pF [| 30 | | te | ns. tssx SetUp Time, SiGxtoCukx | | too PTs tusx HoldTime,CikxtosiGy | | too | Ts 'sra SetUpTimeFSatoClKa | | too | Ts tweR HoldTime,ClkatoFSa | | too | Ts ‘spr SetUpTimaDatocika | | wo Ts yor HoldTime,ClkatoDa | | TT tosr Delay Time, CLKp to SIGR C= 100 pF [ [rT 30 :—*YT ss 1-7

= | &| Timing Waveforms oa e ~~ | wCH 3 ‘Re: ——- ‘FC tik & _ » = tory 8 —] tine a e s Nn a —| HF ay j= tne atte — ‘wen - chk; = cH FSx =}. SIGNALING FRAME (TP3020 ONLY) CUR 1 2 3 4 5 J 7 — oz j— "Dox tonz * a Ga aa Ga Ga Ga Gaal) Gb | [tors —— torsH q ctx, ’ FSR, TS SIGNALING FRAME {TP3020 ONLY) —~| [> 'sor clk , 2 a 4 5 6 7 ' oe » XD tom—-l jae TUWss08-2 1-8

POWER-UP lowed, it is possible that on the frame prior to power-down, | 3 Upon application of power, internal circuitry initializes the the encoder could be assigned to an incorrect time slot | “Ly CODEC and places it into the power-down mode. No se- (e.g. 1, 3, 7, 15 or 31), resulting in a possible PCM bus | "9 quencing of 5V or —5V is required. In the power-down conflict. Ss mode, all non-essential circuits are deactivated, the TAl- SERIAL CONTROL PORT 8 STATE PCM data output Dx is placed in the high impedance When the TP3020/TP3021 is operated in the time slot as- | = state and the receive signaling output of the TP3020, SiGp, . ete signment mode or the fixed time slot mode with continuous a is reset to logical zero. Once in the power-down mode, the jock, the dat ie shifted into the serial control rect UD method of activating the TP3020/TP3021 depends on the clock, the data on Dg is shifted into the serial control regis- | ¢3 chosen mode of operation, time slot assignment or fixed ter, Bit 1 first. in the time slot assignment mode, depending | 3 time slot on B1 and B2, the data in the RCV or XMT time slot regis» | = . ters is updated at the second FSp or FSx pulse after the 4 TIME SLOT ASSIGNMENT MODE first CLK pulse, or the CODEC is powered down. In the | @ The time slot assignment mode of operation is selected by Continuous clock fixed time slot mode, the CODEC Is pow | & maintaining CLKg in a normally low state. The state of the ered up or down at every second FSR or FSx pulse. The = | CODEC is updated by pulsing CLKc eight times within a control register data is interpreted as follows: = period of 125 uS or less. The falling edge of each clock [e1[e2| ss Aetion’ Ss pulse shifts the data on the Dc input into the CODEC. The first two control bits determine if the subsequent control bits 0 Assign time slot to encoder and decoder B3~B8 are to specify the time siot for the encoder (B1 = 0), 0 Assign time slot to encoder the decoder (B2=0) or both (B1 and B2=0) or if the CO- 1 Assign time slot to decoder DEC is to be placed into the power-down mode (B1 and 1 Power-down CODEC B2=1). The desired action will take place upon the occur- rence of the second frame sync pulse following the frst |_83 | 84 | es | 86 | o7 | Be | Timesict | pulse of CLKc. Assigning a time slot to either the encoder or o!lolololo 1 decoder will automatically power-up the entire CODEC cir- o!olololo 2 cuit. The Dx output and Da input, however, will be inhibited o!]oloalo 1 3 for one additional frame to allow the analog circuitry time to 0 0 0 0 1 4 stabilize. If separate time slots are to be assigned to the encoder and the decoder, the encoder time slot should be : . . . . assigned first. This is necessary because up to four frames : . : : : : are required to assign both time slots separately, but only : : : : : three frames are necessary to activate the Dx output. If the 1 1 1 1 1 63 encode time slot has not been updated the PCM data will be 1 1 1 1 1 64 outputted during the previously assigned time slot which may now be assigned to another CODEC. During the power-down command, bits 3 through 8 are ig- nored. Note that with 64 possible time slot assignments it is FIXED TIME SLOT MODE frequently possible to assign a time slot which does not There are several ways in which the TP3020/TP3021 may exist. This can be useful to disable an encoder or decoder operate in the fixed time slot mode. The first and easiest without powering down the CODEC. method is to leave CLKc disconnected or to connect CLK SIGNALING to Voc. In this situation, Dc behaves as a power-down input. When Dc goes low, both encode and decode time slots are The TP3020 p-law CODEC contains circuitry to insert and set to one on the second subsequent frame sync pulse. extract signaling information for the PCM data. The transmit Time slot one corresponds to the eight CLKx or CLKp cy- signaling frame is signified by widening the FSx pulse from cles starting one cycle from the nominal leading edge of one cycle of CLKx to two or more cycles. FS x or FSp respectively. As in the time slot assignment When this occurs, the data present on the SIG, input at the mode, the Dx output is inhibited for one additional frame eighth clock pulse of the encode time slot is inserted into after the circuit is powered up. A logical “1” on Dc powers the last bit of the PCM data stream. A receive signaling the CODEC down on the second subsequent FSy pulse. frame is indicated in a similar fashion by widening the FSR A second fixed time slot method is to operate CLKc continu- pulse to two or more cycles of CLKp. ously. Placing a 1" on Dc will then cause the serial control During a receive signaling frame, the last PCM bit shifted in register to fill up with ones. With B1 and B2 equal to “1” the is latched into a flip-flop and appears at the SIGR output. CODEC will power-down. Placing a “0” on Dg will cause the This output will remain unchanged until the next signaling serial control register to fill up with zeroes, assigning time frame, until a power-down is executed or until power is re- slot one to both the encoder and decoder and powering up moved from the device. Since the least significant bit of the the device. One important restriction with this method of PCM data is lost during a signaling frame, the decoder inter- operation is that the rising transition of Dc must occur at prets the bit as a “1” (ie. half way between a “0” least 8 cycles of CLK¢ prior to FSy. If this restriction is not fol- and a “1”). This minimizes the noise and distortion due to the signaling.

g Functional Description (continued) § | ENCODING DELAY The decoding delay is therefore approximately 28 clock cy- | The encoding process begins at the start of the encode time cles plus one half of a frame time or 81 wS for a 1.544 MHz =| _ slot and is concluded no later than 17 time slots later. In system with an 8 kHz frame rate or 76 HS for a 2.048 MHz | normal applications, this PCM data is not shifted out until system with an 8 kHz frame rate. Again, for some applica- Bd the next time slot 125 S later, resulting in an encoding tions the frame rate could be increased to reduce this delay. = delay of 125 1S. In some applications it is possible to oper- TYPICAL APPLICATION vy) ae the CODEC at a higher frame rate to reduce this delay. A typical application of the TP3020/TP3021 used in con- 3} ith a 2.048 MHz clock, the FS rate could be increased to tenes ica & | 15 kHz reducing the delay from 125 1S to 67 nS. junction with the TP3040 PCM filter is shown. The values of o y » Be. resistor R1 and DG blocking capacitor C1, are non-critical. & DECODING DELAY The capacitor value should exceed 0.1 wF, R1 should not F | The decoding process begins immediately after the end of exceed 160 kM, and the product R1 x C1 should exceed 4 g the decoder time slot. The output of the decoder sample ‘ms. 0.1 yf power supply bypass capacitors should be used Ss and hold amplifier is updated 28 CLKa cycles later. and placed as close to the device as possible. a F i: . Typical Application CLK PON Fy PON _ i _ FROM SLIC. VFyI* VFxO TS, TS Bs hd CLK if CLK RZ AS FS Fi V7 T | sc: rraeaoy cu bal id ro. MO - SB 7e3021 Ri TO SLC GNOA GND FSR wae PWR Gnoo a VERO VFal VFR Ra hed vi vi v vi V7 (iy cc =vVU V BB cc “TS > 0.1 YF i > +50 naam iv Ro + Re TS —— Ra RCV gain = 20 x log (wis + a) for each power amplifer TUH/5596-5 The power supply decoupling capacitors should be 0.1 uF. In order to take advantage of the excellent noise performance of the TP3020/TP3021/TP3040, care must be taken in board layout to prevent coupling of digital noise into the sensitive analog lines. “The external sample/hold capacitor required for use with pin-compatible NMOS CODECS introduces attenuation due to the capacitive divider formed with C1. The SC pin connects VF, to this sample/hold capacitor (via a 3002 resistor) to ensure gain compatibility. The TP3020/TP3021 itself does not require an external sample/hold capacitor. 1-10