TP23753

TPS23753 TI | Alldatasheet

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0.1µ F RDEN RCLS From Ethernet Transformers VDD1 VSS CLS CIN VOUT RCTL CCTL From Spare Pairs or Transformers DSDEN BLNK FRSDA RFRS VB CVBAdapter RFBU RFBL TLV431 ROB CIZ APD RAPD2 RAPD1 RBLNK VDD CIO BR1 BR2 RVC * Adapter□interface□and□RBLNK are□Optional TPS23753 www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 IEEE 802.3-2005 PoE INTERFACE AND ISOLATED CONVERTER CONTROLLER Optimized for Isolated Converters Complete PoE Interface The TPS23753 is a combined Power over Ethernet (PoE) powered device (PD) interface and Adapter ORing Support current-mode dc/dc controller optimized specifically V Adapter Support for isolated converter designs. The PoE Programmable Frequency with Synch. implementation supports the IEEE 802.3-2005 (previously 802.3af) standard, 12.95 W (13 PD. Robust 100 0.7 Ω Hotswap MOSFET Small TSSOP Package The TPS23753 supports a number of input-voltage ORing options including highest voltage, external kV kV System Level ESD Capable adapter preference, and PoE preference. C to 125 C Junction Temperature Range The PoE interface MOSFET. This allows the PoE function to be turned off. Classification can be programmed to any of the defined types with a single resistor. IEEE 802.3-2005 Compliant Powered Devices VoIP Telephones The dc/dc controller a bootstrap startup Access Points mechanism with an internal, switched current source. This provides the advantages of cycling overload fault Security Cameras protection without the constant power loss of a pull up resistor. The programmable oscillator may be synchronized to a higher-frequency external timing reference. Figure Basic TPS23753 Implementation Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1) DISSIPATION RATINGS TPS23753 SLVS853A JUNE 2008 REVISED JUNE 2008 www.ti.com This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either V CC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. PRODUCT INFORMATION (1) DEVICE DUTY CYCLE POE UVLO ON HYST. PACKAGE MARKING TPS23753 80% 35/4.5 PW (TSSOP-14) TP23753 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Voltags are with respect to V SS (unless otherwise noted) VALUE UNIT V DD V DD1 DEN, RTN (2) 0.3 to 100 V V DD1 to RTN 0.3 to 100 V CLS (3) 0.3 to 6.5 V V I Input voltage range [APD, BLNK (3) CTL, FRS (3) V B (3) to RTN 0.3 to 6.5 V CS to RTN 0.3 to V B V V C to RTN 0.3 to V GATE to RTN 0.3 to V C 0.3 V Sourcing current V B Internally limited mA Average sourcing or sinking current GATE mA RMS HBM kV ESD rating CDM 500 V ESD system level (contact/air) (4) kV to Internally T J Operating junction temperature range C Limited (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) I RTN for V RTN 80V. (3) Do not apply voltage to these pins. (4) Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the TPS23753EVM-001 (HPA304-001) evaluation module (documentation available on the web). These were the test levels, not the failure threshold. θ JT θ JA θ JA PACKAGE C/W) (1) C/W) (2) C/W) (1) PW (TSSOP-14) 0.97 173.6 99.3 (1) JEDEC method with high-k board layers, signal and planes). (2) JEDEC method with low-k board signal layers). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 Voltage with respect to V SS (unless otherwise noted) MIN NOM MAX UNIT Input voltage range, V DD V DD1 RTN V Input voltage range, V DD V DD1 to RTN V V I Input voltage range, V C to RTN V Input voltage range, APD, CTL to RTN V B V Input voltage range, CS to RTN V RTN current J 125 350 mA V B sourcing current 2.5 mA V B capacitance 0.08 0.1 2.2 µ F R BLNK 350 k Ω Synchronization pulse width input (when used) 150 ns T J Operating junction temperature range 125 C Unless otherwise noted: CS APD CTL RTN, GATE open, R FRS 60.4 k Ω R BLNK 249 k Ω C VB C VC 0.1 µ R DEN 24.9 k Ω R CLS open, V VDD-VSS V VDD1-RTN 8.5 V V VC-RTN C T J 125 C Controller Section Only SS RTN and V DD V DD1 or SS RTN V DD all voltages referred to RTN. Typical specifications are at PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V C UVLO V C rising 8.65 9.3 Undervoltage lockout V UVLO H Hysteresis (1) 3.3 3.5 3.7 Operating current V C CTL V B 0.40 0.58 0.85 mA V DD1 10.2 V C (0) V 175 t ST Startup time, C VC µ F ms V DD1 V C (0) V V DD1 10.2 V VC 8.6 V 0.44 1.06 1.80 Startup current source I VC mA V DD1 V VC V 2.5 4.3 6.0 V B Voltage 6.5 V V C I VB mA 4.75 5.10 5.25 V FRS CTL= V B Measure GATE Switching frequency 223 248 273 kHz R FRS 60.4 k Ω D MAX Duty cycle CTL= V B Measure GATE 78.5 V SYNC Synchronization Input threshold 2.0 2.2 2.4 V CTL V ZDC duty cycle threshold V CTL until GATE stops 1.3 1.5 1.7 V Softstart period Interval from switching start to V CSMAX 400 800 µ s Input resistance 100 145 k Ω BLNK In addition to t Blanking delay BLNK RTN ns R BLNK 49.9 k Ω CS V CSMAX Maximum threshold voltage V CTL V B V CS until GATE duty cycle drops 0.50 0.55 0.60 V t Turn off delay V CS 0.65 V ns V SLOPE Internal slope compensation voltage Peak voltage at maximum duty cycle, referred to CS 118 142 mV I SL_EX Peak slope compensation current V CTL V B I CS at maximum duty cycle (ac component) µ A Bias current (sourcing) Gate high, dc component of CS current 4.2 µ A (1) The hysteresis tolerance tracks the rising threshold for a given device. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted: CS APD CTL RTN, GATE open, R FRS 60.4 k Ω R BLNK 249 k Ω C VB C VC 0.1 µ R DEN 24.9 k Ω R CLS open, V VDD-VSS V VDD1-RTN 8.5 V V VC-RTN C T J 125 C Controller Section Only SS RTN and V DD V DD1 or SS RTN V DD all voltages referred to RTN. Typical specifications are at PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GATE Source current V CTL V B V C GATE high, Pulsed measurement 0.30 0.46 0.60 A Sink current V CTL V B V C GATE low, Pulsed measurement 0.50 0.79 1.1 A APD V APDEN V APD 1.42 1.5 1.58 Threshold voltage V V APDH Hysteresis (2) 0.28 0.3 0.32 THERMAL SHUTDOWN Turn off temperature 135 145 155 C Hysteresis (3) C (2) The hysteresis tolerance tracks the rising threshold for a given device. (3) These parameters are provided for reference only, and do not constitute part of TI s published device specifications for purposes of TI s product warranty. PoE and Control DD V DD1 or DD1 RTN, V VC-RTN all voltages referred to V SS Typical specifications are at PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DEN (DETECTION) DD V DD1 RTN V SUPPLY positive) Measure I SUPPLY Detection current V DD 1.6 V 64.3 66.5 µ A V DD V 399 406 413 Detection bias current V DD DEN open, Measure I SUPPLY 5.2 µ A V PD_DIS Hotswap disable threshold V I lkg DEN leakage current V DEN V DD Float V DD1 and RTN, Measure I DEN 0.1 µ A CLS (CLASSIFICATION) DD V DD1 RTN V SUPPLY positive) V V DD Measure I SUPPLY R CLS 1270 Ω 1.8 2.14 2.4 R CLS 243 Ω 9.9 10.6 11.3 I CLS Classification current mA R CLS 137 Ω 17.6 18.6 19.4 R CLS 90.9 Ω 26.5 27.9 29.3 R CLS 63.4 Ω 39.9 V CL_ON Regulator turns on, V DD rising 11.7 Classification regulator lower V threshold V CL_HYS Hysteresis (1) 1.9 2.05 2.2 V CU_OFF Regulator turns off, V DD rising Classification regulator upper V threshold V CU_HYS Hysteresis (1) 0.5 0.77 I lkg Leakage current V DD V CLS DEN V SS Measure I CLS µ A RTN (PASS DEVICE) DD1 RTN) On resistance 0.7 1.2 Ω Current limit V RTN 1.5 V DD Pulsed Measurement 405 450 505 mA Inrush limit V RTN V DD V Pulsed Measurement 100 140 180 mA Foldback voltage threshold V DD rising 12.3 13.6 V I lkg Leakage current V DD V RTN 100 DEN V SS µ A UVLO UVLO_R V DD rising 33.9 36.1 Undervoltage lockout threshold V UVLO_H Hysteresis (1) 4.40 4.55 4.70 (1) The hysteresis tolerance tracks the rising threshold for a given device. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

12 APD

www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 ELECTRICAL CHARACTERISTICS (continued) PoE and Control DD V DD1 or DD1 RTN, V VC-RTN all voltages referred to V SS Typical specifications are at PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN Turn off temperature 135 145 155 C Hysteresis (2) C (2) These parameters are provided for reference only, and do not constitute part of TI s published device specifications for purposes of TI s product warranty. TOP VIEW Table Terminal Functions TERMINAL I/O NO. NAME CTL I The control loop input to the PWM (pulse width modulator). Use V B as a pull up for CTL. V bias rail for dc/dc control circuits. Apply a 0.1 µ F to RTN. V B may be used to bias an external V B O optocoupler for feedback. Dc/dc converter switching MOSFET current sense input. Connect CS to the high side of the CS I RTN-referenced current sense resistor. Dc/dc converter bias voltage. The internal startup current source and converter bias winding output V C I/O power this pin. Connect a 0.22 µ F minimum ceramic capacitor to RTN, and a larger capacitor to facilitate startup. GATE O Gate drive output for the dc/dc converter switching MOSFET. RTN RTN is the negative rail input to the dc/dc converter and output of the PoE hotswap. V SS Negative power rail derived from the PoE source. V DD1 Source of dc/dc converter startup current. Connect to V DD for most applications. V DD Positive input power rail for PoE interface circuit. Derived from the PoE source. Connect a 24.9 k Ω resistor from DEN to V DD to provide the PoE detection signature. Pulling this pin DEN I/O to V SS during powered operation causes the internal hotswap MOSFET to turn off. CLS O Connect a resistor from CLS to V SS to program the classification current per Table Pull APD above 1.5 V to disable the internal PD hotswap switch, forcing power to come from an APD I external adapter. Connect to the adapter through a resistor divider. Connect to RTN to utilize the internally set blanking period or connect through a resistor to RTN to BLNK I/O program the blanking period. FRS I/O Connect a resistor from FRS to RTN to program the converter switching frequency. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

D CLRB Q Oscillator

1 GATE

CONV. OFF 800 s/c109 400 s/c109 Soft□Start 0.55V 0.75V CK RTN CS enb 11.5V□& 9.5V 22V□& 21.25V 35V & 30.5V Class Regulator 80m/c87 S R Q 12.5V & 1V ILIMbH L Common Circuits□and PoE□Thermal Monitor RTN CLS VSS DEN EN 2.53V CONV. OFF 4.5V

40 A/c109

(pk) Converter Thermal Monitor 2.875k/c87 50k/c87 50k/c87 APD 1.5V &1.2VAPDb APDbAUXb AUXb Blank Switch Matrix VDD VC Pin www.ti.com Figure TPS23753 Functional Block Diagram Refer to Figure for component reference designators CS for example and the Electrical Characteristics table for values denoted by reference CSMAX for example). Electrical Characteristic values take precedence over any numerical values used in the following sections. APD APD forces power to come from an external adapter connected from V DD1 to RTN by opening the hotswap switch. A resistor divider is recommended on APD when it is connected to an external adapter. The divider provides ESD protection, leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage qualification assures the adapter can support the PD before the PoE current is cut off. Select the APD divider resistors per the following equations where V ADPTR-ON is the desired adapter voltage that enables the APD function as adapter voltage rises. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

( )1 2 _APD APD ADPTR ON APDEN APDENR R V V V= ⋅ − (1) ( ) 1 2 APD APD ADPTR OFF APDEN APDH APD R RV V V R += ⋅ − (2) ( ) ( )BLNK BLNKR k t nsΩ = (3) TPS23753 www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 The CLS output is disabled when a voltage above V APDEN is applied to the APD pin. Place the APD pull-down resistor adjacent to the APD pin. APD should be tied to RTN when not used. BLNK Blanking provides an interval between the gate drive going high and the current comparator on CS actively monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the comparator is active, preventing undesired short duty cycles and premature current limiting. Connect BLNK to RTN to obtain the internally set blanking period. Connect a resistor from BLNK to RTN for a programmable blanking period. The relationship between the desired blanking period and the programming resistor is defined by the following equation. Place the resistor adjacent to the BLNK pin when it is used. CLS Connect a resistor from CLS to V SS to program the classification current per IEEE 802.3-2005 and preliminary 802.3at specifications. The PD power ranges and corresponding resistor values are listed in Table The power assigned should correspond to the maximum average power drawn by the PD during operation. The TPS23753 supports class power levels. CS The current sense input for the dc/dc converter should be connected to the high side of the switching MOSFET s current sense resistor. The current-limit threshold, V CSMAX defines the voltage on CS above which the GATE ON time will be terminated regardless of the voltage on CTL. The TPS23753 provides internal slope compensation to stabilize the current mode control loop. If the provided slope is not sufficient, the effective slope may be increased by addition of R S per Figure Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy traces such as the gate drive signal. CTL CTL is the voltage control loop input to the PWM (pulse width modulator). Pulling V CTL below V ZDC causes GATE to stop switching. Increasing V CTL above V ZDC raises the switching MOSFET programmed peak current. The maximum (peak) current is requested at approximately V ZDC V CSMAX The ac gain from CTL to the PWM comparator is 0.5. Use V B as a pull up source for CTL. DEN Connect a 24.9 k Ω resistor from DEN to V DD to provide the PoE detection signature. DEN goes to a high impedance state when not in the detection voltage range. Pulling DEN to V SS during powered operation causes the internal hotswap MOSFET and class regulator to turn off. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

15000( ) ( ) FRS SW R k f kHz Ω = (4) TPS23753 SLVS853A JUNE 2008 REVISED JUNE 2008 www.ti.com FRS Connect a resistor from FRS to RTN to program the converter switching frequency. Select the resistor per the following relationship. The converter may be synchronized to a frequency above its maximum free-running frequency by applying short ac-coupled pulses into the FRS pin. More information is provided in the section. The FRS pin is high impedance. Keep the connections short and apart from potential noise sources. GATE Gate drive output for the dc/dc converter switching MOSFET. RTN RTN is internally connected to the drain of the PoE hotswap MOSFET, and the dc/dc controller return. RTN should be treated as a local reference plane (ground plane) for the dc/dc controller and converter primary to maintain signal integrity. V B V B is an internal control rail that should be bypassed by a 0.1 µ F capacitor to RTN. V B should be used to bias the feedback optocoupler. V C V C is the bias supply for the dc/dc controller. The MOSFET gate driver runs directly from V C V B is regulated down from V C and is the bias voltage for the rest of the converter control. A startup current source from V DD1 to V C is controlled by a comparator with hysteresis to implement a bootstrap startup of the converter. V C must be connected to a bias source, such as a converter auxiliary output, during normal operation. A minimum 0.22 µ F capacitor, located adjacent to the V C pin, should be connected from V C to RTN to bypass the gate driver. A larger total capacitance is required for startup. V DD Positive input power rail for PoE control that is derived from the PoE. V DD should be bypassed to V SS with a 0.1 µ F (X7R,10%) capacitor as required by the standard. A transient suppressor (Zener) diode, should be connected from V DD to V SS to protect against overvoltage transients. V DD1 Source of dc/dc converter startup current. Connect to V DD for most applications. V DD1 may be isolated by a diode from V DD to support PoE priority operation. V SS V SS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited hotswap switch that connects it to RTN. V SS is clamped to a diode drop above RTN by the hotswap switch. A local V SS reference plane should be used to connect the input components and the V SS pin. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

-40 -20 0 20 40 60 80 100 120 T -□Junction□Temperature□-□°CJ 0 2 4 6 8 10 I -□□Bias□Current□- A VDD /c109 V -□PoE□Voltage□-□VVDD-VSS T =□125°CJ T =□25°CJ T =□-40°CJ 5 10 15 20 25 30 35 40 45 50 55 60 V =□8.6□VVC I -□Source□Current□-□mAVC V -□VVDD1-RTN T =□-40°CJ T =□25°CJ T =□125°CJ 100 120 140 160 -40 -20 0 20 40 60 80 100 120 Converter□Start□Time□-□ms T -□Junction□Temperature□-□°CJ C =□22 FVC /c109 V =□10.2□VVDD1 V =□19.2□VVDD1 V =□35□VVDD1 100 200 300 400 500 600 700 800 900 1000 -40 -20 0 20 40 60 80 100 120 T -□Junction□Temperature□-□°CJ I -□Sinking□- A VC /c109 Gate□Open V =□12□V VC 500□kHz 250□kHz 100□kHz 50□kHz V =□0□VCTL 200 400 600 800 1000 1200 7 9 11 13 15 17 V -□Controller□Bias□Voltage□-□VC V -□Controller□Bias□Current□- A C /c109 Gate□Open T =□25°C J 500□kHz 250□kHz 100□kHz 50□kHz V =□0□VCTL TPS23753 www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 DETECTION BIAS CURRENT PoE CURRENT LIMIT vs vs VOLTAGE TEMPERATURE Figure Figure CONVERTER START TIME CONVERTER STARTUP SOURCE CURRENT vs vs TEMPERATURE V VDD1 Figure Figure CONTROLLER BIAS CURRENT CONTROLLER BIAS CURRENT vs vs TEMPERATURE VOLTAGE Figure Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

-40 -20 0 20 40 60 80 100 120 350 400 450 500 550 600 650 R =□60.4□k (250□kHz)FRS /c87 R =□30.1□k (500□kHz)FRS /c87 R =□148.5□k (100□kHz)FRS /c87 R =□301□k (50□kHz)FRS /c87Switching□Frequency□-□Hz Switching□Frequency□-□Hz T -□Junction□Temperature□-□°CJ 100 200 300 400 500 600 700 800 0 10 20 30 40 50 Switching□Frequency□-□kHz Programmed□Resistance□□(10 /□R )□-6 -1 FRS /c87 Ideal Typical 76.5 77.5 78.5 -40 -20 0 20 40 60 80 100 120 Maximum□Duty□Cycle□-□% T -□Junction□Temperature□-□°CJ R =□301□k (50□kHz)FRS /c87 R =□148.5□k (100□kHz)FRS /c87 R =□60.4□k (250□kHz)FRS /c87 R =□30.1□k (500□kHz)FRS /c87 1 14 1 16 1 18 120 122 124 -40 -20 0 20 40 60 80 100 120 V -□Slope□Compensation□-□mV SLOPE PP T -□Junction□Temperature□-□°CJ TPS23753 SLVS853A JUNE 2008 REVISED JUNE 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY SWITCHING FREQUENCY vs vs TEMPERATURE PROGRAMMED RESISTANCE Figure Figure 10. MAXIMUM DUTY CYCLE CURRENT SLOPE COMPENSATION VOLTAGE vs vs TEMPERATURE TEMPERATURE Figure 11. Figure 12. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

-40 -20 0 20 40 60 80 100 120 I -□Slope□Compensation□- ASL OPE PP /c109 T -□Junction□Temperature□-□°CJ 105 115 -40 -20 0 20 40 60 80 100 120 235 240 245 250 255 260 265 270 T -□Junction□Temperature□-□°CJ Blanking□Period□(R <115□k )□-□ns BLNK /c87 Blanking□Period□(R >115□kW)□-□ns BLN K R =□RTNBLNK R =□249□kBLNK /c87 R =□100□kBLNK /c87 R =□49.9□kBLNK /c87 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 -18 -14 -10 Blanking□Period□-□ns R -□kBLNK /c87 Difference□from□Computed□-□ns TPS23753 www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) CURRENT SLOPE COMPENSATION CURRENT BLANKING PERIOD vs vs TEMPERATURE TEMPERATURE Figure 13. Figure 14. BLANKING PERIOD vs R BLNK Figure 15. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

5742363020.514.510.12.7 Detection Lower L imit Detection Upper LimitClassification Low erLim it Cla ssification Upper Limit Mu st Tu rn Off by - Volta ge Falling Lower Limit - Prope r OperationM ustTurn O n by- Voltage Rising Ma ximu mInput Voltage Detect Classify Shut- down PI Voltage (V) 3/06/08 Threshold Voltages TPS23753 SLVS853A JUNE 2008 REVISED JUNE 2008 www.ti.com The following text is intended as an aid in understanding the operation of the TPS23753 but not as a substitute for the actual IEEE 802.3-2005 or 802.3at standard. The pending IEEE 802.3at standard is an update to IEEE 802.3-2005 clause (PoE), adding high-power options and enhanced classification. Generally speaking, a device compliant to IEEE 802.3-2005 will be referred to as a Type device, and devices with high power or enhanced classification will be referred to as Type devices. Standards change and should always be referenced when making design decisions. The IEEE 802.3-2005 (802.3at) standard defines a method of safely powering a PD (powered device) over a cable, and then removing power if a PD is disconnected. The process proceeds through an idle state and three operational states of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it periodically looks to see if something has been plugged in; this is referred to as detection. The low power levels used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may inquire how much power the PD requires; this is referred to as classification. Type PSEs are required to do hardware classification. The PD may return the default 12.95W (often refered to as 13W) current-encoded class, or one of four other choices. The PSE may then power the PD if it has adequate capacity. Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure shows the operational states as a function of PD input voltage. Figure 16. IEEE 802.3-2005 (Type Operational States The PD input is typically an RJ-45 eight-lead connector which is referred to as the power interface (PI). PD input requirements differ from PSE output requirements to account for voltage drops in the cable and operating margin. The IEEE 802.3-2005 standard uses a cable resistance of Ω to derive the voltage limits at the PD based on the PSE output voltage requirements. Although the standard specifies an output power of 15.4 W at the PSE, only 12.95 W is available at the PI due to the worst-case power loss in the cable. The PSE can apply voltage either between the RX and TX pairs (pins and for 10baseT or 100baseT), or between the two spare pairs and 8). The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges to accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges create a difference between the standard limits at the PI and the TPS23753 specifications. The PSE is permitted to disconnect a PD if it draws more than its maximum class power over a one second interval. A PSE compliant to IEEE 802.3-2005 is required to limit current to between 400 mA and 450 mA during powered operation, and it must disconnect the PD if it draws this current for more than ms. Class and PDs may draw up to 400 mA peak currents for up to ms. The PSE may set lower output current limits based on the PD s declared power requirements. The TPS23753 has a number of internal comparators with hysteresis for stable switching between the various states as shown in Figure Figure relates the parameters in the Electrical Characteristics section to the PoE states. The mode labeled idle between classification and operation implies that the DEN, CLS, and RTN pins are all high impedance. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

VUVLO_R Detection Classification PD Powered Idle VCL_ON VCL_HYS 1.4V VCU_OFF VCU_HYS Note: Variable names refer to Electrical Characteristic Table parameters VVDD-VSS VUVLO_H Operational State PoE Startup Sequence Detection TPS23753 www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 Figure 17. Threshold Voltages The waveforms of Figure demonstrate detection, classification, and startup from a PSE. The key waveforms shown are V VDD-VSS V RTN-VSS and I PI IEEE 802.3-2005 requires a minimum of two detection levels, however four levels are shown in this example. Four levels guard against misdetection of a device when plugged in during the detection sequence. Figure 18. PoE Startup Sequence The TPS23753 is in detection mode whenever V VDD-V SS is below the lower classification threshold. When the input voltage rises above V CL_ON the DEN pin goes to an open-drain condition to conserve power. While in detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to V SS An R DEN of 24.9 k Ω (1%), presents the correct signature. It may be a small, low-power resistor since it only sees a stress of about mW. A valid PD detection signature is an incremental resistance between 23.75 k Ω and 26.25 k Ω at the PI. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

(MPS) TPS23753 Operation Startup and Converter Operation TPS23753 SLVS853A JUNE 2008 REVISED JUNE 2008 www.ti.com The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the parallel combination of R DEN and the TPS23753 bias loading. The input diode bridge s incremental resistance may be hundreds of Ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is partially cancelled by the TPS23753's effective resistance during detection. Hardware classification allows a PSE to determine a PD s power requirements before starting and helps with power management once power is applied. The maximum power entries in Table determine the class the PD must advertise. A Type PD may not advertise Class The PSE may disconnect a PD if it draws more than its stated Class power. The standard permits the PD to draw limited current peaks, however the average power requirement always applies. Voltage between 14.5 V and 20.5 V is applied to the PD for up to ms during hardware Classification. A fixed output voltage is sourced by the CLS pin, causing a fixed current to be drawn from V DD through R CLS The total current drawn from the PSE during classification is the sum of bias and R CLS currents. PD current is measured and decoded by the PSE to determine which of the five available classes is advertised (see Table The TPS23753 disables classification above V CU_OFF to avoid excessive power dissipation. CLS voltage is turned off during PD thermal limit or when APD or DEN are active. The CLS output is inherently current limited, but should not be shorted to V SS for long periods of time. Table Class Resistor Selection POWER AT PD PI Class Current Requirement CLASS RESISTOR Ω NOTES MINIMUM MAXIMUM MAXIMUM (W) MINIMUM (mA) (W) (mA) 0.44 12.95 1270 0.44 3.84 243 3.84 6.49 137 6.49 12.95 90.9 802.3at only, not allowed for IEEE 12.95 25.5 63.4 802.3-2005 (type devices) The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating voltage is applied. A valid MPS consists of a minimum dc current of mA (at a duty cycle of at least ms on every 225 ms) and an ac impedance lower than 26.25 k Ω in parallel with 0.05 µ The ac impedance is usually accomplished by the minimum C IN requirement of µ When APD or DEN are used to force the hotswap switch off, the dc MPS will not be met. A PSE that monitors the dc MPS will remove power from the PD when this occurs. A PSE that monitors only the ac MPS may remove power from the PD. The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits will discharge C IN C VC and C VB while the PD is unpowered. Thus V RTN-VDD will be a small voltage just after full voltage is applied to the PD, as seen in Figure The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When V DD rises above the UVLO turn-on threshold UVLO-R ~35 with RTN high, the TPS23753 enables the hotswap MOSFET with a ~140 mA (inrush) current limit. Refer to the waveforms of Figure for an example. Converter switching is disabled while C IN charges and V RTN falls from V DD to nearly V SS however the converter startup circuit is allowed to charge C VC Once the inrush current falls about 10% below the inrush current limit, the PD control switches to the operational level (~450 mA) and converter switching is permitted. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

000.0E -0.7 -0.6 -0.5 IPI VDD-RTN VC-RTN INRUSH Turn□ONVOUT 50V/DIV 2V/DIV 10V/DIV 100mA/Div Exaggerated□primary- secondary□softstart□handoff PD Interface www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 Converter switching is allowed if the PD is not in inrush and the V C under-voltage lock out (UVLO) permits it. Continuing the startup sequence shown in Figure V VC rises as the startup current source charges C VC and switching is inhibited by the status of the V C UVLO. The V B regulator powers the internal converter circuits as V VC rises. Startup current is turned off, converter switching is enabled, and a softstart cycle starts when V VC exceeds UVLO (~9 V). V VC falls as it powers both the internal circuits and the switching MOSFET gate. If the converter control-bias output rises to support V VC before it falls to UVLO UVLO (~5.5 V), a successful startup occurs. Figure shows a small droop in V VC while the output voltage rises smoothly and a successful startup occurs. Figure 19. Power Up and Start If V VDD-VSS drops below the lower PoE UVLO (UVLO R UVLO H ~30.5 V), the hotswap MOSFET is turned off, but the converter will still run. The converter will stop if V VC falls below the converter UVLO (UVLO UVLO H ~5.5 V), the hotswap is in inrush current limit, or duty cycle is demanded by V CTL CTL V ZDC ~1.5 V), or the converter is in thermal shutdown. The PD section has the following functions, with the first four covered above. Detection Classification V DD to V SS UVLO Orderly sequencing of C IN charge and converter operation Hotswap switch current limit Hotswap switch foldback Hotswap thermal protection The internal hotswap MOSFET is protected against output faults with a current limit and deglitched foldback. The PSE output cannot be relied on to protect the PD MOSFET against transient conditions, so the PD implements its own protection. High stress conditions include converter output shorts, shorts from V DD to RTN, or transients on the input line. An overload on the pass MOSFET engages the current limit, with V RTN-VSS rising as a result. If V RTN rises above ~12 V for longer than ~400 µ the current limit reverts to the inrush limit, and turns the converter off. The 400 µ s deglitch feature prevents momentary transients from causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure shows an example of recovery from a V PSE rising voltage step. The hotswap MOSFET goes into current limit, overshooting to a relatively low current, recovers to 420 mA full current limit, and charges the input capacitor while the converter continues to run. The MOSFET did not go into foldback because V RTN-VSS was below V after the 400 µ s deglitch. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

www.ti.com Figure 20. Response to PSE Step Voltage The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or operation into a V DD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown (OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD state machine will always restart in inrush current limit when exiting from a PD overtemperature event. Pulling DEN to V SS during powered operation causes the internal hotswap MOSFET to turn off. This feature allows a PD with secondary-side adapter ORing to achieve adapter priority. Care must be taken with synchronous converter topologies that can deliver power in both directions. The hotswap switch will be forced off under the following conditions: V APD above V APDEN (~1.5 V DE N V PD_DIS when V VDD-VSS is in the operational range PD over temperature V VDD-VSS PoE UVLO (~30.5 V). The TPS23753 dc/dc controller implements a typical current-mode control as shown in Figure oscillator, overcurrent and PWM comparators, current-sense blanker, softstart, and gate driver. In addition, an internal current-compensation ramp generator, frequency synchronization logic, thermal shutdown, and startup current source with control are provided. The TPS23753 is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM and converter. There is an offset of V ZDC (~1.5 and 2:1 resistor divider between the CTL pin and the PWM. A V CTL below V ZDC will stop converter switching, while voltages above ZDC V CSMAX will not increase the requested peak current in the switching MOSFET. Optocoupler biasing design is eased by this limited control range. The internal startup current source and control logic implement a bootstrap-type startup. The startup current source charges C VC from V DD1 when the converter is disabled (either by the PD control or the V C control), while operational power must come from a converter (bias winding) output. Loading on V C and V B must be minimal while C VC charges, otherwise the converter may never start. The optocoupler will not load V B when the converter is off. The converter will shut off when V C falls below its lower UVLO. This can happen when power is removed from the PD, or during a fault on a converter output rail. When one output is shorted, all the outputs fall in voltage including the one that powers V C The control circuit discharges V C until it hits the lower UVLO and turns off. A restart will initiate as described in "Startup and Converter Operation" if the converter turns off and there is sufficient V DD1 voltage. This type of operation is sometimes referred to as hiccup mode, which provides robust output short protection by providing time-average heating reduction of the output rectifier. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

From□Regulated Output□Voltage Special Switching MOSFET Considerations TPS23753 www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 Care in design of the transformer and V C bias circuit is required to obtain hiccup overload protection. Leading-edge voltage overshoot on the bias winding may cause V C to peak-charge, preventing the expected tracking with output voltage. R VC Figure is often required slow the peak charging. Good transformer bias-to-output-winding coupling results in reduced overshoot and better voltage tracking. The startup current source transitions to a resistance as DD1 V C falls below but will start the converter from V adapters within t ST DD1 10.2, V~85 ms). The bootstrap source provides reliable startup from widely varying input voltages, and eliminates the continual power loss of external resistors. The startup current source will not charge above the maximum recommended V VC if the converter is disabled and there is sufficient V DD1 to charge higher. The peak current limit does not have duty cycle dependency unless R S is used as shown in Figure to increase slope compensation. This makes it easier to design the current limit to a fixed value. The TPS23753 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This aviods current-sense waveform distortion, which tends to get worse at light output loads. While the internally set blanking period is relatively precise, almost all converters will require their own blanking period. The TPS23753 provides the BLNK pin to allow this programming. There may be some situations or designers that prefer an R-C approach. The TPS23753 provides a pull-down on CS during the GATE off time to improve sensing when an R-C filter must be used. The CS input signal should be protected from nearby noisy signals like GATE drive and the MOSFET drain. Converters require a softstart on the voltage error amplifier to prevent output overshoot on startup. Figure shows a common implementation of a secondary-side softstart that works with the typical TL431 error amplifier shown in Figure This secondary-side error amplifier will not become active until there is sufficient voltage on the secondary. The TPS23753 provides a primary-side softstart which persists long enough (~800 µ for secondary side voltage-loop softstart to take over. The primary-side current-loop softstart controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second PWM control input. Figure shows an exaggerated handoff between the primary and secondary-side softstart that is most easily seen in the I PI waveform. The output voltage rises in a smooth monotonic fashion with no overshoot. This handoff can be optimized by decreasing the secondary-side softstart period. Figure 21. Example of Softstart Circuit Added to Error Amplifier The dc/dc controller has an OTSD that can be triggered by heat sources including the V B regulator, GATE driver, bootstrap current source, and bias currents. The controller OTSD turns off V B the GATE driver, resets the softstart generator, and forces the V C control into an under-voltage state. Special care must be used in selecting the converter switching MOSFET. The TPS23753 converter section has minimum V C operating voltage of ~5.5 which is reflected in the applied gate voltage. This will occur during an output overload, or towards the end of a (failed) bootstrap startup. The MOSFET must be able to carry the anticipated peak fault current at this gate voltage. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

R BLNK ( ) ( )BLNK BLNKR k t nsΩ = (5) Current Slope Compensation TPS23753 SLVS853A JUNE 2008 REVISED JUNE 2008 www.ti.com Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations assume that the TPS23753 is the only heat source contributing to the PCB temperature rise. It is possible for a normally operating TPS23753 device to experience an OTSD event if it is excessively heated by a nearby device. The TPS23753 BLNK feature permits programming of the blanking period with specified tolerance. Selection of the blanking period is often empirical because it is affected by parasitics and thermal effects of every device between the gate-driver and output capacitors. There is a critical range of blanking period that is bounded on the short side by erratic operation, and on the long side by potentially harmful switching-MOSFET and output rectifier currents during a short circuit. The minimum blanking period prevents the current limit and PWM comparators from being falsely triggered by the inherent current spike that occurs when the switching MOSFET turns on. The maximum blanking period is bounded by the output rectifier's ability to withstand the currents experienced during a converter output short. A short on the flyback transformer secondary will cause very large peak MOSFET currents that are worsened by longer blanking periods. A long blanking time also increases the minimum load required before cycle skipping occurs in a non-synchronous converter. The TPS23753 provides a choice between internal fixed and programmable blanking periods. The blanking period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and the programmable period is set with a resistor from BLNK to RTN per the following equation. For example, a 100 ns period is programmed by a 100 k Ω resistor. For a brand-new design, it is recommended that an initial blanking period of 125 ns be designed in. This period should be be tuned once the converter is operational. Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer) current for stability at duty cycles near and over 50%. The TPS23753 has a maximum duty cycle limit of 80%, permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers. While the maximum duty cycle is 80%, converters may be designed that run at duty cycles well below 80% for a narrower, V to V range. The TPS23753 provides a fixed internal compensation ramp that suffices for most applications. R S (see Figure may be used if the internally provided slope compensation is not enough. It works with ramp current PK I SL-EX ~40 µ that flows out of the CS pin when the MOSFET is on. The I PK specification does not include the µ A fixed current that flows out of the CS pin. Most current-mode control papers and application notes define the slope values in terms of V PP S (peak ramp voltage switching period), however the electrical characteristics table specifies the slope peak SLOPE based on an 80% duty cycle. Assuming that the desired slope, V SLOPE-D (in mV/period), is based on the full period, compute R S per the following equation where V SLOPE D MAX and I SL-EX are from the electrical characteristics table with voltages in mV, current in µ and the duty cycle is unitless (e.g. D MAX 0.8). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

( )( ) ( ) 1000( ) SLOPE SLOPE D MAX S SL EX V mVV mV D R I A µ RCS GATE CS RTN RS CS5/09/08 FRS and Synchronization 15000( ) ( ) FRS SW R k f kHz Ω = RTN FRSRFRS 47pF Synchronization Pulse 4/30 /08 VSYNC TSYNC RTN FRS RFRS 47pF Synchronization Puls e 4/3 0/08 VSYNC TS YNC 1:1 1000pF Example: Pulse PA0184 Adapter ORing TPS23753 www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 Figure 22. Additional Slope Compensation C S may be required if the presence of R S causes increased noise, due to adjacent signals like the gate drive, to appear at the C S pin. The TPS23753 has an internal pull-down on C S ~500 Ω while the MOSFET is OFF to reduce cycle-to-cycle carry-over voltage on C S The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the TPS23753 converter to a higher frequency. The internal oscillator sets the maximum duty cycle at 80% and controls the current-compensation ramp circuit. R FRS should be selected per the following equation. The TPS23753 may be synchronized to an external clock to eliminate beat frequencies from a sampled system, or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by applying a short pulse ns) of magnitude V SYNC to FRS as shown in Figure R FRS should be chosen so that the maximum free-running frequency is just below the desired synchronization frequency. The synchronization pulse terminates the potential on-time period, and the off-time period doesn t begin until the pulse terminates. A short pulse is preferred to avoid reducing the potential on-time. Figure shows examples of non-isolated and transformer-coupled synchronization circuits The pulse at the FRS pin should reach between 2.5 V and V B with a minimum width of ns (above 2.5 and rise/fall times less than ns. The FRS node should be protected from noise because it is high-impedance. Figure 23. Synchronization Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

0.1uF R DEN R CLS From EthernetTransformers V DD VSS CLS DEN Low Voltage Output RTN From Spare Pairs or Transformers Power Circuit Adapter Option 3 Adapter Option 2 Adapter Option 1 V DD1 Optional for PoE Priority 5/8/08 TPS23753 SLVS853A JUNE 2008 REVISED JUNE 2008 www.ti.com installation. While most present, the TPS23753 supports forced operation from either of the power sources. Figure illustrates three options for diode ORing external power into a PD. Only one option would be used in any particular design. Option applies power to the TPS23753 PoE input, option applies power between the TPS23753 PoE section and the power circuit, and option applies power to the output side of the converter. Each of these options has advantages and disadvantages. A detailed discussion of the TPS23753 and ORing solutions is covered in application note Advanced Adapter ORing Solutions using the TPS23753 literature number SLVA306 Figure 24. ORing Configurations Preference of one power source presents a number of challenges. Combinations of adapter output voltage (nominal and tolerance), power insertion point, and which source is prefered determine solution complexity. Several factors which add to the complexity are the natural high-voltage selection of diode ORing (the simplest method of combining sources), the current limit implicit in the PSE, and PD inrush and protection circuits (necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the combinations. However the TPS23753 offers several built-in combinations. Several examples will demonstrate the limitations inherent in ORing solutions. Diode ORing a V adapter with PoE (option presents the problem that either source might be higher. A blocking switch would be required to assure which source was active. A second example is combining a V adapter with PoE using option The converter will draw approximately four times the current at V from the adapter than it does from PoE at Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must be turned off while C IN capacitance charges, with a subsequent converter restart at the higher voltage and lower input current. A third example is use of a V adapter with ORing option The PD hotswap would have to handle four times the current, and have the resistance (be times larger) to dissipate equal power. A fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power from the PD. If ac power is then lost, the PD will stop operating until the PSE detects and powers the PD. The most popular preferential ORing scheme is option with adapter priority. The hotswap MOSFET is disabled when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution works well with a wide range of adapter voltages, is simple, and requires few external parts. When the ac power fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD will momentarily loose power until the PSE completes its startup cycle. The DEN pin can be used to disable the PoE input when ORing with option This is an adapter priority implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven from the secondary side of the converter. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

49.9kΩ 10kΩ4.99kΩ 6.04kΩ 10kΩ 0.01µ F 301kΩ 1uF VB To FRS RTN TL331IDBV Design Procedure TPS23753 www.ti.com SLVS853A JUNE 2008 REVISED JUNE 2008 The least popular technique is PoE priority. It is implemented by placing a diode between the PD supply voltage, V DD and the dc/dc controller bias voltage, V DD1 The diode prevents reverse biasing of the PoE input diode bridges when option adapter ORing is used. The PSE may then detect, classify, and provide power to the PD while a live adapter is connected. As long as the PoE voltage is greater than the adapter voltage, the PSE will power the load. The APD function is not used in this technique. The IEEE standards require that the Ethernet cable be isolated from ground and all other system potentials. The adapter must meet a minimum 1500 Vac dielectric withstand test between the output and all other connections for options and The adapter only needs this isolation for option if it is not provided by the converter. Adapter ORing diodes are shown for all the options to protect against a reverse voltage adapter, a short on the adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in option A TVS across the rectified PoE voltage per Figure must be used. An SMAJ58A, or a part with equal to or better performance, is recommended for general indoor applications. If an adapter is connected from V DD1 to RTN, as in ORing option above, voltage transients caused by the input cable inductance ringing with the internal PD capacitance can occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the absolute maximum ratings Outdoor standards. The international standard CISPR (and adopted versions) is often used as a requirement for conducted emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions. Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE Powered Device With Isolated Flyback TI literature number SLUA469 Additionally, IEEE802.3-2005 section 33.4 has requirements for noise injected onto the Ethernet cable based on compatibility with data transmission. Occasionally, a technique referred to as frequency dithering is utilized to provide additional EMI measurement reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider bandwidth, thus lowering peak measurements. The circuit of Figure modulates the switching frequency by feeding a small ac signal into the FRS pin. These values may be adapted to suit individual needs. Figure 25. Frequency Dithering A detailed design procedure for PDs using the TPS23753 is covered in Designing with the TPS23753 Powered Device and Power Supply Controller literature number SLVA305 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS23753

www.ti.com IEEE Standard for Information Technology Part Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications IEEE Computer Society, IEEE 802.3 -2005 (Clause 33) Information technology equipment Radio disturbance characteristics Limits and methods of measurement International Electrotechnical Commission, CISPR Edition 5.2, 2006-03 Designing with the TPS23753 Powered Device and Power Supply Controller Eric Wright, TI, SLVA305 Advanced Adapter ORing Solutions using the TPS23753 Eric Wright, TI, SLVA306 Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated Flyback Donald Comiskey, TI, SLUA469 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS23753

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS23753PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS23753PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS23753PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS23753PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS23753PWR TSSOP PW 14 2000 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2008 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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Summary

IEEE 802.3-2005 PoE INTERFACE AND ISOLATED CONVERTER CONTROLLER

Description