TP11362

TP11362A NSC | Alldatasheet

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n CCITT G.726 compatible at 40, 32, 24, 16 kbps n ANSI T1.301 compatible at 32 kbps n 8-channel half-duplex (encode or decode) or 4-channel full-duplex operation in 8 kHz frame n Each channel individually configurable n Selectable µ-law or A-law PCM coding n Asynchronous 8 MHz master clock operation n TTL and CMOS compatible inputs and outputs n 28-pin PLCC or 24-pin DIP packages n Power consumption of typ. 6 mW at +5V per full-duplex channel n On-Chip Power-On-Reset n −40˚C to +85˚C operating temperature range n Single 5V supply Block Diagram TRI-STATE® and COMBO ® are registered trademarks of National Semiconductor Corporation. DS012877-1 FIGURE 1. Block Diagram

Transmit PCM serial data input. TSI is an 8-bit PCM data stream and is shifted into an 8-bit serial-to-parallel register on the falling edges of PSCK while CE and TRB are high. The last 8 bits of TSI are latched and transferred to the core for processing at the falling edge of CE. TSO Transmit ADPCM TRI-STATE ® serial data output. A serial data bit stream of 4- to 5-bit length is shifted out with the ris- ing edge of ASCK when CE is high following the processing of a transmit channel. TSO is in TRI-STATE mode while CE is low or while RSO output is active. RSI Receive ADPCM serial data input. A serial data bit stream of 4- to 5-bit length is shifted in with the falling edges of ASCK while CE is high and TRB is low. The last 4 or 5 bits of RSI are latched and transferred to the core for processing at the falling edge of CE. RSO Receive PCM TRI-STATE serial data output. An 8-bit serial PCM data stream is shifted out with the rising edges of PSCK when CE is high following the processing of a receive channel. RSO is in TRI-STATE mode while CE is low or while TSO output is active. PSCK PCM serial clock input. PSCK is used to shift PCM data into TSI or out of RSO while CE is active (high). The transfer de- pends on the logic state of TRB. ASCK ADPCM serial clock input. ASCK is used to shift ADPCM data into RSI or out of TSO while CE is active (high). The transfer depends on the logic state of TRB. CLK Master clock input. CLK may be asynchronous to PSCK or ASCK. CE Chip enable input. When CE is high, it enables data transfer. The falling edge of CE latches and transfers the serial data TSI or RSI to the core for processing and strobes the control signals QSEL0, QSEL1, PCM1, EN and INIT. CE should change state only when PSCK and ASCK are high. CE, when low, sets the TSO and RSO outputs into TRI-STATE mode. TRB Transmitter or receiver select. A logic low at TRB selects the receiver of the channel processed. A logic high enables the transmitter of the channel processed. TRB determines which input register is enabled and which output register and out- put is enabled. TRB should be stable while CE is high. EN Channel enable input. EN is strobed in with the falling edge of CE. A logic high at the falling edge of CE indicates that the channel is active, and the ADPCM will process the data just clocked in. INIT Channel initialization input. INIT is read at the falling edge of CE. A logic high at the falling edge of CE causes the ADPCM processor to initialize the channel currently processing. PCM1 PCM coding law select. A logic low at PCM1 selects 8-bit µ-law, while a logic high selects 8-bit A-law with even bit in- version. Plastic Chip Carriers DS012877-2 Top View Order Number TP11362AV See NS Package Number V28A Plastic Dual-In-Line DS012877-3 Top View Order Number TP11362AN See NS Package Number N24A www.national.com 2

be pulled high for normal operation. tied low for normal operation. CC1 and GND1, and VCC2 and GND2. TABLE 1. Bit Rate Selection tively, to the value of the difference signal for transmission. speech and voice band data signals. put with the rising edges of PSCK. cycle of CE at the TSO output with the rising edges of ASCK. clock cycles required for processing the data. TABLE 2. Processing Cycles must be low for more than 4 CLK cycles.

ASCK need only be valid while CE is high. FIGURE 3. Serial Output Structure

FIGURE 4. Full Duplex Timing Diagram (40 kbps ADPCM mode)

FIGURE 5. Full Duplex Timing Diagram (32 kbps ADPCM mode)

with the rising edges of ASCK and PSCK respectively. Table 4shows the transfer order of the ADPCM output data. ADPCM data, the ADPCM output will recirculate. TABLE 3. Transfer Order of ADPCM Input Data (RSI). The Last Bit Prior TABLE 4. Transfer Order of ADPCM Output Data (TSO) with 4 ASCK Rising Edges TABLE 5. Transfer Order of ADPCM Output Data (TSO) the ITU G.726 recommendation. .The minimum low time of RSTB is 2 CLK cycles. after the completion of the initialization.

quires 4 CLK cycles for CE to maintain all channel variables. served during this time by disabling the internal registers. TABLE 6. TSO at Channel NOP TABLE 7. RSO at Channel NOP

Absolute Maximum Ratings (Note *NO TGT: FNXref NS0465*) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V CC to GND 7V Voltage at Any Digital Inputs or Outputs GND − 0.3V to V CC + 0.3V Storage Temperature Range −45˚C to +125˚C Lead Temperature (Soldering, 10 sec) 300˚C Latch-up Immunity on any Pin ±75 mA θJA (28-pin PLCC) 79˚C/W θJA (24-pin DIP) 49˚C/W Unless otherwise noted, limits printed inbold characters are guaranteed forVCC = 5.0V ± 5% , GND1 = GND2 = 0V, TA = −40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. Typical values are specified at VCC = +5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units ICC0 Supply Current CLK = 8.0 MHz, RSTB = Low 1.8 mA (Power Down Mode) ICC1 Supply Current CLK = 8.0 MHz, RSTB = High 7 9 mA (Power Up Mode) PD Power Dissipation 35 mW VIL Input Low Voltage ASCK, PSCK, CE, TRB, 0.8 V VIH Input High Voltage CLK, RSTB 2.4 V VIL Input Low Voltage PCM1, RSI, TSI, QSEL0, 0.7 V VIH Input High Voltage QSEL1, INIT, EN 2.0 V VOL Output Low Voltage I L = 4m A 0.4 V VOH Output High Voltage I L = −4 mA 2.4 V IL = −0.4 mA; VCC = 4.75V VCC − 0.8 V IIL Input Low Current GND < VIN < VIL, All Signal Inputs −10 µA IIH Input High Current V IH < VIN < VCC , All Signal Inputs 10 µA Test Inputs TST0, TST1, TST2 (Note 4) 150 µA IOZ Output Current in High GND < VO < VCC , TSO and RS0 −10 10 µA Impedance State C I Input Capacitance 10 pF C O Output Capacitance 10 pF C L Capacitive Load 100 pF Note 4:Test inputs have internal pull-down resistor. Timing Specifications Unless otherwise noted, limits printed inbold characters are guaranteed for VCC = 5.0V ± 5% , GND1 = GND2 = 0V, TA = −40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. Typical values are specified at VCC = +5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units fCLK CLK Frequency (Note 5) Assuming 50 % Duty Cycle 7.9 8.0 16 MHz tCLK CLK Duty-Cycle 40 % 50% 60% CLK Period tR Rise Time (CLK, CE, 10 ns ASCK, PSCK) tF Fall Time (CLK, CE, 10 ns ASCK, PSCK) tCEP CE Period Encode or Decode 123 CLK Initialization 45 Cycles Disable 9 t CEL CE Pulse Width, Low 4 CLK Cycles www.national.com 10

Timing Specifications(Continued) Unless otherwise noted, limits printed inbold characters are guaranteed for VCC = 5.0V ± 5% , GND1 = GND2 = 0V, TA = −40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. Typical values are specified at VCC = +5V, TA = 25˚C. Symbol Parameter Conditions Min Typ Max Units tHDCEL Hold Time, CE low after From CE Low 15 ns PSCK/ASCK High t SUCEH Setup Time, CE High Before From CE Low 15 ns PSCK/ASCK Low t TRBH TRB Hold Time From CE Low 20 ns tTRBS TRB Setup Time From ASCK Low and PSCK Low 20 ns tIS TSI, RSI Setup Time From ASCK Low and PSCK Low 20 ns tIH TSI, RSI Hold Time From ASCK Low and PSCK Low 20 ns tPSCK/ASCK PSCK/ASCK High and 55 ns Low Times t ON TSO, RSO Turn On Time From CE High 40 ns tOD TSO, RSO Propagation From ASCK High or PSCK High 40 ns Delay Time tOFF TSO, RSO Turn Off Time From CE Low 20 ns (Valid Data to TRI-STATE) tCS Setup Time for Control From CE Low Signals (INIT, EN, 20 ns PCM1, QSEL1, QSEL0) t CH Hold Time for Control From CE Low Signals (INIT, EN, 20 ns PCM1, QSEL1, QSEL0) t RSTL RSTB Pulse Width Low 2 CLK Cycles tRSTH RSTB High to the First 6 CLK CE High-Low Transition Cycles Note 5:Values for 4 full-duplex (decoding and encoding) or 8 half-duplex (decoding or encoding) channels operation in a 125 µs period. 11 www.national.com

FIGURE 6. ADPCM Timing

FIGURE 7. Typical Application in an ISDN Pair Gain System

Note 6: The duty cycle of CE can be adjusted to adapt to different PCM data bit clocks of the COMBO. Note 7: The DX data output is shown with the long frame sync mode (non-delayed data timing mode). FIGURE 8. Example of a Timing Interface between an ADPCM and a COMBO

Physical Dimensionsinches (millimeters) unless otherwise noted 24-Lead (0.600" Wide) Molded Dual-In-Line Package Order Number TP11362AN 15 www.national.com

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 28-Lead Molded Plastic Leaded Chip Carrier Order Number TP11362AV TP11362A Quad Adaptive Differential PCM Processor National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.